Datasheet FDP8896 Datasheet (Fairchild)

N

May 2008

FDP8896

FDP8896

N-Channel PowerTrench® MOSFET
30V, 92A, 5.9mΩ

General Description

This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
r

and fast switching speed.

DS(ON)

Applications

• DC/DC converters

(FLANGE)

DRAIN

TO-220AB

FDP SERIES

MOSFET Maximum Ratings T

Symbol Parameter Ratings Units

V
V

I

E
P
T

D

DSS
GS

AS

D

, T

J

STG

Drain to Source Voltage 30 V
Gate to Source Voltage ±20 V
Drain Current
Continuous (T
Continuous (T
Continuous (T

= 25oC, VGS = 10V) (Note 1)

C

= 25oC, VGS = 4.5V) (Note 1) 85 A

C

= 25oC, VGS = 10V, with R

amb

Pulsed Figure 4 A
Single Pulse Avalanche Energy (Note 2) 74 mJ
Power dissipation 80 W
Derate above 25

o

C0.53W/

Operating and Storage Te mperature -55 to 175

SOURCE

DRAIN

GATE

= 25°C unless otherwise noted

C

Features

•r

•r

• High performance trench technology for extremely low

• Low gate charge

• High power and current handling capability

•

RoHS Compliant

= 62oC/W) 16 A

θJA

DS(ON)

DS(ON)

r

DS(ON)

= 5.9mΩ, V
= 7.0mΩ, V

G

= 10V, ID = 35A

GS

= 4.5V, ID = 35A

GS

D

S

92 A

tmM

o

o

C

C

Thermal Characteristics

R

θJC

R

θJA

Thermal Resistance Junction to Case TO-220 1.88
Thermal Resistance Junction to Ambient TO-220 ( Note 3) 62

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDP8896 FDP8896 TO-220AB Tube N/A 50 units

©2008 Fairchild Semiconductor Corporation

o

C/W

o

C/W

FDP8896 Rev. A2

FDP8896

Electrical Characteristics T

= 25°C unless otherwise noted

C

Symbol Parameter Tes t Cond itions Min Typ Max Units

Off Characteristics

B

VDSS

I

DSS

I

GSS

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V

V

= 24V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC - - 250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1.2 - 2.5 V

I

= 35A, VGS = 10V - 0.0050 0.0059

D

= 35A, VGS = 4.5V - 0.0060 0.0070

I

Drain to Source On Resistance

D

I

= 35A, VGS = 10V,

D

= 175oC

T

J

- 0.0078 0.0094

Dynamic Characteristics

C

ISS

C

OSS

C

RSS

R

G

Q

g(TOT)

Q

g(5)

Q

g(TH)

Q

gs

Q

gs2

Q

gd

Input Capacitance
Output Capacitance - 490 - pF
Reverse Transfer Capacitance - 300 - pF

= 15V, VGS = 0V,

V

DS

f = 1MHz

Gate Resistance VGS = 0.5V, f = 1MHz - 2.3 - Ω
Total Gate Charge at 10V VGS = 0V to 10V
Total Gate Charge at 5V VGS = 0V to 5V - 25 36 nC

V

= 15V

Threshold Gate Charge VGS = 0V to 1V - 2.3 3.0 nC
Gate to Source Gate Charge - 8 - nC
Gate Charge Threshold to Plateau - 5.7 - nC

DD

= 35A

I

D

= 1.0mA

I

g

Gate to Drain “Miller” Charge - 9.5 - nC

- 2525 - pF

-4867nC

µA

Ω

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 9 - ns
Rise Time - 103 - ns
Turn-Off Delay Time - 56 - ns
Fall Time - 44 - n s
Turn-Off Time - - 150 ns

(VGS = 10V)

Drain-Source Diode Characteristics

V

SD

t

rr

Q

RR

Notes:
1: Package current limitation is 80A.
2: Starting T
3: Pulse width = 100s.
4

Source to Drain Diode Voltage
Reverse Recovery Time ISD = 35A, dISD/dt = 100A/µs- -27ns

Reverse Recovered Charge ISD = 35A, dISD/dt = 100A/µs- -12nC

= 25°C, L = 36µH, IAS = 64A, VDD = 27V, VGS = 10V.

J

- - 168 ns

= 15V, ID = 35A

V

DD

= 4.5V, RGS = 6.2Ω

V

GS

I

= 35A - - 1.25 V

SD

I

= 20A - - 1.0 V

SD

©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

FDP8896

Typical Characteristics T

= 25°C unless otherwise noted

C

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULT IPL I ER

0

0 25 50 75 100 175

125

150

TC, CASE TEMPERATURE (oC)

Figure 1. Normali ze d Po we r Dis sip ation vs Case

Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

100

CURRENT LIMITED
BY PACKAGE

80

VGS = 10V

60

VGS = 4.5V

40

, DRAIN CURRENT (A)

D

I

20

0

25 50 75 100 125 150

175

TC, CASE TEMPERATURE (oC)

Figure 2. Maximum Contin uous Drain Current vs

Case Temperature

P

DM

t

1

t

x R

θJC

+ T

2

C

1

10

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-2

10

-1

10

θJC

10

1/t2

0

Figure 3. Normalized Maximum Transient Thermal Impedance

1000

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

VGS = 4.5V

, PEAK CURRENT (A)

DM

I

100

50

-5

10

-4

10

-3

10

-2

10

-1

10

t, PUL SE WIDTH (s)

TC = 25oC
FOR TEMPERATURES

o

ABOVE 25

C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

10

C

150

0

1

10

Figure 4. Peak Current Capability

©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

FDP8896

Typical Characteristics T

1000

100

10

OPERATION IN THIS

AREA MAY BE

, DRAIN CURRENT (A)

D

I

LIMITED BY r

1

SINGLE PULSE
TJ = MAX RATED

= 25oC

T

C

0.1
110

DS(ON)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

= 25°C unless otherwise noted

C

Figure 5. Forward Bias Safe Operating Area

160

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

V

= 15V

DD

120

TJ = 25oC

80

, DRAIN CURRENT (A)

D

I

40

TJ = 175oC

0

1.5 2.0 2.5 3.0 3.5
VGS, GATE TO SOURCE VOLTAGE (V)

TJ = -55oC

10µs

100µs

1ms

10ms

DC

500

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

100

10

, AVALANCHE CURRENT (A)

AS

I

60

1

0.01 0.1 1 10 100

STARTING TJ = 150oC

tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Applica ti on Note s AN75 14 and AN75 15

Figure 6. Unclamped Inductive Switching

Capability

160

VGS = 10V

120

80

, DRAIN CURRENT (A)

D

I

40

0

4

0 0.25 0.5 0.75 1.0 1.25 1.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 4V

TC = 25oC

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 5V

VGS = 3V

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

14

ID = 35A

12

10

8

, DRAIN TO SOURCE

ON RESISTANCE (mΩ)

DS(ON)

r

6

ID = 1A

4

246810

V

, GATE TO SOURCE VOLTAGE (V)

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

Figure 9. Drain to Source On Resis tanc e vs Ga te

Voltage and Drain Current

©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

1.6

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.4

1.2

1.0

ON RESISTANCE

0.8

NORMALIZED DRAIN TO SOURCE

0.6

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 35A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDP8896

Typical Characteristics T

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

C

VGS = VDS, ID = 250µA

Figure 11. Normalized Gate Thresho ld Voltage vs

Junction Temperature

5000

1000

C

= C

RSS

GD

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

100

0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)

C

ISS

C

OSS

= CGS + C

≅ C

DS

+ C

GD

GD

30

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200
T

, JUNCTION TEMPERATURE (oC)

J

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 15V

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 1020304050

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 35A
I

= 16A

D

Figure 13. Capacitance vs Drain to Source

Voltage

©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

Figure 14. Gate Charge Waveforms for Constant

Gate Current

Test Circuits and Waveforms

V

DS

L

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

I

AS

DUT

t

0V

P

I

AS

0.01Ω

0

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

DS

V

DD

V

Q

I

g(REF)

L

V

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

= 1V

Q

gs2

Q

g(TH)

Q

gs

0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

BV

DSS

t

P

t

AV

Q

g(TOT)

DS

Q

g(5)

V

GS

VGS = 5V

gd

FDP8896

V

DS

V

DD

V

= 10V

GS

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

t

d(OFF)

90%

t

OFF

t

f

90%

10%

50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

PSPICE Electrical Model

.SUBCKT FDP8896 2 1 3 ; rev November 2003

FDP8896

Ca 12 8 2.3e-9
Cb 15 14 2.3e-9
Cin 6 8 2.3e-9

DPLCAP

10

Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 33
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1

GATE

1

LGATE

RLGATE

RGATE

9

EVTEMP
+

20

ESG

18
22

RSLC2

­6

8

EVTHRES

+

+

19

8

6

-

Lgate 1 9 5.5e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.7e - 9

RLgate 1 9 55
RLdrain 2 5 10
RLsource 3 7 27

Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

CA

S1A

12

S1B

S2A

13

14

8

13

S2B

13

+

+

6

EGS EDS

8

-

-

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.3e-3
Rgate 9 20 2.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}

15

CIN

CB

-

+

-

5

51

5

51

21

MSTRO

14

5
8

RSLC1

+

ESLC

­50

RDRAIN

16

8

MMED

8

DBREAK

11

+

17

EBREAK

IT

18

-

MWEAK

RSOURCE

RBREAK

17 18

RVTHRES

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

.MODEL DbodyMOD D (IS=4E-12 IKF=10 N=1.01 RS=2.6e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=8.8e-10 M=0.57 TT=1e-16 XTI=2.2)
.MODEL Dbrea kM O D D ( R S=8e-2 TRS1=1e- 3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=9.4e-10 IS=1e-30 N=10 M=0.4)

.MODEL MmedMOD NMOS (VTO=1.98 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.3 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=2.4 KP=350 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=1.68 KP=0.05 IS=1e-30 N=10 T OX=1 L=1u W=1u RG=23 RS=0.1 T_ABS=25)

.MODEL RbreakMOD RES (TC1 =8.3e-4 TC2=-4e-7)
.MODEL RdrainMOD RES (TC1=1e-3 TC2=8e-6)
.MODEL RSLCMOD RES (TC1=9e -4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=7.5e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2.4e-3 TC2=-8.8e-6)
.MODEL RvtempMOD RES (TC1=- 2.6e-3 TC2=2e-7)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)
.ENDS

Note: For further discussio n of the PSP ICE mode l, consul t A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Confere nce Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

SABER Electrical Model

rev November 2003
template FDP8896 n2,n1,n3 =m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=4e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-16,xti=2.2)
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=9.4e-10,isl=10e-30,nl=10,m=0.4)
m..model mmedmod = (type=_n,vto=1.98,kp=10, is=1e-30, tox=1)
m..model mstrong mod = (type=_n,vto=2.4,k p=350,is=1e-30, tox=1 )
m..model mweakmod = (type=_n,vto=1.68,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2)
c.ca n12 n8 = 2.3e-9
c.cb n15 n14 = 2.3e-9
c.cin n6 n8 = 2.3e-9

dp.dbody n7 n5 = model= dbodymod
dp.dbreak n5 n11 = model=dbreakmod

ESG

dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 33

spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1

GATE

1

LGATE

RLGATE

RGATE

9

EVTEMP
+

18
22

20

spe.evthres n6 n 21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1
l.lgate n1 n9 = 5.5e-9

l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.7e-9

CA

S1A

12

S1B

res.rlgate n1 n9 = 55
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 27

m.mmed n16 n6 n8 n8 = model=mmed mod, l=1u, w=1u, temp=m_temp
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp

res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-4e-7
res.rdrain n50 n16 = 2.3e-3, tc1=1e-3,tc2=8e-6
res.rgate n9 n20 = 2.3
res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2e-3, tc1=7.5e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-2.4e-3,tc2=-8.8e- 6
res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

19

8

6

-

S2A

14

13

13

8

S2B

13

+

+

6

EGS EDS

8

-

-

15

CIN

CB

-

+

-

5

MSTRO

14

5
8

RSLC1

51

ISCL

50
RDRAIN

16

21

8

MMED

8

DBREAK

11

MWEAK

EBREAK

+

-

RSOURCE

RBREAK

17 18

IT

RVTHRES

17
18

7

RVTEMP
19

-

+

22

RLDRAIN

LSOURCE

RLSOURCE

VBAT

LDRAIN

DBODY

DRAIN

2

SOURCE

3

FDP8896

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))

}
}

©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

FDP8896

PSPICE Thermal Model

REV 23 Novemb er 20 03
FDP8896T
CTHERM1 TH 6 9e-4

CTHERM2 6 5 1e-3
CTHERM3 5 4 2e-3
CTHERM4 4 3 3e-3
CTHERM5 3 2 7e-3
CTHERM6 2 TL 8e-2

RTHERM1 TH 6 3.0e-2
RTHERM2 6 5 1.0e-1
RTHERM3 5 4 1.8e-1
RTHERM4 4 3 2.8e-1
RTHERM5 3 2 4.5e-1
RTHERM6 2 TL 4.6e-1

SABER Thermal Model

SABER thermal model FDP8896T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =9e-4
ctherm.ctherm2 6 5 =1e-3
ctherm.ctherm3 5 4 =2e-3
ctherm.ctherm4 4 3 =3e-3
ctherm.ctherm5 3 2 =7e-3
ctherm.ctherm6 2 tl =8e-2

rtherm.rtherm1 th 6 =3.0e-2
rtherm.rtherm2 6 5 =1.0e-1
rtherm.rtherm3 5 4 =1.8e-1
rtherm.rtherm4 4 3 =2.8e-1
rtherm.rtherm5 3 2 =4.5e-1
rtherm.rtherm6 2 tl =4.6e-1
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

RTHERM6

2

CTHERM6

tl

CASE

©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

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®

tm

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®

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™

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FAST
FastvCore™
FlashWriter

®

®

®

®

®

*

* EZSWITCH™ and FlashWriter

FPS™
F-PFS™

®

FRFET
Global Power Resource
Green FPS™
Green FPS™ e-Series™
GTO™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MillerDrive™
MotionMax™
Motion-SPM™
OPTOLOGIC
OPTOPLANAR

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®

are trademarks of System General Corporation, used under license by Fairchild Semiconductor.

®

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PDP-SPM™
Power-SPM™
PowerTrench

SM

Programmable Active Droop™
QFET

®

®

QS™
Quiet Series™
RapidConfigure™
Saving our world 1mW at a time™
SmartMax™
SMART START™

®

SPM
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SuperMOS™

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The Power Franchise

TinyBoost™
TinyBuck™
TinyLogic

®

TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™

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UHC
Ultra FRFET™
UniFET™
VCX™
VisualMax™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

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LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body or (b)
support or sustain life, and (c) whose failure to perform when
properly used in accordance with instructions for use provided

2. A critical component in any component of a life support,
device, or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.

in the labeling, can be reasonably expected to result in a
significant injury of the user.

PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design

This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.

This datasheet contains preliminary data; supplementary data will be pub-

Preliminary First Production

lished at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.

No Identification Needed Full Production

Obsolete Not In Production

@2008 Fairchild Semiconductor Corporation FDP8896 Rev.A2

This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve the design.

This datasheet contains specifications on a product that is discontinued by
Fairchild Semiconductor. The datasheet is for reference information only.

Rev. I34