Datasheet FDB20AN06A0, FDP20AN06A0 Datasheet (Fairchild)

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FDB20AN06A0 / FDP20AN06A0

N-Channel PowerTrench® MOSFET
60V, 45A, 20mΩ

FDB20AN06A0 / FDP20AN06A0

June 2003

Features

•r

•Q

• Low Miller Charge

•Low Q

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

Formerly developmental type 82547

DRAIN

(FLANGE)

MOSFET Maximum Ratings T

= 17mΩ (Typ.), V

DS(ON)

(tot) = 15nC (Typ.), V

g

Body Diode

RR

= 10V, ID = 45A

GS

= 10V

GS

TO-2 20 AB

FDP SERIES

DRAIN

GATE

SOURCE

= 25°C unless otherwise noted

C

Applications

• Motor / Body Load Control

• ABS Systems

• Powertrain Management

• Injection Systems

• DC-DC converters and Off-line UPS

• Distributed Power Architectures and VRMs

• Primary Switch for 12V and 24V systems

GATE

SOURCE

TO-2 63 AB

FDB SERIES

DRAIN

(FLANGE)

D

G

S

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Source Voltage 60 V

Gate to Source Voltage ±20 V

Drain Current

Continuous (T

I

D

Continuous (T

Continuous (T

= 25oC, VGS = 10V)

C

= 100oC, VGS = 10V) 32 A

C

= 25oC, VGS = 10V, R

amb

= 43oC/W) 9 A

θJA

45 A

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse Avalanche Energy ( Note 1) 50 mJ

Power dissipation 90 W

o

Derate above 25

C0.60W/

Operating and Storage Temperature -55 to 175

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a

All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

©2003 Fairchild Semiconductor Corporation

Thermal Resistance Junction to Case TO-220, TO-263 1.67

Thermal Resistance Junction to Ambient TO-220, TO-263 ( Note 2) 62

Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 43

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

certification.

FDB20AN06A0 / FDP20AN06A0 Rev. B

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDB20AN06A0 FDB20AN06A0 TO-263AB 330mm 24mm 800 units

FDP20AN06A0 FDP20AN06A0 TO-220AB Tube N/A 50 units

FDB20AN06A0 / FDP20AN06A0

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B

I

DSS

I

GSS

VDSS

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 60 - - V

V

= 50V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- -250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

= 45A, VGS = 10V - 0.017 0.020

I

Drain to Source On Resistance

D

I

= 45A, VGS = 10V,

D

T

= 175oC

J

- 0.039 0.047

Dynamic Characteristics

C

C

C

Q

Q

Q

Q

Q

ISS

OSS

RSS

g(TOT)

g(TH)

gs

gs2

gd

Input Capacitance

Output Capacitance - 185 - pF

Reverse Transfer Capacitance - 60 - pF

Total Gate Charge at 10V VGS = 0V to 10V

Threshold Gate Charge VGS = 0V to 2V - 2 2.6 nC

Gate to Source Gate Charge - 6 - nC

Gate Charge Threshold to Plateau - 4 - nC

Gate to Drain “Miller” Charge - 4.5 - nC

Switching Characteristics (V

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time

Turn-On Delay Time - 11 - ns

Rise Time - 98 - ns

Turn-Off Delay Time - 23 - ns

Fall Time - 33 - ns

Turn-Off Time - - 84 ns

GS

= 10V)

= 25V, VGS = 0V,

V

DS

f = 1MHz

V

= 30V, ID = 45A

DD

V

= 10V, RGS = 20Ω

GS

V

DD

I

= 45A

D

I

= 1.0mA

g

= 30V

-950- pF

15 19 nC

--164ns

µA

Ω

Drain-Source Diode Characteristics

I

= 45A - - 1.25 V

V

SD

t

rr

Q

RR

Notes:
1: Starting TJ = 25°C, L = 80µH, IAS = 36A.
2: Pulse width = 100s.

©2003 Fairchild Semiconductor Corporation FDB20AN06A0 / FDP20AN06A0 Rev. B

Source to Drain Diode Voltage

Reverse Recovery Time ISD = 45A, dISD/dt = 100A/µs- - 32ns

Reverse Recovered Charge ISD = 45A, dISD/dt = 100A/µs- - 25nC

SD

= 22A - - 1.0 V

I

SD

FDB20AN06A0 / FDP20AN06A0

Typical Characteristics T

= 25°C unless otherwise noted

C

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PUL SE

-4

10

10

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

150

0

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Current vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

10

TC, CASE TEMPERATURE (oC)

Case Temperature

P

DM

NOTES:
DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z

-1

10

θJC

10

0

x R

t

1

t

2

2

+ T

θJC

C

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

600

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

VGS = 10V

100

, PEAK CURRENT (A)

DM

I

40

-5

10

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

TC = 25oC

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

10

C

150

0

1

10

Figure 4. Peak Current Capability

©2003 Fairchild Semiconductor Corporation FDB20AN06A0 / FDP20AN06A0 Rev. B

FDB20AN06A0 / FDP20AN06A0

Typical Characteristics T

1000

100

10

OPERATION IN THIS

AREA MAY BE

, DRAIN CURRENT (A)

D

I

LIMITED BY r

1

SINGLE PUL SE
TJ = MAX RATED

TC = 25oC

0.1
110100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

= 25°C unless otherwise noted

C

10µs

100µs

1ms

10ms

DC

Figure 5. Forward Bias Safe Operating Area

100

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

V

= 15V

DD

80

TJ = -55oC

60

TJ = 175oC

300

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

100

tAV = (L/R)ln[(IAS*R)/(1.3*R ATED BV

10

, AVALANCHE CURRENT (A)

AS

I

1

0.01

STARTING TJ = 150oC

tAV, TIME IN AVALANCHE (ms)

0.1 1 10

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Application Not es AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

100

VGS = 20V

80

60

VGS = 10V

VGS = 7V

40

TJ = 25oC

, DRAIN CURRENT (A)

D

I

20

0

456789

VGS, GATE TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

17.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

17.0

16.5

16.0

DRAIN TO SOURCE ON RESISTANCE(mΩ)

15.5

0 1020304050

ID, DRAIN CURRENT (A)

VGS = 10V

Figure 9. Drain to Source On Resistance vs Drain

Current

40

, DRAIN CURRENT (A)

D

I

20

0

0123

2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200

VGS = 5V

VDS, DRAIN TO SOURCE VOLTAGE (V)

TJ, JUNCTION TEMPERATURE (oC)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 6V

TC = 25oC

VGS = 10V, ID = 45A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

©2003 Fairchild Semiconductor Corporation FDB20AN06A0 / FDP20AN06A0 Rev. B

FDB20AN06A0 / FDP20AN06A0

Typical Characteristics T

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 - 40 0 40 80 120 160 200

TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

C

VGS = VDS, ID = 250µA

Figure 11. Normalized Gate Threshold Voltage vs

Junction Temperature

2000

1000

C

= C

RSS

GD

C

ISS

C

OSS

= CGS + C

≅ C

DS

+ C

GD

GD

1.15
ID = 250µA

1.10

1.05

1.00

BREAKDOWN VOLTAGE

0.95

NORMALIZED DRAIN TO SOURCE

0.90

-80 -40 0 40 80 120 160 200

TJ, JUNCTION TEMPERATURE (oC)

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 30V

8

6

C, CAPACITANCE (pF)

100

V

= 0V, f = 1MHz

GS

40

0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Source

Voltage

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

60

03691215

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 45A
ID = 9A

Figure 14. Gate Charge Waveforms for Constant

Gate Current

©2003 Fairchild Semiconductor Corporation FDB20AN06A0 / FDP20AN06A0 Rev. B

Test Circuits and Waveforms

V

DS

L

VARY tP TO OBTAIN

REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

I

AS

DUT

t

0V

P

I

AS

0.01Ω

0

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

DS

V

DD

V

Q

I

g(REF)

L

V

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

= 2V

Q

gs2

Q

g(TH)

Q

gs

0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

BV

DSS

t

P

t

AV

Q

g(TOT)

DS

gd

V

GS

FDB20AN06A0 / FDP20AN06A0

V

DS

V

DD

V

= 10V

GS

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

10%

90%

PULSE WIDTH

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2003 Fairchild Semiconductor Corporation FDB20AN06A0 / FDP20AN06A0 Rev. B

Thermal Resistance vs. Mounting Pad Area

80

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and thermal resistance R

A

is never exceeded.

JM

serves as the basis for establishing the rating of the part.

TJMTA–()

P

-----------------------------=

DM

R

θ JA

In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
complex and influenced by many factors:

1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminar y application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.

DM

(oC/W)

θJA

(EQ. 1)

, in an

is

DM

60

C/W)

o

(

θJA

R

40

20

Figure 21. Thermal Resistance vs Mounting

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

(0.645) (6.45) (64.5)

AREA, TOP COPPER AREA in2 (cm2)

1100.1

Pad Area

FDB20AN06A0 / FDP20AN06A0

Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

19.84

------------- ------------- -----------+

26.51

=

R

θ JA

26.51

=

R

θ JA

©2003 Fairchild Semiconductor Corporation FDB20AN06A0 / FDP20AN06A0 Rev. B

0.262 Area+()

Area in Inches Squared

128

------------- ------------- --------+

1.69 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

PSPICE Electrical Model

.SUBCKT FDP20AN06A0 2 1 3 ; rev April 2003
Ca 12 8 4.4e-10
Cb 15 14 4.4e-10
Cin 6 8 9.2e-10

Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 67.2
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1

Lgate 1 9 6.3e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.5e-9

RLgate 1 9 63
RLdrain 2 5 10
RLsource 3 7 25

Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMO D
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1e-3
Rgate 9 20 4.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 10e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

EVTEMP

+

18
22

20

S1A

12

13814

S1B

EGS EDS

FDB20AN06A0 / FDP20AN06A0

17
18

7

+

RVTE MP

19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

6

-

S2A

13

S2B

13

+

+

6
8

-

-

5

RSLC1

51

+

5

ESLC

51

­50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5
8

-

MMED

8

DBREAK

11

+

EBREAK

-

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*150),2.7))}

.MODEL DbodyMOD D (IS=3.8E-12 N=1.06 RS=4e-3 TRS1=2.4e-3 TRS2=1.1e-6
+ CJO=6.8e-10 M=0.53 TT=2.3e-8 XTI=3.9)
.MODEL DbreakMOD D (RS=1.8 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=2.7e-10 IS=1e-30 N=10 M=0.44)

.MODEL MmedMOD NMOS (VTO=3.8 KP=2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=4.7 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=4.34 KP=35 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=3.27 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG =47 RS=0.1 T_ABS=25)

.MODEL RbreakMOD RES (TC1=9e-4 TC2=1e-7)
.MODEL RdrainMOD RES (TC1=6e-3 TC2=8e-5)
.MODEL RSLCMOD RES (TC1=1e-3 TC2=3.5e-5)
.MODEL RsourceMOD RES (TC1=9e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.1e -3 TC2=-1.3e-5)
.MODEL RvtempMOD RES (TC1=-3e-3 TC2=1e-7)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-1.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-2)
.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2003 Fairchild Semiconductor Corporation FDB20AN06A0 / FDP20AN06A0 Rev. B

SABER Electrical Model

rev April 2003
template FDP20AN06A0 n2,n1,n3 =m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=3.8e-12,nl=1.06,rs=4e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=6.8e-10,m=0.53,tt=2.3e-8,xti=3.9)
dp..model dbreakmod = (rs=1.8,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=2.7e-10,isl=10e-30,nl=10,m=0.44)
m..model mmedmod = (type=_n,vto=3.8,kp=2,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.34,kp=35,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.27,kp=0.03,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5,voff=-8)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-1.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-2)
c.ca n12 n8 = 4.4e-10
c.cb n15 n14 = 4.4e-10
c.cin n6 n8 = 9.2e-10

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod

ESG

dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 67.2
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1

GATE

1

LGATE

RLGATE

RGATE

9

EVTEMP
+

18
22

20

spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1

S1A

12

l.lgate n1 n9 = 6.3e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.5e-9

S1B

CA

res.rlgate n1 n9 = 63
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 25

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u ,temp=m_temp
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u ,temp=m_temp

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

19

8

6

-

S2A

13814

13

S2B

13

+

+

6

EGS EDS

8

-

-

15

CIN

CB

-

+

-

5

MSTRO

14

5
8

RSLC1

51

ISCL

50

RDRAIN

16

21

8

MMED

8

DBREAK

11

MWEA K

EBREAK

+

17
18

-

RSOURCE

RBREAK

17 18

IT

RVTHRES

7

RVTE MP

19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB20AN06A0 / FDP20AN06A0

res.rbreak n17 n18 = 1, tc1=9e-4,tc2=1e-7
res.rdrain n50 n16 = 1e-3, tc1=6e-3,tc2=8e-5
res.rgate n9 n20 = 4.7
res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=3.5e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 10e-3, tc1=9e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.1e-3,tc2=-1.3e-5
res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1e-7
sw_vcsp.s1a n6 n12 n13 n8 = model= s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/150))** 2.7))
}
}

©2003 Fairchild Semiconductor Corporation FDB20AN06A0 / FDP20AN06A0 Rev. B

FDB20AN06A0 / FDP20AN06A0

PSPICE Thermal Model

REV 23 April 2003

FDP20AN06A0T

CTHERM1 TH 6 1.8e-3
CTHERM2 6 5 8.0e-3
CTHERM3 5 4 9.0e-3
CTHERM4 4 3 1.1e-2
CTHERM5 3 2 1.2e-2
CTHERM6 2 TL 2.0e-2

RTHERM1 TH 6 3.0e-2
RTHERM2 6 5 1.0e-1
RTHERM3 5 4 1.4e-1
RTHERM4 4 3 2.3e-1
RTHERM5 3 2 4.1e-1
RTHERM6 2 TL 4.2e-1

SABER Thermal Model

SABER thermal model FDP20AN06A0T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1.8e-3
ctherm.ctherm2 6 5 =8.0e-3
ctherm.ctherm3 5 4 =9.0e-3
ctherm.ctherm4 4 3 =1.1e-2
ctherm.ctherm5 3 2 =1.2e-2
ctherm.ctherm6 2 tl =2.0e-2

rtherm.rtherm1 th 6 =3.0e-2
rtherm.rtherm2 6 5 =1.0e-1
rtherm.rtherm3 5 4 =1.4e-1
rtherm.rtherm4 4 3 =2.3e-1
rtherm.rtherm5 3 2 =4.1e-1
rtherm.rtherm6 2 tl =4.2e-1
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

RTHE RM6

tl

©2003 Fairchild Semiconductor Corporation FDB20AN06A0 / FDP20AN06A0 Rev. B

CTHERM6

CASE

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Advance Information

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No Identification Needed

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In Design

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Rev. I3