Datasheet FDP10AN06A0, FDB10AN06A0 Datasheet (Fairchild Semiconductor)

FDB10AN06A0 / FDP10AN06A0

N-Channel PowerTrench® MOSFET
60V, 75A, 10.5mΩ

FDB10AN06A0 / FDP10AN06A0

July 2002

Features

•r

•Q

• Low Miller Charge

• Low Qrr Body Diode

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

Formerly developmental type 82560

= 9.5mΩ (Typ.), V

DS(ON)

(tot) = 28nC (Typ.), V

g

= 10V, ID = 75A

GS

= 10V

GS

Applications

• Motor / Body Load Control

• ABS Systems

• Powertrain Management

• Injection Syste m s

• DC-DC converter s and Off-line UPS

• Distributed P ower Arc hitectures and VRMs

• Primary Switch for 12V and 24V systems

D

DRAIN

(FLANGE)

SOURCE

DRAIN

GA TE

TO-220AB

FDP SERIES

MOSFET Maximum Ratings T

= 25°C unless otherwise not ed

C

GATE

SOURCE

TO-263AB

FDB SERIES

DRAIN

(FLANGE)

G

S

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Sou r c e Voltage 60 V
Gate to Source Voltage ±20 V
Drain Curr e nt
Continuous (T

I

D

Continuous (T

Continuous (T

= 25oC, VGS = 10V)

C

= 100oC, VGS = 10V) 54 A

C

= 25oC, VGS = 10V) with R

amb

= 43oC/W) 12 A

θJA

75 A

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse Avalanche Energy (Note 1) 429 mJ
Power dissipation 135 W

o

Derate above 25

C0.9W/

Operating and Storage Temperature -55 to 175

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

This product has been designed to meet the extreme test conditions an d environment dem anded by the au tomotive industry. For a

All Fairchild Semiconductor products are manufactu red, assembled and tested under ISO9000 and QS9000 quality systems

©2002 Fairchild Semiconductor Corporation

Thermal Resistance Junction t o Case TO-220, TO-263 1.11
Thermal Resistance Junction t o Ambient T O-220, TO-263 (Note 2) 62
Thermal Resistance Junction to Ambient TO-263, 1 in2 copper pad area 43

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be fou nd a t: http://ww w.f airc hilds e m i.co m /pr oduc ts/dis c rete/reliab ility/ind ex.html.

certification.

FDB10AN 06A0 / FDP 10AN06A0 Rev. A

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDB10AN06A0 FDB10AN06A0 TO- 263AB 330mm 24mm 800 unit s
FDP10AN06A0 FDP10AN06A0 TO- 220AB Tube N/A 50 unit s

FDB10AN06A0 / FDP10AN06A0

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Con ditions Min Typ Max Units

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain to Sou r c e Br ea k down Voltag e ID = 250µA, VGS = 0V 60 - - V

V

= 50V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- -250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

I

= 75A, VGS = 10V - 0.0095 0.0105

D

I

= 37A, VGS = 6V - 0.017 0.027

Drain to S ou r c e On Re si st ance

D

= 75A, VGS = 10V,

I

D

T

= 175oC

J

- 0.021 0.023

Dynamic Characteristics

C
C
C
Q
Q
Q
Q
Q

ISS
OSS
RSS

g(TOT)
g(TH)
gs
gs2
gd

Input Capacitance
Output Capacitance - 340 - pF
Reverse Transfer Capacitance - 110 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total Gate Charge at 10V VGS = 0V to 10V
Threshold Gate Charge VGS = 0V to 2V - 3.5 4.6 nC
Gate to Source Gate Charg e - 11.7 - nC
Gate Charge Threshold to Plateau - 8.2 - nC

V

DD

I

= 75A

D

I

= 1.0m A

g

= 30V

Gate to Drain “Miller” Charge - 7.4 - nC

- 1840 - pF

28 37 nC

µA

Ω

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 8 - ns
Rise Time - 128 - ns
Turn-Off D elay Time - 27 - ns
Fall Time - 36 - ns
Turn-Off Time - - 94 ns

(VGS = 10V)

V

= 30V, ID = 75A

DD

V

= 10V, RGS = 10Ω

GS

--206ns

Drain-Source Diode Characteristics

I

= 75A - - 1.2 5 V

V

SD

t

rr

Q

RR

Notes:
1: Starting T
2: Pulse Width = 100s

©2002 Fairchild Semiconductor Corporation FDB10AN06A0 / FDP10AN06A0 Rev. A

Source to Drain Diode Voltage
Reverse Recovery Time ISD = 75A, dISD/dt = 100A/µs- -27ns

Reverse Recovered Charge ISD = 75A, dISD/dt = 100A/µs- -23nC

= 25°C, L = 8.58mH, IAS = 10A.

J

SD

I

= 40A - - 1.0 V

SD

FDB10AN06A0 / FDP10AN06A0

Typical Characteristics T

= 25°C unless otherwise noted

C

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

10

80

60

40

, DRAIN CURRENT (A)

D

I

20

150

0

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

10

TC, CASE TEMPERATURE (oC)

Case Temperature

P

DM

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-1

10

θJC

10

1/t2

x R

0

θJC

t

1

+ T

t

2

C

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

1000

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

VGS = 10V

, PEAK CURRENT (A)

DM

I

100

70

-5

10

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

TC = 25oC
FOR TEMPERATURES

o

ABOVE 25

C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

10

C

150

0

1

10

Figure 4. Peak Current Capability

©2002 Fairchild Semiconductor Corporation FDB10AN06A0 / FDP10AN06A0 Rev. A

Typical Characteristics T

= 25°C unless otherwise noted

C

FDB10AN06A0 / FDP10AN06A0

500

100

OPERATION IN THIS

10

, DRAIN CURRENT (A)

D

1

I

0.1

AREA MAY BE

LIMITED BY r

SINGLE PULSE
TJ = MAX RATED

T

= 25oC

C

110100

DS(ON)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

10µs
100µs

1ms

10ms

DC

Figure 5. Forward Bias Safe Operating Area

500

100

10

, AVALANCHE CURRENT (A)

AS

I

1

0.01

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

150

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

125

V

= 15V

DD

100

75

TJ = 25oC

150

125

100

75

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

STARTING TJ = 150oC

0.1 1 10

tAV, TIME IN AVALANCHE (ms)

Capability

VGS = 10V

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

= 7V

V

GS

VGS = 6V

50

, DRAIN CURRENT (A)

D

I

TJ = 175oC

25

0

45678

TJ = -55oC

VGS, GATE TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

25

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

20

15

10

DRAIN TO SOURCE ON RESISTANCE(mΩ)

5

0 20406080

VGS = 6V

VGS = 10V

ID, DRAIN CURRENT (A)

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

50

, DRAIN CURRENT (A)

D

I

25

0

01234

2.5

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TJ, JUNCTION TEMPERATURE (oC)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TC = 25oC

V

= 5V

GS

VGS = 10V, ID = 75A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

©2002 Fairchild Semiconductor Corporation FDB10AN06A0 / FDP10AN06A0 Rev. A

FDB10AN06A0 / FDP10AN06A0

Typical Characteristics T

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

C

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

3000

C

= CGS + C

1000

ISS

C

≅ C

+ C

OSS

DS

GD

GD

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200
T

, JUNCTION TEMPERATURE (oC)

J

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 30V

8

6

C

= C

RSS

GD

C, CAPACITANCE (pF)

100

V

= 0V, f = 1MHz

GS

50

0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Sour ce

Voltage

4

, GATE TO SOURCE VOLTAGE (V)

2

GS

V

0

60

0 5 10 15 20 25 30

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 75A
I

= 12A

D

Figure 14. Gat e Charge Waveforms for Constant

Gate Currents

©2002 Fairchild Semiconductor Corporation FDB10AN06A0 / FDP10AN06A0 Rev. A

Test Circuits and Waveforms

V

DS

L

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

I

AS

DUT

t

0V

P

I

AS

0.01Ω

0

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Wavef orm s

V

DS

V

DD

V

Q

I

g(REF)

L

V

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

= 2V

Q

gs2

Q

g(TH)

Q

gs

0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

BV

DSS

t

P

t

AV

Q

g(TOT)

DS

gd

V

GS

FDB10AN06A0 / FDP10AN06A0

V

DS

V

DD

V

= 10V

GS

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

10%

90%

PULSE WIDTH

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2002 Fairchild Semiconductor Corporation FDB10AN06A0 / FDP10AN06A0 Rev. A

Thermal Resistance vs. Mounting Pad Area

80

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maxi mum al lowab le de vice p ower di ssip ation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

serve s as the basis for establ ishing the rating of the part.

TJMTA–()

P

----------------- ------------=

DM

R

θJA

DM

(oC/W)

θJA

(EQ. 1)

, in an

60

C/W)

o

(

θJA

R

40

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

FDB10AN06A0 / FDP10AN06A0

In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power d issipati on rating s. Precise d etermin ation of P
comple x and influenced by many factors:

DM

is

1. Mou nting pad area ont o which the device is attached and
whet her the re is copp er on one s ide or both side s of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the
duty cycle and the transient thermal response of the part,
the boa rd and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 bo ar d with 1oz copp er after 1 00 0 se c o n ds
of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides
the necessary inf ormation for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice t hermal model or manu ally utilizin g the normal ized
maximum transient thermal impedance curve.

20

1100.1

(0.645) (6.45) (64.5)

AREA, TOP COPPER AREA in2 (cm2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

Therma l resi stances correspondi ng to other copper are as
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inch es squ are and equ ation 3 is for area in cent imeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

19.84

-------------------------------------+

26.51

=

R

θJA

26.51

=

R

θJA

©2002 Fairchild Semiconductor Corporation FDB10AN06A0 / FDP10AN06A0 Rev. A

0.262 Area+()

Area in Inches Squared

128

----------------------------------+

1.69 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

PSPICE Electrical Model

.SUBCKT FDP 10AN06A0 2 1 3 ; rev July 2002
Ca 12 8 7e-10
Cb 15 14 7e-10
Cin 6 8 1.8e-9

Dbod y 7 5 DbodyMOD
Dbreak 5 11 Db reakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 68.4
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgat e 1 9 7e-9

Ldrain 2 5 1.0e -9
Lsou rce 3 7 3e-9

RLgate 1 9 70
RLdr ai n 2 5 10
RLsource 3 7 30

Mmed 16 6 8 8 M m edMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.6e-3
Rgate 9 20 3.6
RSLC1 5 51 RSL CM OD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 6e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BM OD
S2a 6 15 14 13 S2AM OD
S2b 13 15 14 13 S2BM OD

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

-

13

10

6
8

+

+

RSLC2

6

S2A

14
13

S2B

6
8

-

-

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

-

5

51

5

51

21

MSTRO

14

5
8

RSLC1

+

ESLC

­50

RDRAIN

16

8

MMED

8

DBREAK

11

+

17

EBREAK

18

-

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

7

+

RVTEMP
19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB10AN06A0 / FDP10AN06A0

Vbat 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ ABS(V(5,51)))*(PWR(V (5,51)/(1e-6*250),7))}
.MODEL DbodyMOD D (IS=9E-12 N=1.06 RS=2.7e-3 TRS1=2.4e-3 TRS2=1.1e-6

+ CJO=1.25e-9 M=5.3e-1 TT=4e-9 XTI=3.9)
.MODEL DbreakMOD D (RS= 2. 7e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=4.7e-10 IS=1e-30 N=10 M=0.44)

.MODEL MmedM OD NMOS (VTO= 3.6 KP =5.5 IS=1e-30 N=10 T OX=1 L=1u W=1u R G=3.6)
.MODEL MstroMOD NMOS (VTO=4.4 KP=80 IS=1e- 30 N=10 TOX=1 L=1u W=1u)
.MODEL Mwe akMOD NMOS (VTO=3.06 KP=0. 03 I S=1e-30 N=10 TOX =1 L=1u W=1u RG=36 RS=0.1)

.MODEL Rb reakMOD RES (TC1=9e-4 TC2=5e-7)
.MODEL Rd rai nMOD RES (TC 1=2.5e-2 TC2=7.8e-5)
.MODEL RSLCMOD RES (TC1=1e-3 TC2=3.5e-5)
.MODEL RsourceMOD RES (TC 1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (T C1=-5.9e-3 TC 2=-1.3e-5)
.MODEL RvtempMOD RES (T C1=-2.3e-3 TC 2=1.3e-6)

.MODEL S1AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 8 VOFF =-5 )
.MODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 5 VOFF =-8 )
.MODEL S2AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 2 VOFF =-1 .5 )
.MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1.5 VO FF=- 2)

.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Rec ords, 1991, writ ten by William J. Hepp and C. Frank
Wheatley.

©2002 Fairchild Semiconductor Corporation FDB10AN06A0 / FDP10AN06A0 Rev. A

SABER Electrical Model

REV July 2002
template FDP 10AN06A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=9e-12,nl=1.06,rs=2.7e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.25e-9,m=5.3e-1,tt=4e-9,xti=3.9)
dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e- 6)
dp..model dplcapmod = (cjo=4.7e-10,isl=10e-30,nl=10,m=0.44)
m..model mmedmod = (type=_n,vto=3.6,kp=5.5,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.4,kp=80,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.06,kp=0.03,is=1e-30, tox=1,rs=0.1)
sw_vcsp.. mo del s1amod = (ron=1e- 5,roff=0.1,vo n=-8,voff=-5)
sw_vcsp.. mo del s1bmod = (ron=1e- 5,roff=0.1,vo n=-5,voff=-8)
sw_vcsp.. mo del s2amod = (ron=1e- 5,roff=0.1,vo n=-2,voff=-1.5)
sw_vcsp.. mo del s2bmod = (ron=1e- 5,roff=0.1,vo n=-1.5,voff=-2)
c.ca n12 n8 = 7e- 10
c.cb n15 n14 = 7e- 10
c.cin n6 n8 = 1.8e -9

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplca pm od

spe.ebreak n11 n7 n17 n18 = 68.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1

GATE

1

LGATE

RLGATE

RGATE

9

EVTEMP
+

20

spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1
l.lgate n1 n9 = 7e -9

l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 3e-9

S1A

12

S1B

CA

res.rlgate n1 n9 = 70
res.rldrai n n2 n5 = 10
res.rlsource n3 n7 = 30

m.mmed n16 n6 n8 n8 = m odel=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=ms tr ongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakm od, l=1u, w=1u

ESG

18
22

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

19

8

6

-

S2A

14

13

13

8

S2B

13

+

+

6

EGS EDS

8

-

-

5

RSLC1

51

ISCL

8

MMED

DBREAK

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

50
RDRAIN

16

21

-

MSTRO

CIN

15

CB

14

+

5
8

-

RLDRAIN

+

17
18

LSOURCE

­7

RLSOURCE

RVTEMP
19

­VBAT

+

22

LDRAIN

DBODY

DRAIN

2

SOURCE

3

FDB10AN06A0 / FDP10AN06A0

res.rbreak n17 n18 = 1, tc1=9e-4,tc 2=5e-7
res.rdrain n50 n16 = 1.6e-3, tc1=2. 5e-2,tc2=7. 8e-5
res.rgate n9 n20 = 3.6
res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=3.5e-5
res.rslc2 n5 n50 = 1e3
res.rsour ce n8 n7 = 6e-3, tc1=1e- 3, tc 2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.9e-3,tc2=-1.3e-5
res.rvtemp n18 n19 = 1, tc1=-2.3e-3,tc2=1.3e-6
sw_vcsp.s1 a n6 n12 n13 n8 = model= s1amod
sw_vcsp.s1 b n13 n12 n13 n8 = model =s1bmod
sw_vcsp.s2 a n6 n15 n14 n13 = model =s2amod
sw_vcsp.s2 b n13 n15 n14 n13 = model= s2bmod

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5, n51)/(1e-9+abs(v(n5,n51) )))*((abs(v(n5,n51)*1e 6/250))** 7))

©2002 Fairchild Semiconductor Corporation FDB10AN06A0 / FDP10AN06A0 Rev. A

FDB10AN06A0 / FDP10AN06A0

SPICE Thermal Model

REV 23 July 2002
FDP10AN06A0T

CTHERM1 TH 6 3.2e-3
CTHERM2 6 5 3. 3e-3
CTHERM3 5 4 3. 4e-3
CTHERM4 4 3 3. 5e-3
CTHERM5 3 2 6. 4e-3
CTHERM6 2 TL 1.9e-2

RTHERM1 TH 6 5.5e-4
RTHERM2 6 5 5. 0e-3
RTHERM3 5 4 4. 5e-2
RTHERM4 4 3 1. 5e-1
RTHERM5 3 2 3. 37e-1
RTHERM6 2 TL 3.5e-1

SABER Thermal Model

SABER thermal model FDP10A N06A0T
template thermal_model th tl
thermal_ c th , tl
{
ctherm.c th erm 1 th 6 =3.2e-3
ctherm.ctherm2 6 5 =3.3e-3
ctherm.ctherm3 5 4 =3.4e-3
ctherm.ctherm4 4 3 =3.5e-3
ctherm.ctherm5 3 2 =6.4e-3
ctherm.ctherm6 2 tl =1.9e-2

rtherm.rtherm1 th 6 =5.5e-4
rtherm.rt herm2 6 5 =5.0e-3
rtherm.rt herm3 5 4 =4.5e-2
rtherm.rt herm4 4 3 =1.5e-1
rtherm.rt herm5 3 2 =3.37e-1
rthe r m.rtherm6 2 tl =3.5 e-1
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

RTHERM6

tl

©2002 Fairchild Semiconductor Corporation FDB10AN06A0 / FDP10AN06A0 Rev. A

CTHERM6

CASE

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Rev. I