FDN358P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
SuperSOTTM-3 P-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited for
low voltage applications in notebook computers, portable
phones, PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are needed
in a very small outline surface mount package.
SuperSOTTM-3
SuperSOTTM-6
SuperSOTTM-8
D
358
S
SuperSOT -3
TM
G
-1.5 A, -30 V, R
R
= 0.125 Ω @ VGS = -10 V
DS(ON)
= 0.20 Ω @ VGS = - 4.5 V.
DS(ON)
High power version of industry SOT-23 package: identical
pin out to SOT-23; 30% higher power handling capability.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
SO-8SOT-223
D
G
SOIC-16
S
Absolute Maximum RatingsT
= 25oC unless other wise noted
A
SymbolParameterFDN358PUnits
V
DSS
V
GSS
I
D
Drain-Source Voltage-30V
Gate-Source Voltage ±20V
Drain/Output Current - Continuous-1.5A
- Pulsed-5
P
D
TJ,T
Maximum Power Dissipation (Note 1a)0.5W
(Note 1b)
Operating and Storage Temperature Range-55 to 150°C
Turn - Off Delay Time1727ns
Turn - Off Fall Time101.8ns
g
gs
gd
Total Gate Charge
Gate-Source Charge1nC
Gate-Drain Charge1.1nC
VDS = -5 V, ID = -1.5 A,
VGS = -10 V
816ns
6.59.1nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Note:
1. R
JA
θ
design while R
Typical R
Maximum Continuous Drain-Source Diode Forward Current-0.42A
Drain-Source Diode Forward VoltageVGS = 0 V, IS = -0.42 A (Note 2)-0.74-1.2V
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design.
CA
θ
using the board layouts shown below on FR-4 PCB in a still air environment :