Datasheet FDMS7700S Datasheet (Fairchild)

Page 1
Dual N-Channel PowerTrench® MOSFET
N-Channel: 30 V, 30 A, 7.5 mN-Channel: 30 V, 40 A, 2.4 m
Features
Q1: N-Channel
Max rMax r
Q2: N-Channel
Max rMax r
RoHS Compliant
= 7.5 mΩ at VGS = 10 V, ID = 12 A
DS(on)
= 12 mΩ at VGS = 4.5 V, ID = 10 A
DS(on)
= 2.4 mΩ at VGS = 10 V, ID = 20 A
DS(on)
= 2.9 mΩ at VGS = 4.5 V, ID = 18 A
DS(on)
General Description
This device includes two specialized N-Channel MOSFETs in a dual MLP package.The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET (Q2) have been designed to provide optimal power efficiency.
Applications
ComputingCommunicationsGeneral Purpose Point of Load Notebook VCORE
FDMS7700S Dual N-Channel PowerTrench
December 2009
®
MOSFET
S2
S2
S2
S1/D2
D1
D1
D1
D1
Top Bottom
MOSFET Maximum Ratings T
Symbol Parameter Q1 Q2 Units
V
DS
V
GS
I
D
P
D
TJ, T
STG
Drain to Source Voltage 30 30 V Gate to Source Voltage (Note 3) ±20 ±20 V Drain Current -Continuous (Package limited) TC = 25 °C 30 40
-Continuous (Silicon limited) T
-Continuous T
-Pulsed 40 60 Power Dissipation for Single Operation TA = 25 °C 2.2 T Operating and Storage Junction Temperature Range -55 to +150 °C
Power 56
= 25 °C unless otherwise noted
A
G1
G2
S2
S2 S2 G2
= 25 °C 50 120
C
= 25 °C 12
A
= 25 °C 1.0
A
Q 2
5 6 7 8
1a
1a 1c
Q 1
1b
22
1b
2.5
1d
1.0
Thermal Characteristics
R
θJA θJA
R
θJC
Thermal Resistance, Junction to Ambient 57 Thermal Resistance, Junction to Ambient 125 Thermal Resistance, Junction to Case 3.5 2
1a
1c
50
120
1b
1d
Package Marking and Ordering Information
D1
4
D1
3
D1
2
G1
1
A
W
°C/WR
Device Marking Device Package Reel Size Tape Width Quantity
FDMS7700S FDMS7700S Power 56 13 ” 12 mm 3000 units
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
1
www.fairchildsemi.com
Page 2
FDMS7700S Dual N-Channel PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BV
BVT
I
DSS
I
GSS
DSS
DSS J
Drain to Source Breakdown Voltage Breakdown Voltage Temperature
Coefficient Zero Gate Voltage Drain Current VDS = 24 V, V
Gate to Source Leakage Current VGS = 20 V, VDS= 0 V
On Characteristics
V
GS(th)
VT
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage Gate to Source Threshold Voltage
Temperature Coefficient
Drain to Source On Resistance
Forward Transconductance
ID = 250 µA, VGS = 0 V ID = 1 mA, VGS = 0 V
ID = 250 µA, referenced to 25 °C ID = 1 mA, referenced to 25 °C
= 0 V
GS
VGS = VDS, ID = 250 µA VGS = VDS, ID = 1 mA
ID = 250 µA, referenced to 25 °C ID = 1 mA, referenced to 25 °C
VGS = 10 V, ID = 12 A VGS = 4.5 V, ID = 10 A VGS = 10 V , ID = 12 A , TJ = 125 °C
VGS = 10 V, ID = 20 A VGS = 4.5 V, ID = 18 A VGS = 10 V , ID = 20 A , TJ = 125 °C
VDS = 5 V, ID = 12 A VDS = 5 V, ID = 20 A
Q1Q230
30
Q1 Q2
Q1 Q2
Q1 Q2
Q1Q21
Q1 Q2
Q1
Q2
Q1 Q2
1
15 14
1.8
1.5
6.0
8.5
8.3
1.9
2.2
2.1 63
160
V
mVC
1
500µAµA 100
100nAnA
3 3
-6
-4
mV/°C
7.5 12 12
2.4
2.9
3.4
V
m
S
®
MOSFET
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
g
Q
gs
Q
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge V
Total Gate Charge V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Q1: V
= 15 V, VGS = 0 V, f = 1 MHZ
DS
Q2: V
= 15 V, VGS = 0 V, f = 1 MHZ
DS
Q1: VDD = 15 V, ID = 12 A, R
Q2: VDD = 15 V, ID = 20 A, R
= 0 V to 10 V
GS
Q1 VDD = 15 V,
= 0 V to 4.5 V
GS
ID = 12 A
Q2 VDD = 15 V, ID = 20 A
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
GEN
= 6
Q1 Q2
Q1
GEN
= 6
Q2 Q1
Q2 Q1
Q2 Q1
Q2 Q1
Q2 Q1
Q2
1315
1750
7240
9630
445
2690
600
3580
45
18570280
0.9
0.8
8.62118
2.5
9.21018 20
58
2.3
6.81014 20
10528147
9.34813
4.3 19
2.2 11
34
32 93
67
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
nC
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
www.fairchildsemi.com
Page 3
FDMS7700S Dual N-Channel PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Diode Characteristics
0.8
V
= 0 V, IS = 12 A (Note 2)
V
SD
t
rr
Q
rr
Notes:
1: R
θJA
by the user's board design.
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
a. 57 °C/W when mounted on
2
a 1 in
pad of 2 oz copper
c. 125 °C/W when mounted on a minimum pad of 2 oz copper
GS
V
= 0 V, IS = 20 A (Note 2)Q1Q2
GS
Q1 I
= 12 A, di/dt = 100 A/µs
F
Q2 I
= 20 A, di/dt = 300 A/µs
F
Q1 Q2
Q1 Q2
is guaranteed by design while R
θJC
b. 50 °C/W when mounted on a 1 in
d. 120 °C/W when mounted on a minimum pad of 2 oz copper
2
pad of 2 oz copper
1.2
0.7
1.2
275343
85
10
10018160
θCA
is determined
V
ns
nC
®
MOSFET
2: Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%. 3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
www.fairchildsemi.com
Page 4
FDMS7700S Dual N-Channel PowerTrench
Typical Characteristics (Q1 N-Channel)T
40
30
20
10
, DRAIN CURRENT (A)
D
I
0
VGS = 3.5 V
0.0 0.5 1.0 1.5 2.0
Figure 1.
1.6
ID = 12 A V
= 10 V
GS
1.4
1.2
NORMALIZED
1.0
DRAIN TO SOURCE ON-RESISTANCE
0.8
-75 -50 -25 0 25 50 75 100 125 150
T
Fi gure 3. Normalized On Resistance
vs Junction Temperature
VGS = 10 V
V
= 6
V
GS
VGS = 4.5 V
VGS = 4 V
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
V
,
DRAIN TO SOURCE VOLTAGE (V)
DS
On Region Characteristics Figure 2.
, JUNCTION TEMPERATURE (
J
o
C)
= 25°C unless otherwise noted
J
4
3
VGS = 3.5 V
2
NORMALIZED
1
DRAIN TO SOURCE ON-RESISTANCE
0
0 10203040
I
No rmali ze d On-Res is tance
vs Drain Current and Gate Voltage
40
)
m
(
30
20
DRAIN TO
,
DS(on)
r
10
SOURCE ON-RESISTANCE
0
246810
V
GS
Figure 4.
On-Resistance vs Gate to
Source Voltage
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
VGS = 4 V
V
VGS = 6 V
,
DRAIN CURRENT (A)
D
TJ = 125 oC
TJ = 25 oC
,
GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
ID = 12 A
GS
= 4.5 V
V
GS
= 10 V
®
MOSFET
40
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
30
V
= 5 V
DS
20
10
, DRAIN CURRENT (A)
D
I
0
1.5 2.0 2.5 3.0 3.5 4.0
TJ = 150 oC
TJ = 25 oC
VGS, GATE TO SOURCE V OLTAGE (V)
Figure 5. Transfer Characteristics
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
40
V
= 0 V
GS
10
1
0.1
0.01
, REVERSE DRAIN CURRENT (A)
S
TJ = -55 oC
I
0.001
0.0 0.2 0.4 0.6 0.8 1.0 1.2
TJ = 150 oC
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6.
Source to Drain Diode
TJ = 25 oC
TJ = -55 oC
Forward Voltage vs Source Current
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Page 5
FDMS7700S Dual N-Channel PowerTrench
Typical Characteristics (Q1 N-Channel)T
10
ID = 12 A
8
V
= 10 V
DD
6
4
V
DD
2
, GATE TO SOURCE VOLTAGE (V)
GS
V
0
0 5 10 15 20
Figure 7.
Qg, GATE CHARGE (nC)
Gate Charge Characteristics Figure 8.
60
V
= 10 V
GS
40
V
= 4.5 V
GS
20
Limited by Package
DRAIN CURRENT (A)
,
D
I
0
25 50 75 100 125 150
T
,
CASE TEMPERATURE
C
Figure 9.
Maximum Continuous Drain
Current vs Case Temperature
= 20 V
VDD = 15 V
R
= 3.5 oC/W
θ
JC
o
(
C
)
= 25°C unless otherwise noted
J
2000 1000
100
CAPACITANCE (pF)
f = 1 MHz
= 0 V
V
GS
10
0.1 1 10 30
VDS, DRAIN TO SOURCE VOLTAGE (V)
Cap aci tan ce v s Dr ain
to Source Voltage
100
10
1
THIS AR EA IS
LIMITED BY r
SINGLE PULSE
, DRAIN CURRENT (A)
0.1
T
D
J
I
R
θ
T
A
0.01
0.01 0.1 1 10 100
DS(on
= MAX RATED
= 125 oC/W
JA
= 25 oC
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 10.
Operating Area
C
iss
C
oss
C
rss
100us
1 ms
10 ms
)
100 ms
1s
10s
DC
200
Forwa rd Bias Safe
®
MOSFET
1000
100
10
, PEAK TRANSIENT POWER (W)
1
(PK)
P
0.5
-4
10
-3
10
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
-2
10
-1
10
t, PULSE WIDTH (s)
110
Figure 11. Single Pulse Maximum Power Dissipation
SINGLE PULSE
= 125 oC/W
R
θ
JA
T
= 25 oC
A
100 1000
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Page 6
FDMS7700S Dual N-Channel PowerTrench
Typical Characteristics (Q1 N-Channel)T
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
JA
θ
Z
0.1
IMPEDANCE,
0.01
NORMALIZED THERMAL
0.001
0.1
0.05
0.02
0.01
SINGLE PULSE R
= 125 oC/W
θ
JA
(
Note 1c
)
-4
10
-3
10
-2
10
10
t, RECTANGULAR PULSE DURATION (sec)
Figure 12. Junction-to-Ambient Transient Thermal Response Cu rve
= 25°C unless otherwise noted
J
NOTES: DUTY FACTOR: D = t
PEAK TJ = PDM x Z
-1
110
P
DM
t
1
t
2
1/t2
x R
+ T
θJA
θJA
A
100 1000
®
MOSFET
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
www.fairchildsemi.com
Page 7
Typical Characteristics (Q2 SyncFET)
FDMS7700S Dual N-Channel PowerTrench
60
PULSE DURATION = 80 µs
50
40
30
VGS = 10 V
VGS = 4.5 V
VGS = 3.5 V
VGS = 3 V
DUTY CYCLE = 0.5% MAX
20
, DRAIN CURRENT (A)
D
10
I
VGS = 2.5 V
0
0 0.2 0.4 0.6 0.8 1.0
V
,
DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 13. On-Region Characteristics
1.6
ID = 20 A V
= 10 V
GS
1.4
1.2
1.0
NORMALIZED
0.8
DRAIN TO SOURCE ON-RESISTANCE
0.6
-75 -50 -25 0 25 50 75 100 125 150
T
, JUNCTION TEMPERATURE (
J
Figure 15. Normalized On-Resistance
vs Junction Temperature
6
5
VGS = 2.5 V
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
4
3
2
NORMALIZED
VGS = 3 V
1
V
DRAIN TO SOURCE ON-RESISTANCE
VGS = 3.5 V
0
0 102030405060
I
,
DRAIN CURRENT (A)
D
GS
= 4.5 V
V
= 10 V
GS
Figure 14. Normalized on-Resistance vs Drain
Current and Gate Voltage
10
)
m
8
(
PULSE DURA TION = 80 µs DUTY CYCLE = 0.5% MAX
ID = 20 A
6
DRAIN TO
,
4
DS(on)
r
TJ = 125 oC
2
SOURCE ON-RESISTANCE
0
o
C)
246810
TJ = 25 oC
V
,
GATE TO SOURCE VOLTAGE (V)
GS
®
MOSFET
Figure 16. On-Resistance vs Gate to
Source Voltage
60
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
50
V
= 5 V
DS
40
TJ = 125 oC
30
20
, DRAIN CURRENT (A)
D
I
10
0
1.0 1.5 2.0 2.5 3.0
VGS, GATE TO SOURCE V OLTAGE (V)
Figure 17. Transfer Characteristics
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
60
V
= 0 V
GS
10
TJ = 125 oC
1
TJ = 25 oC
TJ = -55 oC
0.1
0.01
, REVERSE DRAIN CURRENT (A)
S
I
0.001 0 0.2 0.4 0.6 0.8 1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
TJ = 25 oC
TJ = -55 oC
Figure 18. Source to Drain Diode
Forward Voltage vs Source Current
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Page 8
Typical Characteristics (Q2 SyncFET)
FDMS7700S Dual N-Channel PowerTrench
10
ID = 20 A
8
V
= 10 V
DD
6
4
VDD = 20 V
VDD = 15 V
2
, GATE TO SOURCE VOLTAGE ( V)
GS
V
0
04080120
Qg, GATE CHARGE (nC)
Figure 19. Gate Charge Charac ter is tics
150
R
= 2 oC/W
θ
V
= 10 V
GS
100
V
= 4.5 V
GS
50
DRAIN CURRENT (A)
,
D
I
Limited by Package
0
25 50 75 100 125 150
T
,
CASE TEMPERATURE
C
JC
o
(
C
)
30000
C
10000
1000
CAPACITANCE (pF)
100
f = 1 MHz
= 0 V
V
GS
0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
iss
C
oss
C
rss
Figure 20. Capacitance vs Drain
to Source Voltage
100
10
THIS AREA IS
1
LIMITED BY r
SINGLE PULSE
= MAX RATED
T
, DRAIN CURRENT (A)
D
I
J
0.1
R
θJA
= 25
T
A
0.01
0.01 0.1 1 10 100
DS(on)
o
= 120
C/W
o
C
VDS, DRAIN to SOURCE VOLTAGE (V)
30
®
MOSFET
1 ms
10 ms 100 ms
1 s
10 s
DC
Figure 21. M aximum Contin uous Drai n
Current vs
Case Temperature
1000
100
10
, PEAK TRANSIENT POWER (W)
1
(PK)
P
0.5
-3
10
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
10
Figure 22. Forward Bias Safe Operating Area
SINGLE PULSE R
= 120 oC/W
θ
JA
T
= 25 oC
A
-2
Figure 23. Single Pulse Maximum Power Dissipation
-1
10
t, PULSE WIDTH (s)
110
100 1000
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Page 9
Typical Characteristics (Q2 SyncFET)
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
JA
θ
Z
0.1
IMPEDANCE,
0.01
NORMALIZED THERMAL
0.001 10
Figure 24. Junction-to-Ambient Transient Thermal Response Curve
0.1
0.05
0.02
0.01
SINGLE PULSE R
= 120 oC/W
θ
JA
(Note 1d)
-3
-2
10
-1
10
t, RECTANGULAR PULSE DURATION (s)
110
NOTES: DUTY FACTOR: D = t
PEAK TJ = PDM x Z
P
DM
1/t2
θJA
100 1000
x R
θJA
t
1
+ T
FDMS7700S Dual N-Channel PowerTrench
t
2
A
®
MOSFET
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
www.fairchildsemi.com
Page 10
Typical Characteristics (continued)
SyncFET Schottky body diode Characteristics
FDMS7700S Dual N-Channel PowerTrench
Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 25 shows the reverse recovery characteristic of the FDMS7700S.
12
9
6
3
CURRENT (A)
0
-3
-6 100 150 200 250 300
TIME (ns)
didt = 300 A/µ s
Figure 25. FDMS7700S SyncFET body
diode reverse recovery characteristic
Schottky barrier diodes exhibit significant leakage at high tem­perature and high reverse voltage. This will increase the power in the device.
-1
10
-2
10
-3
10
-4
10
, REVERSE LEAKAGE CURRENT (A)
-5
10
DSS
I
0 5 10 15 20 25 30
VDS, REVERSE VOLTAGE (V)
TJ = 125 oC
TJ = 100 oC
TJ = 25 oC
Figure 26. SyncFET body diode reverse leakage versus drain-source voltage
®
MOSFET
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
www.fairchildsemi.com
Page 11
Dimensional Outline and Pad Layout
FDMS7700S Dual N-Channel PowerTrench
®
MOSFET
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
www.fairchildsemi.com
Page 12
TRADEMARKS
tm
®
tm
tm
The following includes registered and unregistered trademarks and service marks, o wned by Fairchild Semiconducto r and/or its g lobal subsidiaries, and i s not intended to be an exhaustive list of all such trademarks.
AccuPower™ Auto-SPM™ Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK EfficentMax™ EZSWITCH™*
™*
Fairchild Fairchild Semiconductor FACT Quiet Series™ FACT FAST FastvCore™ FETBench™ FlashWriter
®
®
®
®
®
*
®
FPS™ F-PFS™ FRFET Global Power Resource Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ MotionMax™ Motion-SPM™ OPTOLOGIC OPTOPLANAR
®
PDP SPM™ Power-SPM™
PowerTrench
®
SM
PowerXS™ Programmable Active Droop™ QFET QS™ Quiet Series™ RapidConfigure™
Saving our world, 1mW /W /kW at a time™ SmartMax™ SMART START™ SPM STEALTH™ SuperFET™ SuperSOT™-3
®
®
SuperSOT™-6 SuperSOT™-8 SupreMOS™ SyncFET™ Sync-Lock™
®
®
®
The Power Franchise
TinyBoost™ TinyBuck™ TinyCalc™ TinyLogic TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ TriFault Detect™
®
®
®
TRUECURRENT™*
®
UHC Ultra FRFET™ UniFET™ VCX™ VisualMax™
®*
XS™
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
FDMS7700S Dual N-Channel PowerTrench
®
MOSFET
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
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2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
expected to result in a significant injury of the user.
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PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative / In Design
Preliminary First Production
No Identification Needed Full Production
Obsolete Not In Production
©2009 Fairchild Semiconductor Corporation FDMS7700S Rev.C
Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
Datasheet contains preliminary data; supplement ary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The dat asheet is for reference information only.
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Rev. I41
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