Datasheet FDMS7608S Datasheet (Fairchild)

FDMS7608S

Power 56

S2

G2

D1

G1

D1

S1/D2

S2

G2

D1

G1

Top

Bottom

Pin1

Q2

Q1

Dual N-Channel PowerTrench® MOSFET

Q1: 30 V, 22 A, 10.0 mΩ Q2: 30 V, 30 A, 6.3 mΩ

FDMS7608S Dual N-Channel PowerTrench

June 2011

Features

Q1: N-Channel

 Max r  Max r

Q2: N-Channel

 Max r  Max r

 RoHS Compliant

= 10.0 mΩ at VGS = 10 V, ID = 12 A

DS(on)

= 13.6 mΩ at VGS = 4.5 V, ID = 10 A

DS(on)

= 6.3 mΩ at VGS = 10 V, ID = 15 A

DS(on)

= 7.2 mΩ at VGS = 4.5 V, ID = 13 A

DS(on)

General Description

This device includes two specialized N-Channel MOSFETs in a dual MLP package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET (Q2) have been designed to provide optimal power efficiency.

Applications

 Computing  Communications  General Purpose Point of Load  Notebook VCORE

®

MOSFET

MOSFET Maximum Ratings T

Symbol Parameter Q1 Q2 Units

V

DS

V

GS

I

D

E

AS

P

D

TJ, T

STG

Drain to Source Voltage 30 30 V Gate to Source Voltage (Note 3) ±20 ±20 V Drain Current -Continuous (Package limited) TC = 25 °C 22 30

-Continuous (Silicon limited) T

-Continuous T

-Pulsed 50 60 Single Pulse Avalanche Energy (Note 4) 29 33 mJ Power Dissipation for Single Operation TA = 25°C 2.2 Power Dissipation for Single Operation T Operating and Storage Junction Temperature Range -55 to +150 °C

= 25°C unless otherwise noted

A

= 25 °C 46 60

C

= 25 °C 12

A

= 25°C 1.0

A

1a

1a 1c

15

2.5

1.0

1b

1b 1d

A

W

Thermal Characteristics

R

θJA θJA

R

θJC

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDMS7608S FDMS7608S Power 56 13 ” 12

Thermal Resistance, Junction to Ambient 57 Thermal Resistance, Junction to Ambient 125 Thermal Resistance, Junction to Case 4.0 3.2

1a

1c

mm 3000 units

50

120

1b

1d

°C/WR

FDMS7608S Dual N-Channel PowerTrench

Electrical Characteristics T

= 25°C unless otherwise noted

J

Symbol Parameter Test Conditions Type Min Typ Max Units

Off Characteristics

BV

ΔBV ΔT

I

DSS

I

GSS

DSS

DSS J

Drain to Source Breakdown Voltage Breakdown Voltage Temperature

Coefficient Zero Gate Voltage Drain Current V

Gate to Source Leakage Current V

= 250 μA, VGS = 0 V

D

I

= 1 mA, VGS = 0 V

D

I

= 250 μA, referenced to 25°C

D

I

= 10 mA, referenced to 25°C

D

= 24 V, V

DS

= 20 V, V

GS

DS

= 0 V = 0 V

Q1Q230

30

Q1 Q2

V

13 19

mV/°C

1

500 100

100nAnA

I

On Characteristics

V

GS(th)

ΔV ΔT

r

DS(on)

g

FS

GS(th)

J

Gate to Source Threshold Voltage Gate to Source Threshold Voltage

Temperature Coefficient

Static Drain to Source On Resistance

Forward Transconductance

= VDS, I

GS

V

= VDS, I

GS

I

= 250 μA, referenced to 25°C

D

I

= 10 mA, referenced to 25°C

D

= 10 V, ID = 12 A

V

GS

V

= 4.5 V, ID = 10 A

GS

V

= 10 V, ID = 12 A, T

GS

V

= 10 V, ID = 15 A

GS

V

= 4.5 V, ID = 13 A

GS

V

= 10 V, ID = 15 A, T

GS

V

= 5 V, ID = 12 A

DD

V

= 5 V, ID = 15 A

DD

= 250 μA

D

= 1 mA

D

= 125°C

J

= 125°C

J

Q1Q21.2

1.2

Q1 Q2

Q1

Q2

Q1 Q2

1.9

1.7

-6

-4

7.4

10.0

10.3

4.8

6.0

6.6 54

76

3.0

3.0 mV/°C

10.0

13.6

13.9

6.3

7.2

8.6

μA

V

mΩ

S

®

MOSFET

Dynamic Characteristics

C

iss

C

oss

C

rss

R

g

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Gate Resistance

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q

g(TOT)

gs

gd

Turn-On Delay Time

Rise Time

Turn-Off Delay Time

Fall Time

Total Gate Charge V

Gate to Source Charge

Gate to Drain “Miller” Charge

1135

Q1:

= 15 V, VGS = 0 V, f = 1 MHZ

V

DS

Q2:

= 15 V, VGS = 0 V, f = 1 MHZ

V

DS

Q1 Q2

Q1Q20.2

0.2

1380

390 478

42 60

1.6

0.5

1510 1835

520 635

65 90

3.2

2.0

pF

Ω

7

19 20

18 21

12

14 14

10 10

35 36

10 10

24 30

14 16

ns

nC

7 3

3

3 2

9

nC

Q1 V

= 15 V, ID = 12 A, R

DD

Q2 V

= 15 V, ID = 15 A, R

DD

= 0V to 10 V

GS

= 0V to 5 V

GS

Q1 V

DD

I

= 12 A

D

Q2 V

DD

I

= 15 A

D

= 6 Ω

GEN

= 6 Ω

GEN

= 15 V,

Q1 Q2

3.6

3.5

2.5

3.0

Electrical Characteristics T

= 25°C unless otherwise noted

J

Symbol Parameter Test Conditions Type Min Typ Max Units

Drain-Source Diode Characteristics

25 21

19

9

1.1

1.2

0.8

1.2

40 34

18 33

is determined by

θCA

V

= 0 V, IS = 2 A (Note 2)

GS

V

= 0 V, IS = 12 A (Note 2)

V

SD

t

rr

Q

rr

Notes:

1.R

is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R

θJA

the user's board design.

Source-Drain Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

GS

V

= 0 V, IS = 2 A (Note 2)

GS

V

= 0 V, IS = 15 A (Note 2)

GS

Q1

= 12 A, di/dt = 100 A/μs

I

F

Q2 I

= 15 A, di/dt = 300 A/μs

F

Q1 Q1 Q2 Q2

Q1 Q2

is guaranteed by design while R

θJC

0.75

0.84

0.63

0.80

FDMS7608S Dual N-Channel PowerTrench

V

ns

nC

a. 57 °C/W when mounted on

2

pad of 2 oz copper

a 1 in

c. 125 °C/W when mounted on a minimum pad of 2 oz copper

2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.

3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.

4. Q1: EAS of 29 mJ is based on starting TJ = 25 oC; N-ch: L = 0.3 mH, IAS = 14 A, VDD = 27 V, VGS = 10 V. 100% tested at L = 3 mH, IAS = 3.75 A. Q2: EAS of 33 mJ is based on starting TJ = 25 oC; N-ch: L = 0.3 mH, IAS = 15 A, VDD = 27 V, VGS = 10 V. 100% tested at L = 3 mH, IAS = 3.9 A.

b. 50 °C/W when mounted on

2

a 1 in

pad of 2 oz copper

d. 120 °C/W when mounted on a minimum pad of 2 oz copper

®

MOSFET

FDMS7608S Dual N-Channel PowerTrench

0.00.51.01.52.0

0

10

20

30

40

50

V

GS

= 3 V

V

GS

= 6 V

V

GS

= 4 V

V

GS

= 10 V

V

GS

= 4.5 V

V

GS

= 3.5 V

PULSE DURATION = 80 μ s DUTY CYCLE = 0.5% MAX

I

D

, DRAIN CURRENT (A)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

0 1020304050

0

1

2

3

4

5

6

VGS = 3 V

VGS = 6 V

VGS = 3.5 V

PULSE DURA TION = 80 μs DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTA NCE

I

D

, DRAIN CURRENT (A)

V

GS

= 4 V

VGS = 4.5 V

V

GS

= 10 V

-75 -50 -25 0 25 50 75 100 125 150

0.6

0.8

1.0

1.2

1.4

1.6

ID = 12 A V

GS

= 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESISTANC E

T

J

, JUNCTION TEMPERATURE (

o

C)

2345678910

0

10

20

30

40

TJ = 125 oC

ID = 12 A

TJ = 25 oC

V

GS

, GATE TO SOURCE VOLTA G E (V)

r

DS(on)

,

DRAIN TO

SOURCE ON-RESISTANCE

(mΩ)

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

1.5 2.0 2.5 3.0 3.5 4.0 4.5

0

10

20

30

40

50

TJ = 150 oC

V

DS

= 5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

I

D

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

50

TJ = -55 oC

TJ = 25 oC

TJ = 150 oC

V

GS

= 0 V

I

S

, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics (Q1 N-Channel) T

Figure 1.

On Region Characteristics Figure 2.

= 25°C unless otherwise noted

J

Nor mal ize d On -Re sis tan ce

vs Drain Current and Gate Voltage

®

MOSFET

Figure 3 . Norma li zed On Re si stanc e

vs Junction Temperature

Figure 5. Transfer Characteristics

Figure 4.

On-Resistance vs Gate to

Source Voltage

Figure 6.

Source to Drain Di ode

Forward Voltage vs Source Current

FDMS7608S Dual N-Channel PowerTrench

0 3 6 9 12 15 18

0

2

4

6

8

10

ID = 12 A

V

DD

= 20 V

V

DD

= 10 V

V

GS

, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 30

10

100

1000

2000

f = 1 MHz V

GS

= 0 V

CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

rss

C

oss

C

iss

0.001 0.01 0.1 1 10 50

1

10

30

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I

AS

, AVALANCHE CURRENT (A)

25 50 75 100 125 150

0

10

20

30

40

50

R

θJC

= 4.0 oC/W

V

GS

= 4.5 V

Limited by Package

V

GS

= 10 V

I

D

, DRAIN CURRENT (A)

T

C

, CASE TEMPERATURE (

o

C)

0.01 0.1 1 10 1 00200

0.01

0.1

1

10

100

100 μs

DC

100 ms

10 ms

1 ms

1s

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS

LIMITED BY r

DS(on)

SINGLE PULSE T

J

= MAX RATED

R

θJA

= 125

o

C/W

T

A

= 25

o

C

10s

10-410-310-210-1110

100 1000

0.5

1

10

100

1000

SINGLE PULSE R

θJA

= 125 oC/W

P(

PK

), PEAK TRANSIENT POWER (W)

t, PULSE WIDTH (sec)

Typical Characteristics (Q1 N-Channel) T

Figure 7.

Gate Charge Characteristics Figure 8.

= 25°C unless otherwise noted

J

Cap aci t anc e vs Drai n

to Source Voltage

®

MOSFET

Figure 9.

Uncl ampe d Ind ucti ve

Switching Capability

Figure 11. Forward Bias Safe

Op

erating Area

Figure 10.

Ma xi mu m Continuous Drain

Current vs Case Temperature

Figure 12.

Si ngle Pul se Maximu m

Power Dissipation

FDMS7608S Dual N-Channel PowerTrench

10

-4

10

-3

10

-2

10

-1

110

100 1000

0.001

0.01

0.1

1

2

SINGLE PULSE R

θJA

= 125 oC/W

(Note 1b)

DUTY CYCLE-DESCENDING ORDER

NORMALIZED THERMAL

IMPEDANCE,

Z

θJA

t, RECTANGULAR PU L SE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

P

DM

t

1

t

2

NOTES: DUTY FACTOR: D = t1/t

2

PEAK TJ = PDM x Z

θJA

x R

θJA

+ T

A

Typical Characteristics (Q1 N-Channel) T

Figure 13.

Junction-to-Ambient Transient Thermal Response Curve

= 25°C unless otherwise noted

J

®

MOSFET

FDMS7608S Dual N-Channel PowerTrench

0.00.51.01.52.0

0

10

20

30

40

50

60

V

GS

= 3 V

V

GS

= 4 V

V

GS

= 6 V

V

GS

= 10 V

V

GS

= 4.5 V

V

GS

= 3.5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

I

D

, DRAIN CURRENT (A)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

0 102030405060

0

1

2

3

4

VGS = 3 V

VGS = 6 V

VGS = 3.5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTA NC E

I

D

, DRAIN CURRENT (A)

V

GS

= 4 V

VGS = 4.5 V

V

GS

= 10 V

-75 -50 -25 0 25 50 75 100 125 150

0.6

0.8

1.0

1.2

1.4

1.6

ID = 15 A V

GS

= 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESISTANCE

T

J

, JUNCTION TEMPERATURE (

o

C)

246810

0

4

8

12

16

20

24

28

TJ = 125 oC

ID = 15 A

TJ = 25 oC

V

GS

, GATE TO SOURCE VOLTA G E (V)

r

DS(on)

,

DRAIN TO

SOURCE ON-RESISTANCE

(mΩ)

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

1.5 2.0 2.5 3.0 3.5 4.0

0

10

20

30

40

50

60

TJ = 125 oC

V

DS

= 5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

I

D

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

60

TJ = -55 oC

TJ = 25 oC

TJ = 125 oC

V

GS

= 0 V

I

S

, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics (Q2 N-Channel) T

Figure 14.

On-Region Characteristics Figure 15. Normalized on-Resistance vs Drain

= 25 °C unless otherwise noted

J

Current and Gate Voltage

®

MOSFET

Figure 16. Normalized On-Resistance

vs Junction Temperature

Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode

Figure 17. On-Resistance vs Gate to

Source Voltage

Forward Voltag e vs Source Current

FDMS7608S Dual N-Channel PowerTrench

0 5 10 15 20

0

2

4

6

8

10

ID = 15 A

V

DD

= 20 V

V

DD

= 10 V

V

GS

, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 30

10

100

1000

3000

f = 1 MHz V

GS

= 0 V

CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

rss

C

oss

C

iss

0.001 0.01 0.1 1 10 100

1

10

30

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALA NCHE (ms)

I

AS

, AVALANCHE CURRENT (A)

25 50 75 100 125 150

0

14

28

42

56

70

R

θJC

= 3.2 oC/W

V

GS

= 4.5 V

Limited by Package

V

GS

= 10 V

I

D

, DRAIN CURRENT (A)

T

C

, CASE TEMPERATURE (

o

C)

0.01 0.1 1 10 1 00200

0.01

0.1

1

10

100

100 μs

DC

100 ms

10 ms

1 ms

1s

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS A REA IS

LIMITED BY r

DS(on)

SINGLE PULSE T

J

= MAX RATED

R

θJA

= 120

o

C/W

T

A

= 25

o

C

10s

10-410-310-210-110010

1

100 1000

0.5

1

10

100

1000

SINGLE PULSE R

θJA

= 120 oC/W

P(

PK

), PEAK TRANSIENT POWER (W)

t, PULSE WIDTH (sec)

Typical Characteristics (Q2 N-Channel) T

Figure 20. Gate Charge Characteristics

= 25°C unless otherwise noted

J

Figure 21. Capacitance vs Drain

to Source Voltage

®

MOSFET

Figure 22. Unclamped Inductive

Switching Capability

Fi gure 24 . Forwar d Bias S afe

Operating Area

Figur e 23 . Maxi mum Conti nuous Dra in

Current vs Case Temperature

Figure 25. Single Pulse Maximum Power

Dissipation

10

-4

10

-3

10

-2

10

-1

10

0

10

1

100 1000

0.001

0.01

0.1

1

2

SINGLE PULSE R

θJA

= 120 oC/W

(Note 1b)

DUTY CYCLE-DESCENDING ORDER

NORMALIZED THERMAL

IMPEDANCE,

Z

θJA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

P

DM

t

1

t

2

NOTES: DUTY FACTOR: D = t

1/t2

PEAK TJ = PDM x Z

θJA

x R

θJA

+ T

A

FDMS7608S Dual N-Channel PowerTrench

Typical Characteristics (Q2 N-Channel) T

Figure 26. Junction-to-Ambient Transient Thermal Response Curve

= 25 °C unless otherwise noted

J

®

MOSFET

23.0623.08 23.1023.1223.14 23.1623.1823.20 23.2223.24

-4

0

4

8

12

16

CURRENT (A)

TIME (ns)

di/dt = 300 A/μs

0 5 10 15 20 25 30

10

-6

10

-5

10

-4

10

-3

10

-2

TJ = 125 oC

TJ = 100 oC

TJ = 25 oC

I

DSS

, REVERSE LEAKAGE CURRENT (A)

VDS, REVERSE VOLTAGE (V)

Typical Characteristics (continued)

SyncFET Schottky body diode Characteristics

FDMS7608S Dual N-Channel PowerTrench

Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDMS7608S.

Figure 27. FDMS7608S SyncFET body

diode reverse recovery characteristic

Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device.

Figure 28. SyncFET body diode reverse leakage versus drain-source voltage

®

MOSFET

Dimensional Outline and Pad Layout

6.30

0.63

1.27

(OPTION 2 - ISOLATED LEADS)

(OPTION 1 - FUSED LEADS 5,6,7)

0.20

0 .34 0 4X

RECOMM ENDED LA ND PATTERN

2.67

4.00

0.65 TYP

12 3 4

5

6 7 8

0.92

0.66

0.54

0.40

0.65 (5X)

0.63

3.81

1.27

6.0

5.0

PIN#1 QUADRANT

0.80 MAX

0.25 0

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIME NSIONS AND TOLERANCES PER

E. DRAWIN G FIL E NAME : MKT -ML P 08Prev1

A. DOES NOT FULLY CONFORM TO

JEDEC REGISTRATION, MO-229.

ASME Y14. 5M, 1994

TOP VIEW

BOTTOM VIEW

RECOMM ENDED LA ND PATTERN

0.08 C

B

A

0.10 C

2X

0.10 C

2X

SIDE VIEW

(0.20)

SEATING PLANE

0.10 C A B

0.10 C

12 3 4

5 6 7 8

6.30

2.67

4.00

0.65 TYP

PIN #1 IDENT

0.05 C

1

2

3

4

5

6 7 8

0.05

0.00

2.72

2.62

3.85

3.75

0.48

0.38

(5X)

0.97

0.87

0.56

0.46

(5X)

0.92

0.66

0.55

0.54

0.40

0.45

D. L AND PATTERN RECOMMENDATION IS

BASED ON FSC DESIGN ONLY

FDMS7608S Dual N-Channel PowerTrench

®

MOSFET

TRADEMARKS

tm

®

tm

The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor a nd/or its global subsid iaries, and is not intended to be an exhaustive list of all such trademarks.

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*

FDMS7608S Dual N-Channel PowerTrench

®

MOSFET

*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used here in:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

ANTI-COUNTERFEITING POLICY

Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support Counterfeiting of semiconductor parts is a growing problem in the industr y. All manufactures of semicondu ctor products are experiencing count erfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience ma ny problems such as lo ss of bran d reput ation, sub standard perf ormance, failed application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the

proliferation of counterfeit parts. Fairchild strongly en courages customers t o purchase Fairchild parts either dir ectly from Fairchild or from Auth orized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct o r from authorized distr ibutors.

PRODUCT STATUS DEFINITIONS Definition of Terms

.

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Datasheet Identification Product Status Definition

Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.

Rev. I54

Datasheet FDMS7608S Datasheet (Fairchild)

Specifications and Main Features

Frequently Asked Questions

User Manual