Datasheet FDMS3615S Datasheet (Fairchild)

FDMS3615S

Q

G1

D1

G2

S2

D1

PHASE (S1/D2)

S2

S2 S2 G2

D1

D1 D1

G1

PHASE

Power 56

Top Bottom

Pin 1

PowerTrench® Power Stage

25V Asymmetric Dual N-Channel MOSFET

FDMS3615S PowerTrench

August 2011

Features

Q1: N-Channel

 Max r  Max r

Q2: N-Channel

 Max r  Max r  Low inductance packaging shortens rise/fall times, resulting in

lower switching losses

 MOSFET integration enables optimum layout for lower circuit

inductance and reduced switch node ringing

 RoHS Compliant

= 5.8 mΩ at VGS = 10 V, ID = 16 A

DS(on)

= 8.3 mΩ at VGS = 4.5 V, ID = 13 A

DS(on)

= 3.4 mΩ at VGS = 10 V, ID = 18 A

DS(on)

= 4.6 mΩ at VGS = 4.5 V, ID = 15 A

DS(on)

General Description

This device includes two specialized N-Channel MOSFETs in a dual PQFN package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET (Q2) have been designed to provide optimal power efficiency.

Applications

 Computing  Communications  General Purpose Point of Load  Notebook VCORE  Server

2

5 6 7 8

4 3 2 1

1

®

Power Stage

MOSFET Maximum Ratings T

Symbol Parameter Q1 Q2 Units

V

DS

V

GS

I

D

E

AS

P

D

TJ, T

STG

Drain to Source Voltage 25 25 V Gate to Source Voltage (Note 3) ±20 ±20 V Drain Current -Continuous (Package limited) TC = 25 °C 23 18

-Continuous (Silicon limited) T

-Continuous T

-Pulsed 45 36 Single Pulse Avalanche Energy 38 Power Dissipation for Single Operation TA = 25°C 2.3 Power Dissipation for Single Operation T Operating and Storage Junction Temperature Range -55 to +150 °C

= 25°C unless otherwise noted

A

= 25 °C 89 88

C

= 25 °C 16

A

= 25°C 1.0

A

1a

4 1a 1c

18

98

2.3

1.0

1b

5 1b 1d

A

mJ

W

Thermal Characteristics

R

θJA

R

θJA

Thermal Resistance, Junction to Ambient 55 Thermal Resistance, Junction to Ambient 125

1a

1c

55

125

1b

°C/W

1d

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

Y8OA

K10OC

FDMS3615S Power 56 13 ” 12

mm 3000 units

FDMS3615S PowerTrench

Electrical Characteristics T

= 25°C unless otherwise noted

J

Symbol Parameter Test Conditions Type Min Typ Max Units

Off Characteristics

BV

ΔBV ΔT

I

DSS

I

GSS

DSS

DSS J

Drain to Source Breakdown Voltage Breakdown Voltage Temperature

Coefficient Zero Gate Voltage Drain Current V

Gate to Source Leakage Current V

= 250 μA, VGS = 0 V

D

I

= 1 mA, VGS = 0 V

D

I

= 250 μA, referenced to 25°C

D

I

= 10 mA, referenced to 25°C

D

= 20 V, V

DS

= 20 V, V

GS

DS

= 0 V = 0 V

Q1Q225

25

Q1 Q2

V

18 16

mV/°C

1

500 100

100nAnA

I

On Characteristics

V

GS(th)

ΔV ΔT

r

DS(on)

g

FS

GS(th)

J

Gate to Source Threshold Voltage Gate to Source Threshold Voltage

Temperature Coefficient

Static Drain to Source On Resistance

Forward Transconductance

= VDS, I

GS

V

= VDS, I

GS

I

= 250 μA, referenced to 25°C

D

I

= 10 mA, referenced to 25°C

D

= 10 V, ID = 16 A

V

GS

V

= 4.5 V, ID = 13 A

GS

V

= 10 V, ID = 16 A, T

GS

V

= 10 V, ID = 18 A

GS

V

= 4.5 V, ID = 15 A

GS

V

= 10 V, ID = 18 A, T

GS

V

= 5 V, ID = 16 A

DD

V

= 5 V, ID = 18 A

DD

= 250 μA

D

= 1 mA

D

= 125°C

J

= 125°C

J

Q1Q21.2

1.2

Q1 Q2

Q1

Q2

Q1 Q2

1.7

1.8

-5

-6

4.8

6.9

6.6

2.5

3.6

3.4 63

84

2.5

2.5 mV/°C

5.8

8.3

7.9

3.4

4.6

4.1

μA

V

mΩ

S

®

Power Stage

Dynamic Characteristics

C

iss

C

oss

C

rss

R

g

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Gate Resistance

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q

g(TOT)

Q

g(TOT)

Q

gs

Q

gd

Turn-On Delay Time

Rise Time

Turn-Off Delay Time

Fall Time

Total Gate Charge V

Gate to Source Charge

Gate to Drain “Miller” Charge

1326

Q1:

= 13 V, VGS = 0 V, f = 1 MHZ

V

DS

Q2:

= 13 V, VGS = 0 V, f = 1 MHZ

V

DS

Q1 Q2

Q1Q20.2

0.2

2175

342 574

78

118

0.9

1.0

1765 2895

455 765

115 180

2.9

3.2

pF

Ω

Q1 V

= 13 V, ID = 16 A, R

DD

Q2 V

= 13 V, ID = 18 A, R

DD

= 0V to 10 V

GS

= 0V to 4.5 V

GS

Q1 V

DD

I

= 16 A

D

Q2 V

DD

I

= 18 A

D

= 6 Ω

GEN

= 6 Ω

GEN

= 13 V,

Q1 Q2

7.7

9.51519

1.7310 10

19

34

24

49

1.4

2.21010

19

27

31

43

9

13

14

20

3.6

5.7

2.4

3.7

ns

nC

Electrical Characteristics T

= 25°C unless otherwise noted

J

Symbol Parameter Test Conditions Type Min Typ Max Units

Drain-Source Diode Characteristics

0.8

19 24

19

1.2

1.2 34

38

6

12 35

is determined

θCA

V

= 0 V, IS = 16 A (Note 2)

V

SD

t

rr

Q

rr

Notes:

1. R

is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R

θJA

by the user's board design.

Source-Drain Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

GS

V

= 0 V, IS = 18 A (Note 2)

GS

Q1 I

= 16 A, di/dt = 100 A/s

F

Q2 I

= 18 A, di/dt = 300 A/s

F

Q1 Q2

is guaranteed by design while R

θJC

ns

nC

FDMS3615S PowerTrench

V

®

Power Stage

a. 55 °C/W when mounted on

2

pad of 2 oz copper

a 1 in

c. 125 °C/W when mounted on a minimum pad of 2 oz copper

2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.

3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.

4. EAS of 38 mJ is based on starting TJ = 25 oC; N-ch: L = 0.3 mH, IAS = 16 A, VDD = 23 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 14.6 A.

5. EAS of 98 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 14 A, VDD = 23 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 21 A.

b. 55 °C/W when mounted on

2

a 1 in

pad of 2 oz copper

d. 125 °C/W when mounted on a minimum pad of 2 oz copper

FDMS3615S PowerTrench

0.0 0.5 1.0 1.5

0

9

18

27

36

45

V

GS

= 6 V

V

GS

= 4 V

V

GS

= 10 V

V

GS

= 3 V

V

GS

= 3.5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

I

D

, DRAIN CURRENT (A)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

0 9 18 27 36 45

0

2

4

6

8

VGS = 6 V

VGS = 3.5 V

PULSE DURA TION = 80 μs DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTA NCE

I

D

, DRAIN CURRENT (A)

V

GS

= 4 V

VGS = 3 V

V

GS

= 10 V

-75 -50 -25 0 25 50 75 100 125 150

0.6

0.8

1.0

1.2

1.4

1.6

ID = 16 A V

GS

= 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESISTANC E

T

J

, JUNCTION TEMPERATURE (

o

C)

2468

0

5

10

15

20

25

30

TJ = 125 oC

ID = 16 A

TJ = 25 oC

V

GS

, GATE TO SOURCE VOLTAGE (V)

r

DS(on)

,

DRAIN TO

SOURCE ON-RESISTANCE

(mΩ)

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

1234

0

9

18

27

36

45

TJ = 150 oC

V

DS

= 5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

I

D

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

50

TJ = -55 oC

TJ = 25 oC

TJ = 150 oC

V

GS

= 0 V

I

S

, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics (Q1 N-Channel) T

Figure 1.

On Region Characteristics Figure 2.

= 25°C unless otherwise noted

J

Normali z e d O n - R esistance

vs Drain Current and Gate Voltage

®

Power Stage

Fig u re 3. Norma l ized O n Res i stanc e

vs Junction Temperature

Figure 5. Transfer Characteristics

Figure 4.

On-Resistance vs Gate to

Source Voltage

Figure 6.

Source to Drain Diode

Forward Voltage vs Source Current

FDMS3615S PowerTrench

0 5 10 15 20

0

2

4

6

8

10

ID = 16 A

V

DD

= 16 V

V

DD

= 10 V

V

GS

, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 13 V

0.1 1 10

50

100

1000

3000

f = 1 MHz V

GS

= 0 V

CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

rss

C

oss

C

iss

25

0.001 0.01 0.1 1 10 100

1

10

20

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I

AS

, AVALANCHE CURRENT (A)

25 50 75 100 125 150

0

5

10

15

20

R

θJA

= 55 oC/W

V

GS

= 4.5 V

Limited by Package

V

GS

= 10 V

I

D

, DRAIN CURRENT (A)

T

A

, AMBIENT TEMPERATURE (

o

C)

0.01 0.1 1 10 100200

0.01

0.1

1

10

100

100 μs

DC

100 ms

10 ms

1 ms

1s

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS

LIMITED BY r

DS(on)

SINGLE PULSE T

J

= MAX RATED

R

θJA

= 125

o

C/W

T

A

= 25

o

C

10s

10-410-310-210

-1

110

100 1000

0.5

1

10

100

1000

SINGLE PULSE R

θJA

= 125 oC/W

P(

PK

), PEAK TRANSIENT POWER (W)

t, PULSE WIDTH (sec)

Typical Characteristics (Q1 N-Channel) T

Figure 7.

Gate Charge Characteristics Figure 8.

= 25°C unless otherwise noted

J

Capacitance vs Drain

to Source Voltage

®

Power Stage

Figure 9.

Unc l a m p e d I ndu c t i v e

Switching Capability

Figure 11. Forward Bias Safe

Op

erating Area

Figure 10.

Ma ximum Continuous D rai n

Current vs Ambient Temperature

Figure 12.

Si ngle Puls e Maximum

Power Dissipation

FDMS3615S PowerTrench

10

-4

10

-3

10

-2

10

-1

110

100 1000

0.001

0.01

0.1

1

2

SINGLE PULSE R

θJA

= 125 oC/W

(Note 1b)

DUTY CYCLE-DESCENDING ORDER

NORMALIZED THERMAL

IMPEDANCE,

Z

θJA

t, RECTANGULAR PU L SE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

P

DM

t

1

t

2

NOTES: DUTY FACTOR: D = t1/t

2

PEAK TJ = PDM x Z

θJA

x R

θJA

+ T

A

Typical Characteristics (Q1 N-Channel) T

Figure 13.

Junction-to-Ambient Transient Thermal Response Curve

= 25°C unless otherwise noted

J

®

Power Stage

FDMS3615S PowerTrench

0.0 0.5 1.0 1.5

0

9

18

27

36

V

GS

= 3 V

V

GS

= 5.5 V

V

GS

= 10 V

V

GS

= 4 V

V

GS

= 3.5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

I

D

, DRAIN CURRENT (A)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

0 9 18 27 36

0

2

4

6

8

VGS = 5.5 V

VGS = 3 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTA NC E

I

D

, DRAIN CURRENT (A)

V

GS

= 3.5 V

VGS = 4 V

V

GS

= 10 V

-75 -50 -25 0 25 50 75 100 125 150

0.6

0.8

1.0

1.2

1.4

1.6

ID = 18 A V

GS

= 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESISTANCE

T

J

, JUNCTION TEMPERATURE (

o

C)

2468

0

3

6

9

12

15

TJ = 125 oC

ID = 18 A

TJ = 25 oC

V

GS

, GATE TO SOURCE VO LTAGE (V)

r

DS(on)

,

DRAIN TO

SOURCE ON-RESISTANCE

(mΩ)

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

1.0 1.5 2.0 2.5 3.0 3.5

0

9

18

27

36

TJ = 150 oC

V

DS

= 5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

I

D

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

0.0 0.2 0.4 0.6 0.8 1.0

0.001

0.01

0.1

1

10

50

TJ = -55 oC

TJ = 25 oC

TJ = 125 oC

V

GS

= 0 V

I

S

, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics (Q2 N-Channel) T

Figure 14.

On-Region Characteristics Figure 15. Normalized on-Resistance vs Drain

= 25 °C unless otherwise noted

J

Current and Gate Voltage

®

Power Stage

Figure 16. Normalized On-Resistance

vs Junction Temperature

FDMS3615S Rev.C6

Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode

Figure 17. On-Resistance vs Gate to

Source Voltage

Forward Voltag e vs Source Current

FDMS3615S PowerTrench

0 8 16 24 32

0

2

4

6

8

10

ID = 18 A

V

DD

= 16 V

V

DD

= 10 V

V

GS

, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 13 V

0.1 1 10

50

100

1000

3000

25

f = 1 MHz V

GS

= 0 V

CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

rss

C

oss

C

iss

0.001 0.01 0.1 1 10 100200

1

10

30

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I

AS

, AVALANCHE CURRENT (A)

25 50 75 100 125 150

0

5

10

15

20

R

θJA

= 55 oC/W

V

GS

= 4.5 V

V

GS

= 10 V

I

D

, DRAIN CURRENT (A)

T

A

, AMBIENT TEMPERATURE (

o

C)

0.01 0.1 1 10 100200

0.01

0.1

1

10

100

DC

100 ms

10 ms

1 ms

1s

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS A REA IS

LIMITED BY r

DS(on)

SINGLE PULSE T

J

= MAX RATED

R

θJA

= 125

o

C/W

T

A

= 25

o

C

10s

10-410-310-210

-1

110

100 1000

0.5

1

10

100

1000

10000

SINGLE PULSE R

θJA

= 125 oC/W

P(

PK

), PEAK TRANSIENT POWER (W)

t, PULSE WIDTH (sec)

Typical Characteristics (Q2 N-Channel) T

Figure 20. Gate Charge Characteristics

= 25°C unless otherwise noted

J

Figure 21. Capacitance vs Drain

to Source Voltage

®

Power Stage

Figure 22. Unclamped Inductive

Switching Capability

Fi gure 2 4. For ward B ias Sa fe

Operating Area

FDMS3615S Rev.C6

Figu r e 23. Max i m um Conti n u ous Dra i n

Current vs Ambient Temperature

Figure 25. Single Pulse Maximum Power

Dissipation

10

-4

10

-3

10

-2

10

-1

110

100 1000

0.0001

0.001

0.01

0.1

1

2

SINGLE PULSE R

θJA

= 125 oC/W

(Note 1b)

DUTY CYCLE-DESCENDING ORDER

NORMALIZED THERMAL

IMPEDANCE,

Z

θJA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

P

DM

t

1

t

2

NOTES: DUTY FACTOR: D = t

1/t2

PEAK TJ = PDM x Z

θJA

x R

θJA

+ T

A

FDMS3615S PowerTrench

Typical Characteristics (Q2 N-Channel) T

Figure 26. Junction-to-Ambient Transient Thermal Response Curve

= 25 °C unless otherwise noted

J

®

Power Stage

FDMS3615S Rev.C6

0 50 100 150 200

-5

0

5

10

15

20

CURRENT (A)

TIME (ns)

di/dt = 300 A/μs

0 5 10 15 20 25

10

-6

10

-5

10

-4

10

-3

10

-2

TJ = 125 oC

TJ = 100 oC

TJ = 25 oC

I

DSS

, REVERSE LEAKAGE CURRENT (A)

VDS, REVERSE VOLTAGE (V)

Typical Characteristics (continued)

SyncFET Schottky body diode Characteristics

FDMS3615S PowerTrench

Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDMS3615S.

Figure 27. FDMS3615S SyncFET body

diode reverse recovery characteristic

Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device.

Figure 28. SyncFET body diode reverse leakage versus drain-source voltage

®

Power Stage

FDMS3615S Rev.C6

Application Information

1. Switch Node Ringing Suppression

Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions.

FDMS3615S PowerTrench

®

Power Stage

Figure 29. Power Stage phase node rising edge, High Side Turn on

*Patent Pending

Power Stage Device

Competitors solution

FDMS3615S Rev.C6

Figure 30. Shows the Power Stage in a buck converter topology

FDMS3615S PowerTrench

®

Power Stage

2. Recommended PCB Layout Guidelines

As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part.

Figure 31. Recommended PCB Layout

FDMS3615S Rev.C6

Following is a guideline, not a requirement which the PCB designer should consider:

1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic inductance and High Frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected depending upon the application.

2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance between the thermal and electrical performance of Power Stage.

3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be directly in line (as shown in figure 31) with the inductor for space savings and compactness.

4. The PowerTrench part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen the high-frequency ringing.

5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the MOSFET and turns the devices on and off as efficiently as possible. At higher-fre quency opera tion this imp edance can limit the gate current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional sw itching losses. Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This provides a very compact path for the drive signals and improves efficiency of the part.

®

Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the

FDMS3615S PowerTrench

®

Power Stage

6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.

7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction. Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias.

FDMS3615S Rev.C6

Dimensional Outline and Pad Layout

C

L

CPKG

PKG

5.10

4.90

6.10

5.90

C

3.00

2.80

3.81

1.02

0.82

TOP VIEW

SIDE VIEW

BOTTOM VIEW

14

85

123

4

876

0.10 CAB

0.05

C

2.25

2.05

5

0.58

0.38

NOTES: UNLESS OTHERWISE SPECIFIED

A) DOES NOT FULLY CONFORM TO

JEDEC RE GI S TRATI ON, MO-240, ISSUE B DATE D 10/2009.

B) ALL DIM E NS IONS ARE IN

MILLIMET ERS.

C) DIMENSIONS DO NOT I NCLUDE

BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCE ED 0.10MM.

D) DIMENS IONING AND TOLERANCING

PER ASME Y14.5M-1994.

E) IT IS RECOMMENDED TO HAVE NO

TRACES OR VIAS WITHIN THE KEEP OUT AREA.

F) DRAWIN G FILE NAME: PQN08EREV4.

SEE

DETAI L A

(SCALE: 2X)

0.05

0.00

0.30

0.20

0.08

C

PIN #1

IDEN T MA Y

APPEAR AS

OPTIONAL

SEATING PLANE

0.10 C

1.10

0.90

RE CO MM E NDE D LA ND P A T TE RN

0.65 TYP

1

2

3

4

5

6 7 8

1.27

1.32

1.12

A

0.10

C

2X

B

0.10 C

2X

0.00

1.60

2.52

1.21

2.31

1.18

1. 27 TY P

2.00

2.15

0.63

0.59

3.18

4.00 C

L

C

L

0.51

0.31

0.58

0.38

2.13

3.15

0.35

0.70

0.50

3.90

3.70

0.44

0.24

6X

0.71

0.61

KEEP OUT AREA

5.10

4.16

FDMS3615S Rev.C6

FDMS3615S PowerTrench

®

Power Stage

tm

®

tm

TRADEMARKS

The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor an d/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

2Cool™ AccuPower™ Auto-SPM™ AX-CAP™*

®

BitSiC Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ DEUXPEED Dual Cool™ EcoSPARK EfficentMax™ ESBC™

Fairchild Fairchild Semiconductor FACT Quiet Series™ FACT FAST FastvCore™ FETBench™

®

® ®

®

FlashWriter FPS™ F-PFS™ FRFET Global Power Resource Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MicroPak2™ MillerDrive™ MotionMax™ Motion-SPM™ mWSaver™ OptiHiT™ OPTOLOGIC OPTOPLANAR

®

*

®

PDP SPM™ Power-SPM™ PowerTrench PowerXS™

SM

Programmable Active Droop™ QFET QS™ Quiet Series™ RapidConfigure™

Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™ SPM STEALTH™ SuperFET SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS SyncFET™ Sync-Lock™ ®*

®

The Power Franchise The Right Technology for Your Success™

TinyBoost™ TinyBuck™ TinyCalc™

®

TinyLogic TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™

®

TranSiC TriFault Detect™ TRUECURRENT μSerDes™

®

UHC Ultra FRFET™ UniFET™ VCX™ VisualMax™ XS™

®

*

FDMS3615S PowerTrench

®

Power Stage

*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used here in:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

expected to result in a significant injury of the user.

ANTI-COUNTERFEITING POLICY

Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support Counterfeiting of semiconductor parts is a growing problem in the industry. All manufact ures of semiconductor products are experienci ng counterfeiting of their parts. Customers who inadvertently purchase counterfeit par ts e xperien ce man y prob lems such as loss of brand re put ati on, subst anda rd performance , failed application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the

proliferation of counterfeit parts. Fair child strongly encou rages cu stomer s to pur chase F airch ild part s either directly from Fairchild or fro m Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild ’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and en courage our cu stomers to d o their part in sto pping this practice by buying d irect or from authori zed distributors.

PRODUCT STATUS DEFINITIONS Definition of Terms

.

Datasheet Identification Product Status Definition

Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.

Rev. I55

FDMS3615S Rev.C6

Datasheet FDMS3615S Datasheet (Fairchild)

Specifications and Main Features

Frequently Asked Questions

User Manual