Datasheet FDMF6820A Datasheet (Fairchild)

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

April 2012

Benefits

 Ultra-Compact 6x6mm PQFN, 72% Space-Saving

Compared to Conventional Discrete Solutions

 Fully Optimized System Efficiency  Clean Switching Waveforms with Minimal Ringing  High-Current Handling

Features

 Over 93% Peak-Efficiency  High-Current Handling: 60A  High-Performance PQFN Copper-Clip Package  3-State 3.3V PWM Input Driver  Skip-Mode SMOD# (Low-Side Gate Turn Off) Input  Thermal Warning Flag for Over-Temperature

Condition

 Driver Output Disable Function (DISB# Pin)  Internal Pull-Up and Pull-Down for SMOD# and

DISB# Inputs, Respectively

 Fairchild PowerTrench

Clean Voltage Waveforms and Reduced Ringing

®

Technology MOSFETs for

 Fairchild SyncFET™ (Integrated Schottky Diode)

Technology in Low-Side MOSFET

 Integrated Bootstrap Schottky Diode  Adaptive Gate Drive Timing for Shoot-Through

Protection

 Under-Voltage Lockout (UVLO)  Optimized for Switching Frequencies up to 1MHz  Low-Profile SMD Package  Fairchild Green Packaging and RoHS Compliance  Based on the Intel

®

4.0 DrMOS Standard

Description

The XS™ DrMOS family is Fairchild’s next-generation, fully optimized, ultra-compact, integrated MOSFET plus driver power stage solution for high-current, highfrequency, synchronous buck DC-DC applications. The FDMF6820A integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6mm package.

With an integrated approach, the complete switching power stage is optimized with regard to driver and MOSFET dynamic performance, system inductance, and power MOSFET R Fairchild's high-performance PowerTrench technology, which dramatically reduces switch ringing, eliminating the need for snubber circuit in most buck converter applications.

A driver IC with reduced dead times and propagation delays further enhances the performance. A thermal warning function warns of a potential over-temperature situation. The FDMF6820A also incorporates a Skip Mode (SMOD#) for improved light-load efficiency. The FDMF6820A also provides a 3-state 3.3V PWM input for compatibility with a wide range of PWM controllers.

. XS™ DrMOS uses

DS(ON)

®

MOSFET

Applications

High-Performance Gaming Motherboards

  Compact Blade Servers, V-Core and Non-V-Core

DC-DC Converters

 Desktop Computers, V-Core and Non-V-Core

DC-DC Converters

 Workstations  High-Current DC-DC Point-of-Load Converters  Networking and Telecom Microprocessor Voltage

Regulators

 Small Form-Factor Voltage Regulator Modules

Ordering Information

Part Number Current Rating Package Top Mark

FDMF6820A 60A 40-Lead, Clipbond PQFN DrMOS, 6.0mm x 6.0mm Package FDMF6820A

Typical Application Circuit

V5V

C

VDRV

DISB#

PWM Input

DISB#

PWM

OFF

ON

Open-Drain Output

SMOD#

THWN#

DrMOS Block Diagram

C

VIN

VCIN

VDRV

FDMF6820A

CGND

PGND

VIN

R

BOOT

PHASE

VSWH

BOOT

C

BOOT

Figure 1. Typical Application Circuit

VIN 3V ~ 16V

L

OUT

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

V

OUT

C

OUT

VCIN

DISB#

PWM

THWN#

R

UP_PWM

R

DN_PWM

10µA

UVLO

V

CIN

Temp.

Sense

Input

3- State

Logic

VDRV

BOOT

VIN

Q1 HS Power MOSFET

GH

Logic

D

Level-Shift

Boot

GH

30kΩ

PHASE

Dead-Time

Control

V

DRV

GL

Logic

V

CIN

GL

30kΩ

VSWH

Q2 LS Power MOSFET

10µA

CGND

SMOD#

PGND

Figure 2. DrMOS Block Diagram

Pin Configuration

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 3. Bottom View Figure 4. Top View

Pin Definitions

Pin # Name Description

When SMOD#=HIGH, the low-side driver is the inverse of the PWM input. When

1 SMOD#

2 VCIN IC bias supply. Minimum 1µF ceramic capacitor is recommended from this pin to CGND.

3 VDRV

4 BOOT

5, 37, 41 CGND IC ground. Ground return for driver IC.

6 GH For manufacturing test only. This pin must float; it must not be connected to any pin.

7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.

8 NC

9 - 14, 42 VIN Power input. Output stage supply voltage.

15, 29 -

35, 43

16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET.

36 GL For manufacturing test only. This pin must float; it must not be connected to any pin.

38 THWN#

39 DISB#

40 PWM PWM signal input. This pin accepts a three-state 3.3V PWM signal from the controller.

VSWH

SMOD#=LOW, the low-side driver is disabled. This pin has a 10µA internal pull-up current source. Do not add a noise filter capacitor.

Power for the gate driver. Minimum 1µF ceramic capacitor is recommended to be connected as close as possible from this pin to CGND.

Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE.

No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience.

Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection.

Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module.

Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor.

Absolute Maximum Ratings

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

V

Supply Voltage Referenced to CGND -0.3 6.0 V

CIN

V

Drive Voltage Referenced to CGND -0.3 6.0 V

DRV

V

Output Disable Referenced to CGND -0.3 6.0 V

DISB#

V

PWM Signal Input Referenced to CGND -0.3 6.0 V

PWM

V

Skip Mode Input Referenced to CGND -0.3 6.0 V

SMOD#

V

Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V

GL

V

Thermal Warning Flag Referenced to CGND -0.3 6.0 V

THWN#

V

Power Input Referenced to PGND, CGND -0.3 25.0 V

IN

V

Bootstrap Supply

BOOT

V

High Gate Manufacturing Test Pin

GH

V

PHASE Referenced to CGND -0.3 25.0 V

PHS

V

Switch Node Input

SWH

V

Bootstrap Supply

BOOT

I

THWN# Sink Current -0.1 7.0 mA

THWN#

I

O(AV)

θ

JPCB

Output Current

Junction-to-PCB Thermal Resistance 2.7 °C/W

(1)

TA Ambient Temperature Range -40 +125 °C

TJ Maximum Junction Temperature +150 °C

T

Storage Temperature Range -55 +150 °C

STG

ESD Electrostatic Discharge Protection

Note:

1. I

is rated using Fairchild’s DrMOS evaluation board, at TA = 25°C, with natural convection cooling. This rating

O(AV)

is limited by the peak DrMOS temperature, T layout. This rating can be changed with different application settings.

Referenced to VSWH, PHASE -0.3 6.0 V Referenced to CGND -0.3 25.0 V Referenced to VSWH, PHASE -0.3 6.0 V

Referenced to CGND -0.3 25.0 V

Referenced to PGND, CGND (DC Only) -0.3 25.0 V

Referenced to PGND, <20ns -8.0 28.0 V Referenced to VDRV 22.0 V

Referenced to VDRV, <20ns 25.0 V

f

=300kHz, VIN=12V, V

SW

fSW=1MHz, VIN=12V, VO=1.0V 55

Human Body Model, JESD22-A114 2000

Charged Device Model, JESD22-C101 2500

= 150°C, and varies depending on operating conditions and PCB

J

=1.0V 60

O

A

V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

V

Control Circuit Supply Voltage 4.5 5.0 5.5 V

CIN

V

Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V

DRV

VIN Output Stage Supply Voltage 3.0 12.0 16.0

Note:

2. Operating at high V

can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes

IN

during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must

remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.

(2)

V

Electrical Characteristics

Typical values are VIN = 12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

Basic Operation

IQ Quiescent Current IQ=I

V

UVLO Threshold V

UVLO

V

UVLO_Hys

PWM Input (V

R

V

t

D_HOLD-OFF

V

t

PWM-OFF_MIN

PWM Input (V

R

V

t

D_HOLD-OFF

V

t

PWM-OFF_MIN

DISB# Input

V

t

PD_DISBL

t

PD_DISBH

SMOD# Input

V

t

PD_SLGLL

t

PD_SHGLH

UVLO Hysteresis 0.4 V

= V

CIN

Pull-Up Impedance V

UP_PWM

Pull-Down Impedance V

DN_PWM

PWM High Level Voltage 1.88 2.25 2.61 V

IH_PWM

3-State Upper Threshold 1.84 2.20 2.56 V

TRI_HI

3-State Lower Threshold 0.70 0.95 1.19 V

TRI_LO

PWM Low Level Voltage 0.62 0.85 1.13 V

IL_PWM

= 5V ±10%)

DRV

3-State Shut-Off Time 160 200 ns

3-State Open Voltage 1.40 1.60 1.90 V

HiZ_PWM

PWM Minimum Off Time 120 ns

= V

CIN

Pull-Up Impedance V

UP_PWM

Pull-Down Impedance V

DN_PWM

PWM High Level Voltage 2.00 2.25 2.50 V

IH_PWM

3-State Upper Threshold 1.94 2.20 2.46 V

TRI_HI

3-State Lower Threshold 0.75 0.95 1.15 V

TRI_LO

PWM Low Level Voltage 0.66 0.85 1.09 V

IL_PWM

= 5V ±5%)

DRV

3-State Shut-Off Time 160 200 ns

3-State Open Voltage 1.45 1.60 1.80 V

HiZ_PWM

PWM Minimum Off Time 120 ns

High-Level Input Voltage 2 V

IH_DISB

Low-Level Input Voltage 0.8 V

IL_DISB

I

Pull-Down Current 10 µA

PLD

Propagation Delay

High-Level Input Voltage 2 V

IH_SMOD

Low-Level Input Voltage 0.8 V

IL_SMOD

I

Pull-Up Current 10 µA

PLU

Propagation Delay

= 5V, V

CIN

= 5V, and TA = T

DRV

VCIN+IVDRV

Rising 2.9 3.1 3.3 V

CIN

=5V 26 kΩ

PWM

=0V 12 kΩ

PWM

=5V 26 kΩ

PWM

=0V 12 kΩ

PWM

PWM=GND, Delay Between DISB# from HIGH to LOW to GL from HIGH to LOW

PWM=GND, Delay Between DISB# from LOW to HIGH to GL from LOW to HIGH

PWM=GND, Delay Between SMOD# from HIGH to LOW to GL from HIGH to LOW

PWM=GND, Delay Between SMOD# from LOW to HIGH to GL from LOW to HIGH

= +25°C unless otherwise noted.

J

, PWM=LOW or HIGH or Float 2 mA

25 ns

10 ns

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

Continued on the following page…

Electrical Characteristics

Typical values are VIN = 12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

Thermal Warning Flag

T

Activation Temperature 150 °C

ACT

T

Reset Temperature 135 °C

RST

R

Pull-Down Resistance I

THWN

250ns Timeout Circuit

t

D_TIMEOUT

High-Side Driver (fSW = 1000kHz, I

R

SOURCE_GH

R

t

D_DEADON

t

PD_PLGHL

t

PD_PHGHH

t

PD_TSGHH

Timeout Delay

Output Impedance, Sourcing Source Current=100mA 1 Ω

Output Impedance, Sinking Sink Current=100mA 0.8 Ω

SINK_GH

t

Rise Time GH=10% to 90% 10 ns

R_GH

t

Fall Time GH=90% to 10% 10 ns

F_GH

LS to HS Deadband Time

PWM LOW Propagation Delay

PWM HIGH Propagation Delay (SMOD# =0)

Exiting 3-State Propagation Delay

= 5V, V

CIN

= 5V, and TA = T

DRV

=5mA 30 Ω

PLD

SW=0V, Delay Between GH from HIGH to LOW and GL from LOW to HIGH

= 30A, TA = +25°C)

OUT

GL Going LOW to GH Going HIGH,

1.0V GL to 10% GH

PWM Going LOW to GH Going LOW, V

IL_PWM

to 90% GH

PWM Going HIGH to GH Going HIGH, V

IH_PWM

PWM (From 3-State) Going HIGH to GH Going HIGH, V

= +25°C unless otherwise noted.

J

to 10% GH (SMOD# =0, I

to 10% GH

IH_PWM

D_LS

>0)

250 ns

15 ns

20 30 ns

30 ns

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

Low-Side Driver (fSW = 1000kHz, I

R

SOURCE_GL

R

SINK_GL

t

D_DEADOFF

t

PD_PHGLL

t

PD_TSGLH

Output Impedance, Sourcing Source Current=100mA 1 Ω

Output Impedance, Sinking Sink Current=100mA 0.5 Ω

Rise Time GL=10% to 90% 30 ns

R_GL

Fall Time GL=90% to 10% 15 ns

F_GL

HS to LS Deadband Time

PWM-HIGH Propagation Delay

Exiting 3-State Propagation Delay

= 30A, TA = +25°C)

OUT

SW Going LOW to GL Going HIGH,

2.2V SW to 10% GL

PWM Going HIGH to GL Going LOW, V

IH_PWM

PWM (From 3-State) Going LOW to GL Going HIGH, V

to 90% GL

IL_PWM

to 10% GL

15 ns

10 25 ns

20 ns

Boot Diode

VF Forward-Voltage Drop IF=20mA 0.3 V

VR Breakdown Voltage IR=1mA 22 V

PWM

GL

GH

to

VSWH

V

IH_PWM

90%

1.0V

10%

V

IL_PWM

90%

10%

1.2V

t

D_TIMEOUT

250ns Timeout)

(

2.2V

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

t

PD PHGLL

t

D_DEADON

t

PD_PLGHL

t

D_DEADOFF

Figure 5. PWM Timing Diagram

Typical Performance Characteristics

Test Conditions: VIN=12V, V unless otherwise specified.

60

55

50

(A)

45

OUT

40

35

30

25

20

15

10

Module Output Current, I

VIN= 12V, V

5

0

0 25 50 75 100 125 150

DRV

& V

CIN

PCB Temperature, T

Figure 6. Safe Operating Area Figure 7. Power Loss vs. Output Current

1.7 VIN= 12V, V

1.6

DRV

& V

CIN

1.5

1.4

1.3

1.2

1.1

1.0

Normalized Module Power Loss

0.9

100 200 300 400 500 600 700 800 900 1000 1100

Module Switching Frequency, F

Figure 8. Power Loss vs. Switching Frequency Figure 9. Power Loss vs. Input Voltage

1.15

VIN= 12V, V

1.10

= 1V, FSW= 300kHz, I

OUT

FSW= 300kHz

= 5V, V

OUT

= 5V, V

OUT

=1V, V

CIN

FSW= 1000kHz

= 1V

(°C)

PCB

= 1V, I

= 30A

OUT

SW

= 30A

OUT

=5V, V

(kHz)

DRV

=5V, L

=250nH, TA=25°C, and natural convection cooling,

OUT

11

300kHz

10

500kHz

9

800kHz

(W)

MOD

1000kHz

8

7

VIN= 12V, V

DRV

& V

CIN

= 5V, V

OUT

6

5

4

3

2

Module Power Loss, PL

1

0

0 5 10 15 20 25 30 35 40 45 50 55

Module Output Current, I

OUT

(A)

1.12 V

& V

DRV

CIN

= 5V, V

= 1V, FSW= 300kHz, I

OUT

1.10

1.08

1.06

1.04

1.02

1.00

Normalized Module Power Loss

0.98

4 6 8 1012141618

Module Input Voltage, V

(V)

IN

2.0

1.8

= 1V

OUT

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

= 30A

1.05

1.6

1.4

1.00

1.2

0.95

Normalized Module Power Loss

0.90

4.0 4.5 5.0 5.5 6.0

Driver Supply Voltage, V

DRV

& V

CIN

(V)

1.0

Normalized Module Power Loss

0.8

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

VIN= 12V, V

DRV

& V

Module Output Voltage, V

= 5V, FSW= 300kHz, I

CIN

OUT

(V)

OUT

= 30A

Figure 10. Power Loss vs. Driver Supply Voltage Figure 11. Power Loss vs. Output Voltage

Typical Performance Characteristics

Test Conditions: VIN=12V, V unless otherwise specified.

1.005 VIN= 12V, V

DRV

& V

CIN

1.000

0.995

0.990

0.985

0.980

Normalized Module Power Loss

0.975

200 250 300 350 400 450 500

Output Inductor, L

Figure 12. Power Loss vs. Output Inductor Figure 13. Driver Supply Current vs. Switching

26

(mA)

CIN

& I

DRV

VIN= 12V, V

24

22

20

= 1V, FSW= 300kHz, I

OUT

=1V, V

OUT

= 5V, FSW= 300kHz, V

(nH)

OUT

= 0A

OUT

CIN

OUT

=5V, V

= 1V, I

DRV

OUT

=5V, L

= 30A

=250nH, TA=25°C, and natural convection cooling,

OUT

70

VIN= 12V, V

DRV

& V

CIN

= 5V, V

OUT

= 1V, I

OUT

= 0A

60

(mA)

CIN

50

& I

DRV

40

30

20

Driver Supply Current, I

10

100 200 300 400 500 600 700 800 900 1000 1100

Module Switching Frequency, F

SW

Frequency

1.03

VIN= 12V, V

1.02

1.01

1.00

DRV

& V

CIN

= 5V, V

= 1V

OUT

FSW= 300kHz

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

(kHz)

18

16

Driver Supply Current, I

14

4.0 4.5 5.0 5.5 6.0

Driver Supply Voltage, V

DRV

& V

CIN

(V)

Figure 14. Driver Supply Current vs. Driver

Supply Voltage

3.2

UVLO

UP

DN

(V)

Driver IC Supply Voltage, V

3.1

CIN

3.0

2.9

2.8

2.7

2.6

-55 0 25 55 100 125 150

Driver IC Junction Temperature, TJ(oC)

0.99

FSW= 1000kHz

0.98

Normalized Driver Supply Current

0.97 0 5 10 15 20 25 30 35 40 45 50 55

Module Output Current, I

OUT

(A)

Figure 15. Driver Supply Current vs. Output Current

3.0 TA= 25°C

V

CIN

(V)

IH_PWM

V

HIZ_PWM

V

TRI_HI

TRI_LO

IL_PWM

2.5

(V)

PWM

2.0

1.5

1.0

PWM Threshold Voltage, V

0.5

4.50 4.75 5.00 5.25 5.50

Driver IC Supply Voltage, V

Figure 16. UVLO Threshold vs. Temperature Figure 17. PWM Threshold vs. Driver Supply Voltage

Typical Performance Characteristics

Test Conditions: V

3.0 V

CIN

2.5

(V)

PWM

2.0

1.5

1.0

PWM Threshold V ol tage, V

0.5

-55 0 25 55 100 125 150

Figure 18. PWM Threshold vs. Temperature Figure 19. SMOD# Threshold vs. Driver Supply

2.2

V

(V)

SMOD

SMOD# Threshold Voltage, V

CIN

2

1.8

1.6

1.4

1.2

-55 0 25 55 100 125 150

=5V, V

CIN

=5V, TA=25°C, and natural convection cooling, unless otherwise specified.

DRV

= 5V

Driver IC Junction Temperature, TJ(oC)

= 5V

Driver IC Junction Temperature, TJ(oC)

V

IH_PWM

V

TRI_HI

V

HIZ_PWM

V

IL_PWM

V

IH_SMOD#

V

IL_SMOD#

TRI_LO

2.2 TA= 25°C

(V)

2.0

SMOD

1.8

1.6

1.4

SMOD# Threshold Voltage, V

1.2

4.50 4.75 5.00 5.25 5.50

Driver IC Supply Voltage, V

CIN

(V)

Voltage

-9.0

V

= 5V

CIN

-9.5

(uA)

PLU

-10.0

-10.5

-11.0

-11.5

SMOD# Pull-Up Current, I

-12.0

-55 0 25 55 100 125 150

Driver IC Junction Temperature, TJ(oC)

V

IH_SMOD#

V

IL_SMOD#

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 20. SMOD# Threshold vs. Temperature Figure 21. SMOD# Pull-Up Current vs. Temperature

2.2

TA= 25°C

V

(V)

2.0

DISB

IH_DISB#

1.8

1.6 V

IL_DISB#

1.4

DISB# Threshold Voltage, V

1.2

4.50 4.75 5.00 5.25 5.50

Driver IC Supply Voltage, V

(V)

CIN

Figure 22. DISB# Threshold vs. Driver Supply

2.2 V

= 5V

CIN

(V)

2.0

DISB

V

IH_DISB#

1.8

1.6

V

1.4

IL_DISB#

DISB# Threshold Voltage, V

1.2

-55 0 25 55 100 125 150

Driver IC Junction Temperature, TJ(oC)

Figure 23. DISB# Threshold vs. Temperature

Voltage

Typical Performance Characteristics

Test Conditions: V

12.0 V

CIN

11. 5

(uA)

PLD

11. 0

10.5

10.0

9.5

DISB# Pull- Down Current, I

9.0

-55 0 25 55 100 125 150

Figure 24. DISB# Pull-Down Current vs.

=5V, V

CIN

= 5V

Driver IC Junction Temperature, TJ(oC)

=5V, TA=25°C, and natural convection cooling, unless otherwise specified.

DRV

Temperature

500

IF= 20mA

450

(mV)

400

F

350

300

250

200

150

Boot Diode Forward Voltage, V

100

-55 0 25 55 100 125 150

Driver IC Junction Temperature, TJ(oC)

Figure 25. Boot Diode Forward Voltage vs.

Temperature

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

A

p

Functional Description

The FDMF6820A is a driver-plus-FET module optimized for the synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1MHz.

VCIN and Disable (DISB#)

The VCIN pin is monitored by an Under-Voltage Lockout (UVLO) circuit. When V is enabled. When V disabled (GH, GL=0). The driver can also be disabled by pulling the DISB# pin LOW (DISB# < V holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the DISB# pin voltage HIGH (DISB# > V

Table 1. UVLO and Disable Logic

UVLO DISB# Driver State

0 X Disabled (GH, GL=0)

1 0 Disabled (GH, GL=0)

1 1 Enabled (see Table 2)

1 Open Disabled (GH, GL=0)

Note:

3. DISB# internal pull-down current source is 10µA.

Thermal Warning Flag (THWN#)

The FDMF6820A provides a thermal warning flag (THWN#) to warn of over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN# output returns to a highimpedance state once the temperature falls to the reset temperature (135°C). For use, the THWN# output requires a pull-up resistor, which can be connected to VCIN. THWN# does NOT disable the DrMOS module.

HIGH

THWN# Logic State

Normal Operation

LOW

Figure 26. THWN Operation

rises above ~3.1V, the driver

CIN

falls below ~2.7V, the driver is

CIN

), which

IL_DISB

).

IH_DISB

135°C Reset Temperature

150°C

ctivation

Tem

erature

Thermal Warning

T

J_driver IC

Three-State PWM Input

The FDMF6820A incorporates a three-state 3.3V PWM input gate drive design. The three-state gate drive has both logic HIGH level and LOW level, along with a three-state shutdown window. When the PWM input signal enters and remains within the three-state window for a defined hold-off time (t

D_HOLD-OFF

), both GL and GH are pulled LOW. This enables the gate drive to shut down both high-side and low-side MOSFETs to support features such as phase shedding, which is common on multi-phase voltage regulators.

Exiting Three-State Condition

When exiting a valid three-state condition, the FDMF6820A follows the PWM input command. If the PWM input goes from three-state to LOW, the low-side MOSFET is turned on. If the PWM input goes from three-state to HIGH, the high-side MOSFET is turned on. This is illustrated in Figure 27. The FDMF6820A design allows for short propagation delays when exiting

the three-state window (see Electrical Characteristics).

Low-Side Driver

The low-side driver (GL) is designed to drive a groundreferenced, low-R

, N-channel MOSFET. The bias

DS(ON)

for GL is internally connected between the VDRV and CGND pins. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB#=0V), GL is held LOW.

High-Side Driver

The high-side driver (GH) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor (C at PGND, allowing C internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from C and delivered to the gate of Q1. As Q1 turns on, V rises to V

, forcing the BOOT pin to VIN + V

IN

provides sufficient V the switching cycle, Q1 is turned off by pulling GH to V

. C

SWH

is then recharged to V

BOOT

PGND. GH output is in-phase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the three-state window for longer than the three-state hold-off time, t

). During startup, V

BOOT

to charge to V

BOOT

enhancement for Q1. To complete

GS

DRV

when V

D_HOLD-OFF

is held

SWH

through the

BOOT

SWH

BOOT

SWH

, which

falls to

.

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

V

Adaptive Gate Drive Circuit

The driver IC advanced design ensures minimum MOSFET dead-time, while eliminating potential shootthrough (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. Figure 27 provides the relevant timing waveforms. To prevent overlap during the LOW-to-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes

V

PWM

GH

to

SWH

GL

IH_PWM

CCM

90%

1.0V

V

IL_PWM

2.2

t

R_GL

10%

t

D_HOLD-OFF

t

DCM

F_GL

V

IH_PWM

t

R_GH

HIGH, Q2 begins to turn off after a propagation delay (t

PD_PHGLL

Q1 begins to turn on after adaptive delay t

). Once the GL pin is discharged below 1.0V,

D_DEADON

.

To preclude overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the GH-to-PHASE pin pair. When the PWM signal goes LOW, Q1 begins to turn off after a propagation delay (t

PD_PLGHL

). Once the voltage across GH-to-PHASE falls below 2.2V, Q2 begins to turn on after adaptive delay t

V

TRI_HI

t

F_GH

IH_PWM

DCM

D_DEADOFF

.

V

IH_PWM

V

TRI_HI

V

TRI_LO

V

IL_PWM

90%

10%

V

IN

V

OUT

90%

10%

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

t

PD_PHGLL

t

Notes: t

= propagation delay from external sign al (PWM, SMOD#, etc.) to IC generated signal. Example (t

PD_xxx

= delay from IC generated signal to IC generated signal. Example (t

t

D_xxx

PWM

Exiting 3-state

t

= PWM rise to LS VGS fall, V

PD_PHGLL

= PWM fall to HS VGS fall, V

t

PD_PLGHL

t

= PWM rise to HS VGS rise, V

PD_PHGHH

SMOD# Dead Times t

= SMOD# fall to LS VGS fall, V

PD_SLGLL

t

= SMOD# rise to LS VGS rise, V

PD_SHGLH

D_DEADON

t

PD_PLGHL

t

D_DEADOFF

to 90% LS VGS t

IH_PWM

to 90% HS VGS t

IL_PWM

to 10% HS VGS (SMOD# held LOW)

IH_PWM

to 90% LS VGS t

IL_SMOD

to 10% LS VGS t

IH_SMOD

Enter

3-state

D_DEADON

t

PD_TSGHH

Exit

– LS VGS (GL) LOW to HS VGS (GH) HIGH)

PD_TSGHH

PD_TSGLH

D_DEADON

D_DEADOFF

Figure 27. PWM and 3-StateTiming Diagram

t

D_HOLD-OFF

Enter

3-state

PD_PHGLL

= PWM 3-state to HIGH to HS VGS rise, V

= PWM 3-state to LOW to LS VGS rise, V

= LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS

= VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS

t

PD_TSGHH

Exit

3-state

– PWM going HIGH to LS VGS (GL) going LOW)

IH_PWM

to 10% LS VGS

IL_PWM

t

D_HOLD-OFF

Enter

3-state

to 10% HS VGS

t

PD_TSGLH

Exit

3-state

V

#

Skip Mode (SMOD#)

The Skip Mode function allows for higher converter efficiency when operated in light-load conditions. When SMOD# is pulled LOW, the low-side MOSFET gate signal is disabled (held LOW), preventing discharge of the output capacitors as the filter inductor current attempts reverse current flow – known as “Diode Emulation” Mode.

When the SMOD# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode. This mode allows for gating on the Low Side MOSFET. When the SMOD# pin is pulled LOW, the low-side MOSFET is gated off. If the SMOD# pin is connected to the PWM controller, the controller can actively enable or disable SMOD# when the controller detects light-load condition from output current sensing. Normally this pin is active

LOW. See Figure 28 for timing delays.

Table 2. SMOD# Logic

DISB# PWM SMOD# GH GL

0 X X 0 0

1 3-State X 0 0

1 0 0 0 0

1 1 0 1 0

1 0 1 0 1

1 1 1 1 0

Note:

4. The SMOD# feature is intended to have a short propagation delay between the SMOD# signal and the low-side FET VGS response time to control diode emulation on a cycle-by-cycle basis.

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

SMOD

PWM

GH

to

SWH

V

SWH

GL

IH_PWM

t

PD_PHGLL

t

D_DEADON

90%

1.0V

t

PD_PLGHL

V

IL_PWM

90%

10%

2.2V

t

D_DEADOFF

10%

CCM

V

CCM

t

PD_SLGLL

Delay from SMOD# going

LOW to LS VGSLOW

HS turn -on with SMOD# LOW

IL_SMOD

V

IH_PWM

t

PD_PHGHH

10%

V

IH_SMOD

DCM

t

Delay from SMOD# going

HIGH to LS VGSHIGH

PD_SHGLH

10%

V

OUT

Figure 28. SMOD# Timing Diagram

A

V

Application Information

Supply Capacitor Selection

For the supply inputs (V capacitor is recommended to reduce noise and to supply the peak current. Use at least a 1µF X7R or X5R capacitor. Keep this capacitor close to the VCIN pin and connect it to the GND plane with vias.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor (C

), as shown in Figure 30. A bootstrap capacitance

BOOT

of 100nF X7R or X5R capacitor is usually adequate. A series bootstrap resistor may be needed for specific applications to improve switching noise immunity. The boot resistor may be required when operating above

and is effective at controlling the high-side

15V

IN

MOSFET turn-on slew rate and V values from 0.5 to 3.0Ω are typically effective in reducing VSWH overshoot.

V

5V

), a local ceramic bypass

CIN

overshoot. R

SHW

I

5V

C

VDRV

R

CIN

BOOT

C

VCIN Filter

The VDRV pin provides power to the gate drive of the high-side and low-side power MOSFET. In most cases, it can be connected directly to VCIN, the pin that provides power to the logic section of the driver. For additional noise immunity, an RC filter can be inserted between the VDRV and VCIN pins. Recommended values would be 10Ω and 1µF.

Power Loss and Efficiency

Measurement and Calculation

Refer to Figure 30 for power loss testing method.

Power loss calculations are:

P

=(VIN x IIN) + (V5V x I5V) (W) (1)

IN

P

SW=VSW

P

OUT=VOUT

P

LOSS_MODULE=PIN

P

LOSS_BOARD=PIN

EFF

CIN

x I

(W) (2)

OUT

x I

(W) (3)

OUT

- PSW (W) (4)

- P

(W) (5)

OUT

=100 x PSW/PIN (%) (6)

MODULE

BOARD

C

VIN

=100 x P

I

IN

V

(%) (7)

OUT/PIN

IN

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

DISB#

PWM

Input

OFF

ON

Open -

Drain

Output

DISB#

PWM Input

OFF

Open

Drain

Output

VDRV

DISB#

PWM

SMOD#

THWN#

Figure 29. Block Diagram With V

V

5V

ON

-

I

5V

C

VDRV

DISB#

PWM

SMOD#

THWN#

VCIN

FDMF6820A

FDM 67 5

CGND

VDRV

FDMF6820A

CGND

PGND

VCIN

FDM 5

PGND

VIN

R

BOOT

VSWH

PHASE

VIN

BOOT

VSWH

PHASE

R

C

BOOT

VIN

C

BOOT

V V

I

IN

L

OUT

SW

CIN

Filter

V

IN

C

OUT

I

OUT

V

OUT

C

BOOT

V V

L

OUT

SW

C

OUT

I

OUT

Figure 30. Power Loss Measurement

PCB Layout Guidelines

Figure 31 and Figure 32 provide an example of a proper layout for the FDMF6820A and critical components. All of the high-current paths, such as VIN, VSWH, VOUT, and GND copper, should be short and wide for low inductance and resistance. This aids in achieving a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance.

Recommendations for PCB Designers

1. Input ceramic bypass capacitors must be placed

close to the VIN and PGND pins. This helps reduce the high-current power loop inductance and the input current ripple induced by the power MOSFET switching operation.

2. The V

addition to being the high-frequency current path from the DrMOS package to the output inductor, it serves as a heat sink for the low-side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low-impedance path for the high-frequency, high-current flow between the DrMOS and inductor. The short and wide trace minimizes electrical losses as well as the DrMOS temperature rise. Note that the V voltage and high-frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace acts as a heat sink for the lower MOSFET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission.

3. An output inductor should be located close to the

FDMF6820A to minimize the power loss due to the V

SWH

inductor dissipation does not heat the DrMOS.

4. PowerTrench

stage and are effective at minimizing ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The selected resistor and capacitor need to be the proper size for power dissipation.

5. VCIN, VDRV, and BOOT capacitors should be

placed as close as possible to the VCIN-to-CGND, VDRV-to-CGND, and BOOT-to-PHASE pin pairs to ensure clean and stable power. Routing width and length should be considered as well.

6. Include a trace from the PHASE pin to the VSWH pin

to improve noise margin. Keep this trace as short as possible.

7. The layout should include the option to insert a

small-value series boot resistor between the boot capacitor and BOOT pin. The boot-loop size, including R possible. The boot resistor may be required when operating above 15VIN and is effective at controlling the high-side MOSFET turn-on slew rate and V overshoot. R margin in synchronous buck designs that may have

copper trace serves two purposes. In

SWH

node is a high-

SWH

copper trace. Care should also be taken so the

®

MOSFETs are used in the output

and C

BOOT

can improve noise operating

BOOT

, should be as small as

BOOT

SHW

noise issues due to ground bounce or high positive and negative V

ringing. Inserting a boot

SWH

resistance lowers the DrMOS efficiency. Efficiency versus noise trade-offs must be considered. R

BOOT

values from 0.5Ω to 3.0Ω are typically effective in reducing V

overshoot.

SWH

8. The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative V

SWH

ringing.

9. GND pad and PGND pins should be connected to the GND copper plane with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of the gate driver and MOSFETs.

10. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to the PGND capacitor. This may lead to excess current flow through the BOOT diode.

11. The SMOD# and DISB# pins have weak internal pull-up and pull-down current sources, respectively. These pins should not have any noise filter capacitors. Do not to float these pins unless absolutely necessary.

12. Use multiple vias on the VIN and VOUT copper

areas to interconnect top, inner, and bottom layers to distribute current flow and heat conduction. Do not put many vias on the VSWH copper to avoid extra parasitic inductance and noise on the switching waveform. As long as efficiency and thermal performance are acceptable, place only one VSWH copper on the top layer and use no vias on the VSWH copper to minimize switch node parasitic noise. Vias should be relatively large and of reasonably low inductance. Critical highfrequency components, such as R

BOOT

, C

BOOT

, RC snubber, and bypass capacitors; should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they can be connected from the backside through a network of low-inductance vias.

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 31. PCB Layout Example (Top View)

Figure 32. PCB Layout Example (Bottom View)

Physical Dimensions

B

0.10

2X

0.50

0.40

2.00±0.10

0.10 C

0.08 C

0.40

(0.70)

20

11

C

21

1.10

0.90

6.00

TOP VIEW

FRONT VIEW

4.40±0.10

(2.20)

10

(0.20)

BOTTOM VIEW

0.30

0.20

DETAIL 'A'

SCALE: 2:1

(0.20)

0.05

0.00

0.30

0.20

30

31

2.40±0.10

1.50±0.10

40

1

2.00±0.10

0.50

Figure 33. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

.

PIN#1 INDICATOR

A

6.00

0.25

1.60

0.10

C

2X

0.60

SEE DETAIL 'A'

0.10 CAB

0.05

SEATING

PLANE

C

(40X)

0.20

0.50

0.30

NOTES: UNLESS OTHERWISE SPECIFIED

A) DOES NOT FULLY CONFORM TO JEDEC

B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV2

C

5.80

4.50

31

2.50

40

1

0.50 TYP

2.10

LAND PATTERN

RECOMMENDATION

PIN #1 INDICATOR

(40X)

REGISTRATION MO-220, DATED MAY/2005.

2130

20

11

10

0.35

0.15

2.10

0.40

0.65

FDMF6820A — Extra-Small, High-Performance, High-Frequency DrMOS Module

Datasheet FDMF6820A Datasheet (Fairchild)

Specifications and Main Features

Frequently Asked Questions

User Manual