Datasheet FDMF6708N Datasheet (Fairchild)

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

April 2012

Benefits

 Ultra-Compact 6x6mm PQFN, 72% Space-Saving

Compared to Conventional Discrete Solutions

 Fully Optimized System Efficiency  Clean Switching Waveforms with Minimal Ringing  High-Current Handling

Features

 Over 93% Peak-Efficiency  High-Current Handling: 50A  High-Performance PQFN Copper-Clip Package  3-State 5V PWM Input Driver  Automatic Diode Emulation (Skip Mode) enabled

through ZCD_EN# Input

 Thermal Warning Flag for Over-Temperature

Condition

 Driver Output Disable Function (DISB# Pin)  Internal Pull-Up and Pull-Down for ZCD_EN# and

DISB# Inputs, Respectively

 Fairchild PowerTrench

Clean Voltage Waveforms and Reduced Ringing

®

Technology MOSFETs for

 Fairchild SyncFET™ (Integrated Schottky Diode)

Technology in Low-Side MOSFET

 Integrated Bootstrap Schottky Diode  Adaptive Gate Drive Timing for Shoot-Through

Protection

 Under-Voltage Lockout (UVLO)  Optimized for Switching Frequencies up to 1MHz  Low-Profile SMD Package  Fairchild Green Packaging and RoHS Compliance  Based on the Intel

®

4.0 DrMOS Standard

Description

The XS™ DrMOS family is Fairchild’s next-generation, fully optimized, ultra-compact, integrated MOSFET plus driver power stage solution for high-current, highfrequency, synchronous buck DC-DC applications. The FDMF6708N integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6mm package.

With an integrated approach, the complete switching power stage is optimized with regard to driver and MOSFET dynamic performance, system inductance, and power MOSFET R Fairchild's high-performance PowerTrench technology, which dramatically reduces switch ringing, eliminating the need for snubber circuit in most buck converter applications.

A driver IC with reduced dead times and propagation delays further enhances the performance. A thermal warning function warns of a potential over-temperature situation. The FDMF6708N also incorporates a ZeroCross Detect (ZCD_EN#) for improved light-load efficiency. The FDMF6708N also provides a 3-state 5V PWM input for compatibility with a wide range of PWM controllers.

. XS™ DrMOS uses

DS(ON)

®

MOSFET

Applications

Notebook Computers

  High-Performance Gaming Motherboards  Compact Blade Servers & Workstations, V-Core

and Non-V-Core DC-DC Converters

 Desktop Computers, V-Core and Non-V-Core

DC-DC Converters

 High-Current DC-DC Point-of-Load Converters  Networking and Telecom Microprocessor Voltage

Regulators

 Small Form-Factor Voltage Regulator Modules

Ordering Information

Part Number Current Rating Package Top Mark

FDMF6708N 50A 40-Lead, Clipbond PQFN DrMOS, 6.0mm x 6.0mm Package FDMF6708N

Typical Application Circuit

V5V

C

VDRV

DISB#

PWM Input

DISB#

PWM

OFF

ON

Open-Drain Output

ZCD_EN#

THWN#

DrMOS Block Diagram

C

VIN

VCIN

VDRV

FDMF6708N

CGND

PGND

VIN

R

BOOT

PHASE

VSWH

BOOT

C

BOOT

Figure 1. Typical Application Circuit

VIN 3V ~ 24V

L

OUT

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

V

OUT

C

OUT

VCIN

DISB#

PWM

THWN#

R

UP_PWM

R

DN_PWM

10µA

UVLO

V

CIN

Temp.

Sense

Input

3- State

Logic

VDRV

BOOT

VIN

Q1 HS Power MOSFET

GH

Logic

D

Level-Shift

Boot

GH

20kΩ

PHASE

Dead-Time

Control

V

DRV

GL

Logic

V

CIN

GL

VSWH

Q2 LS Power MOSFET

10µA

CGND

ZCD_EN#

PGND

Figure 2. DrMOS Block Diagram

Pin Configuration

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 3. Bottom View Figure 4. Top View

Pin Definitions

Pin # Name Description

When ZCD_EN#=HIGH, the low-side driver is the inverse of the PWM input. When

1 ZCD_EN#

2 VCIN IC bias supply. Minimum 1µF ceramic capacitor is recommended from this pin to CGND.

3 VDRV

4 BOOT

5, 37, 41 CGND IC ground. Ground return for driver IC.

6 GH For manufacturing test only. This pin must float; it must not be connected to any pin.

7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.

8 NC

9 - 14, 42 VIN Power input. Output stage supply voltage.

15, 29 -

35, 43

16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET.

36 GL For manufacturing test only. This pin must float; it must not be connected to any pin.

38 THWN#

39 DISB#

40 PWM PWM signal input. This pin accepts a three-state 5V PWM signal from the controller.

VSWH

ZCD_EN#=LOW, diode emulation is enabled. This pin has a 10µA internal pull-up current source. Do not add a noise filter capacitor.

Power for the gate driver. Minimum 1µF ceramic capacitor is recommended to be connected as close as possible from this pin to CGND.

Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE.

No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience.

Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection.

Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module.

Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor.

Absolute Maximum Ratings

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

V

Supply Voltage Referenced to CGND -0.3 7.0 V

CIN

V

Drive Voltage Referenced to CGND -0.3 7.0 V

DRV

V

Output Disable Referenced to CGND -0.3 7.0 V

DISB#

V

PWM Signal Input Referenced to CGND -0.3 7.0 V

PWM

V

Note:

1. I

ZCD Enable Signal Input Referenced to CGND -0.3 7.0 V

ZCD_EN#

VGL Low Gate Manufacturing Test Pin Referenced to CGND -0.3 7.0 V

Thermal Warning Flag Referenced to CGND -0.3 7.0 V

THWN#

VIN Power Input Referenced to PGND, CGND -0.3 30.0 V

V

Bootstrap Supply

BOOT

VGH High Gate Manufacturing Test Pin

V

PHASE Referenced to CGND -0.3 30.0 V

PHS

V

Switch Node Input

SWH

V

Bootstrap Supply

BOOT

I

THWN# Sink Current -0.1 7.0 mA

THWN#

I

O(AV)

θ

JPCB

Output Current

Junction-to-PCB Thermal Resistance 3.5 °C/W

(1)

Referenced to VSWH, PHASE -0.3 7.0 V

Referenced to CGND -0.3 30.0 V

Referenced to VSWH, PHASE -0.3 7.0 V

Referenced to CGND -0.3 30.0 V

Referenced to PGND, CGND (DC Only) -0.3 30.0 V

Referenced to PGND,<20ns -8.0 33.0 V

Referenced to VDRV 22.0 V

Referenced to VDRV,<20ns 25.0 V

f

=300kHz, VIN=12V, VO=1.0V 50

SW

fSW=1MHz, VIN=12V, VO=1.0V 45

TA Ambient Temperature Range -40 +125 °C

TJ Maximum Junction Temperature +150 °C

T

Storage Temperature Range -55 +150 °C

STG

ESD Electrostatic Discharge Protection

is rated using Fairchild’s DrMOS evaluation board, at TA = 25°C, with natural convection cooling. This rating

O(AV)

is limited by the peak DrMOS temperature, T

Human Body Model, JESD22-A114 2000

Charged Device Model, JESD22-C101 2500

= 150°C, and varies depending on operating conditions and PCB

J

layout. This rating can be changed with different application settings.

A

V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

V

Control Circuit Supply Voltage 4.5 5.0 5.5 V

CIN

V

Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V

DRV

VIN Output Stage Supply Voltage 3.0 12.0 24.0

Note:

2. Operating at high V

can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes

IN

during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must

remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.

(2)

V

Electrical Characteristics

Typical values are VIN = 12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

Basic Operation

IQ Quiescent Current IQ=I

V

UVLO Threshold V

UVLO

V

UVLO_Hys

PWM Input (V

R

V

t

D_HOLD-OFF

V

t

PWM-OFF_MIN

PWM Input (V

R

V

t

D_HOLD-OFF

V

t

PWM-OFF_MIN

DISB# Input

V

t

PD_DISBL

t

PD_DISBH

ZCD_EN# Input

V

IH_ZCD_EN

V

IL_ZCD_EN

t

PD_ZLGLL

t

PD_ZHGLH

UVLO Hysteresis 0.35 V

= V

CIN

Pull-Up Impedance V

UP_PWM

Pull-Down Impedance V

DN_PWM

PWM High Level Voltage 3.15 3.80 4.45 V

IH_PWM

3-State Upper Threshold 3.10 3.75 4.40 V

TRI_HI

3-State Lower Threshold 1.05 1.40 1.90 V

TRI_LO

PWM Low Level Voltage 0.70 1.00 1.30 V

IL_PWM

= 5V ±10%)

DRV

3-State Shut-Off Time 150 ns

3-State Open Voltage 2.20 2.50 2.80 V

HiZ_PWM

PWM Minimum Off Time 70 ns

= V

CIN

Pull-Up Impedance V

UP_PWM

Pull-Down Impedance V

DN_PWM

PWM High Level Voltage 3.35 3.80 4.25 V

IH_PWM

3-State Upper Threshold 3.30 3.75 4.20 V

TRI_HI

3-State Lower Threshold 1.10 1.40 1.75 V

TRI_LO

PWM Low Level Voltage 0.74 1.00 1.26 V

IL_PWM

= 5V ±5%)

DRV

3-State Shut-Off Time 150 ns

3-State Open Voltage 2.30 2.50 2.70 V

HiZ_PWM

PWM Minimum Off Time 70 ns

High-Level Input Voltage 2 V

IH_DISB

Low-Level Input Voltage 0.8 V

IL_DISB

I

Pull-Down Current 10 µA

PLD

Propagation Delay

High-Level Input Voltage 2 V

Low-Level Input Voltage 0.8 V

I

Pull-Up Current 10 µA

PLU

Propagation Delay

= 5V, V

CIN

= 5V, and TA = T

DRV

VCIN+IVDRV

Rising 3.3 V

CIN

=5V 20 kΩ

PWM

=0V 20 kΩ

PWM

=5V 20 kΩ

PWM

=0V 20 kΩ

PWM

PWM=GND, Delay Between DISB# from HIGH to LOW to GL from HIGH to LOW

PWM=GND, Delay Between DISB# from LOW to HIGH to GL from LOW to HIGH

= +25°C unless otherwise noted.

J

, PWM=LOW or HIGH or Float 2 mA

220 ns

520 ns

PWM=GND, Delay Between ZCD_EN# from HIGH to LOW to GL from HIGH to

1800 ns

LOW

PWM=GND, Delay Between ZCD_EN# from LOW to HIGH to GL from LOW to

20 ns

HIGH

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Continued on the following page…

Electrical Characteristics

Typical values are VIN = 12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

Thermal Warning Flag

T

Activation Temperature 150 °C

ACT

T

Reset Temperature 135 °C

RST

R

Pull-Down Resistance 5kΩ resistor pull-up to V

THWN

High-Side Driver (fSW = 1000kHz, I

R

SOURCE_GH

R

SINK_GH

t

D_DEADON

t

PD_PLGHL

t

PD_PHGHH

t

PD_TSGHH

Output Impedance, Sourcing Source Current=50mA 0.8 Ω

Output Impedance, Sinking Sink Current=50mA 0.6 Ω

Rise Time GH=10% to 90% 10 ns

R_GH

Fall Time GH=90% to 10% 10 ns

F_GH

LS to HS Deadband Time

PWM LOW Propagation Delay

PWM HIGH Propagation Delay (ZCD_EN# =0)

Exiting 3-State Propagation Delay

= 5V, V

CIN

= 5V, and TA = T

DRV

= 30A, TA = +25°C)

OUT

GL Going LOW to GH Going HIGH,

1.7V GL to 10% GH

PWM Going LOW to GH Going LOW, V

IL_PWM

to 90% GH

PWM Going HIGH to GH Going HIGH, V

IH_PWM

PWM (From 3-State) Going HIGH to GH Going HIGH, V

= +25°C unless otherwise noted.

J

60 Ω

CIN

to 10% GH (ZCD_EN# =0, I

to 10% GH

IH_PWM

D_LS

>0)

20 ns

25 ns

35 ns

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Low-Side Driver (fSW = 1000kHz, I

R

SOURCE_GL

R

SINK_GL

t

D_DEADOFF

t

PD_PHGLL

t

PD_TSGLH

t

GL-ON_MIN

Output Impedance, Sourcing Source Current=50mA 0.9 Ω

Output Impedance, Sinking Sink Current=50mA 0.4 Ω

Rise Time GL=10% to 90% 20 ns

R_GL

Fall Time GL=90% to 10% 10 ns

F_GL

HS to LS Deadband Time

PWM-HIGH Propagation Delay

Exiting 3-State Propagation Delay

GL Minimum On Time in DCM

= 30A, TA = +25°C)

OUT

SW Going LOW to GL Going HIGH,

1.7V SW to 10% GL

PWM Going HIGH to GL Going LOW, V

IH_PWM

PWM (From 3-State) Going LOW to GL Going HIGH, V

V

ZCD_EN#

20 ns

to 90% GL

IL_PWM

to 10% GL

20 ns

30 ns

=0V 350 ns

Boot Diode

VF Forward-Voltage Drop IF=1mA 0.6 V

VR Breakdown Voltage IR=1mA 22 V

PWM

GL

GH

to

VSWH

V

IH_PWM

90%

1.7V

10%

V

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

IL_PWM

10%

90%

1.7V

t

PD PHGLL

t

D_DEADON

t

PD PLGHL

t

D_DEADOFF

Figure 5. PWM Timing Diagram

Typical Performance Characteristics

Test Conditions: VIN=12V or 19V, V cooling, unless otherwise specified.

50

45

40

(A)

35

OUT

30

25

20

FSW= 300kHz

FSW= 1000kHz

15

10

Module Output Current, I

5

VIN= 12V, V

0

0 25 50 75 100 125 150

DRV

& V

CIN

= 5V, V

OUT

PCB Temperature, T

Figure 6. Safe Operating Area for 12V

11

12Vin 300kHz

10

12Vin 500kHz

9

8

7

12Vin 800kHz

12Vin 1000kHz

(W)

MOD

6

5

4

3

2

Module Power Loss, PL

1

0

0 5 10 15 20 25 30 35 40 45

V

& V

DRV

CIN

Module Output Current, I

= 1V

PCB

= 5V, V

OUT

(°C)

OUT

=1V, V

= 1V

(A)

CIN

IN

=5V, V

DRV

=5V, L

=250nH, TA=25°C, and natural convection

OUT

50

45

40

(A)

35

OUT

30

25

20

15

FSW= 300kHz

FSW= 1000kHz

10

Module Output Current, I

5

VIN= 19V, V

0

0 25 50 75 100 125 150

& V

CIN

= 5V, V

DRV

PCB Temperature, T

OUT

= 1V

PCB

(°C)

Figure 7. Safe Operating Area for 19VIN

11

19Vin 300kHz

10

19Vin 500kHz

9

8

7

19Vin 800kHz

19Vin 1000kHz

(W)

MOD

6

5

4

3

2

Module Power Loss, PL

1

0

0 5 10 15 20 25 30 35 40 45

V

& V

= 5V, V

DRV

CIN

Module Output Current, I

OUT

= 1V

(A)

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 8. Power Loss vs. Output Current for 12V

1.6 VIN= 12V, V

1.5

DRV

& V

CIN

= 5V, V

OUT

= 1V, I

OUT

= 30A

Figure 9. Power Loss vs. Output Current for 19V

IN

1.16 V

& V

DRV

CIN

= 5V, V

= 1V, FSW= 300kHz, I

OUT

1.12

OUT

IN

= 30A

1.4

1.3

1.2

1.08

1.04

1.1

1.00

1.0

Normalized Module Power Loss

0.9 100 200 300 400 500 600 700 800 900 1000 1100

Module Switching Frequency, F

(kHz)

SW

Normalized Module Power Loss

0.96 4 6 8 10 12 14 16 18 20

Module Input Voltage, V

(V)

IN

Figure 10. Power Loss vs. Sw itching Frequency Figure 11. Power Loss vs. Input Voltag e

Typical Performance Characteristics

Test Conditions: VIN=12V, V unless otherwise specified.

1.25

1.20

1.15

1.10

1.05

1.00

0.95

Normalized Module Power Loss

0.90

0.85

VIN= 12V, V

= 1V, FSW= 300kHz, I

OUT

4.0 4.5 5.0 5.5 6.0

Driver Supply Voltage, V

Figure 12. Power Loss vs. Driver Supply Voltage Figure 13. Power Loss vs. Output Voltage

1.01 VIN= 12V, V

1.00

0.99

0.98

DRV

& V

CIN

= 5V, FSW= 300kHz, V

OUT

=1V, V

OUT

DRV

CIN

= 30A

& V

OUT

=5V, V

(V)

CIN

= 1V, I

OUT

DRV

= 30A

=5V, L

=250nH, TA=25°C, and natural convection cooling,

OUT

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

Normalized Module Power Loss

1.0

0.9

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

VIN= 12V, V

DRV

& V

Module Output Voltage, V

= 5V, FSW= 300kHz, I

CIN

OUT

(V)

45

(mA)

& I

CIN

DRV

40

35

30

VIN= 12V, V

DRV

& V

CIN

= 5V, V

OUT

= 1V, I

OUT

= 0A

25

20

OUT

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

= 30A

0.97

Normalized Module Power Loss

0.96

200 250 300 350 400 450 500

Output Inductor, L

OUT

(nH)

15

10

Driver Supply Current, I

5

100 200 300 400 500 600 700 800 900 1000 1100

Module Switching Frequency, F

(kHz)

SW

Figure 14. Power Loss vs. Output Inductor Figure 15. Driver Supply Current vs. Switching

Frequency

14

VIN= 12V, V

= 1V, FSW= 300kHz, I

OUT

= 0A

13

(mA)

CIN

12

& I

DRV

11

10

9

Driver Supply Current, I

8

4.0 4.5 5.0 5.5 6.0

Driver Supply Voltage, V

DRV

& V

CIN

(V)

Figure 16. Driver Supply Current vs. Driver Supply

1.06 VIN= 12V, V

1.04

DRV

& V

CIN

= 5V, V

OUT

= 1V

1.02

1.00

FSW= 1000kHz

0.98

0.96

0.94

0.92

Normalized Driver Supply Current

0.90

0 5 10 15 20 25 30 35 40 45

FSW= 300kHz

Module Output Current, I

OUT

(A)

Figure 17. Driver Supply Current vs. Output Current

Voltage

Typical Performance Characteristics

Test Conditions: V

3.6

3.5

(V)

3.4

CIN

3.3

3.2

3.1

3.0

Driver Supply Voltage, V

2.9

2.8

-55 0 25 55 100 125 150

Figure 18. UVLO Threshold vs. Temperature Figure 19. PWM Threshold vs. Driver Supply Voltage

4.5 V

CIN

4.0

(V)

3.5

PWM

3.0

2.5

2.0

1.5

PWM Threshold V ol tage, V

1.0

0.5

-55 0 25 55 100 125 150

CIN

=5V, V

=5V, TA=25°C, and natural convection cooling, unless otherwise specified.

DRV

Driver IC Junction Temperature, TJ(oC)

= 5V

Driver IC Junction Temperature, TJ(oC)

UVLO

V

IH_PWM

V

TRI_HI

V

HIZ_PWM

V

UP

TRI_LO

IL_PWM

4.5 TA= 25°C

V

IH_PWM

4.0

(V)

3.5

PWM

3.0

2.5

2.0

1.5

DN

PWM Threshold Voltage, V

1.0

0.5

4.50 4.75 5.00 5.25 5.50

Driver Supply Voltage, V

CIN

(V)

2.0

TA= 25°C

(V)

1.8

ZCD_EN#

V

IH_ZCD_EN#

1.6

1.4 V

1.2

ZCD_EN# Threshold Voltage, V

1.0

4.50 4.75 5.00 5.25 5.50

Driver Supply Voltage, V

CIN

(V)

V

TRI_HI

V

HIZ_PWM

V

TRI_LO

V

IL_PWM

IL_ZCD_EN#

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 20. PWM Threshold vs. Temperature Figure 21. ZCD_EN# Threshold vs. Driver Supply

Voltage

1.8 V

= 5V

(V)

CIN

1.7

ZCD_EN#

1.6

1.5

1.4

1.3

ZCD_EN# Threshold Voltage, V

1.2

-55 0 25 55 100 125 150

Driver IC Junction Temperature, TJ(oC)

V

IH_ZCD_EN#

V

IL_ZCD_EN#

(uA)

PLU

ZCD_EN# Pull-Up Cu rren t, I

-2.0 V

= 5V

CIN

-3.0

-4.0

-5.0

-6.0

-7.0

-8.0

-55 0 25 55 100 125 150

Driver IC Junction Temperature, TJ(oC)

Figure 22. ZCD_EN# Threshold vs. Temperature Figure 23. ZCD_EN# Pull-Up Current vs.

Temperature

Typical Performance Characteristics

Test Conditions: V

2.0 TA= 25°C

(V)

1.8

DISB#

1.6

1.4

1.2

DISB# Threshold Voltage, V

1.0

4.50 4.75 5.00 5.25 5.50

Figure 24. DISB# Threshold vs. Driver Supply

14

V

= 5V

CIN

13

(uA)

PLD

12

11

10

9

8

DISB# Pull- Down Curre nt, I

7

-55 0 25 55 100 125 150

=5V, V

CIN

Driver Supply Voltage, V

=5V, TA=25°C, and natural convection cooling, unless otherwise specified.

DRV

(V)

CIN

Voltage

Driver IC Junction Temperature, TJ(oC)

V

IH_DISB#

V

IL_DISB#

1.8 V

= 5V

CIN

1.7

(V)

DISB#

1.6

1.5

1.4

1.3

DISB# Threshold Voltage, V

1.2

-55 0 25 55 100 125 150

Driver IC Junction Temperature, TJ(oC)

V

IH_DISB#

V

IL_DISB#

Figure 25. DISB# Threshold vs. Temperature

700

IF= 1mA

650

(mV)

F

600

550

500

450

400

350

Boot Diode Forward Voltage, V

300

-55 0 25 55 100 125 150

Driver IC Junction Temperature, TJ(oC)

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 26. DISB# Pull-Down Current vs.

Temperature

Figure 27. Boot Diode Forward Voltage vs.

Temperature

A

p

Functional Description

The FDMF6708N is a driver-plus-FET module optimized for the synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1MHz.

VCIN and Disable (DISB#)

The VCIN pin is monitored by an Under-Voltage Lockout (UVLO) circuit. When V is enabled. When V disabled (GH, GL=0). The driver can also be disabled by pulling the DISB# pin LOW (DISB# < V holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the DISB# pin voltage HIGH (DISB# > V

Table 1. UVLO and Disable Logic

UVLO DISB# Driver State

0 X Disabled (GH, GL=0)

1 0 Disabled (GH, GL=0)

1 1 Enabled (see Table 2)

1 Open Disabled (GH, GL=0)

Note:

3. DISB# internal pull-down current source is 10µA.

Thermal Warning Flag (THWN#)

The FDMF6708N provides a thermal warning flag (THWN#) to warn of over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN# output returns to a highimpedance state once the temperature falls to the reset temperature (135°C). For use, the THWN# output requires a pull-up resistor, which can be connected to VCIN. THWN# does NOT disable the DrMOS module.

HIGH

THWN# Logic State

Normal Operation

LOW

Figure 28. THWN Operation

rises above ~3.3V, the driver

CIN

falls below ~2.95V, the driver is

CIN

), which

IL_DISB

).

IH_DISB

135°C Reset Temperature

150°C

ctivation

erature

Tem

Thermal Warning

T

J_driver IC

Three-State PWM Input

The FDMF6708N incorporates a three-state 5V PWM input gate drive design. The three-state gate drive has both logic HIGH level and LOW level, along with a three-state shutdown window. When the PWM input signal enters and remains within the three-state window for a defined hold-off time (t

D_HOLD-OFF

), both GL and GH are pulled LOW. This enables the gate drive to shut down both high-side and low-side MOSFETs to support features such as phase shedding, which is common on multi-phase voltage regulators.

Exiting Three-State Condition

When exiting a valid three-state condition, the FDMF6708N follows the PWM input command. If the PWM input goes from three-state to LOW, the low-side MOSFET is turned on. If the PWM input goes from three-state to HIGH, the high-side MOSFET is turned on. This is illustrated in Figure 29. The FDMF6708N design allows for short propagation delays when exiting

the three-state window (see Electrical Characteristics).

Low-Side Driver

The low-side driver (GL) is designed to drive a groundreferenced, low-R

, N-channel MOSFET. The bias

DS(ON)

for GL is internally connected between the VDRV and CGND pins. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB#=0V), GL is held LOW.

High-Side Driver

The high-side driver (GH) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor (C at PGND, allowing C internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from C and delivered to the gate of Q1. As Q1 turns on, V rises to V

, forcing the BOOT pin to VIN + V

IN

provides sufficient V the switching cycle, Q1 is turned off by pulling GH to V

. C

SWH

is then recharged to V

BOOT

PGND. GH output is in-phase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the three-state window for longer than the three-state hold-off time, t

). During startup, V

BOOT

to charge to V

BOOT

enhancement for Q1. To complete

GS

when V

DRV

D_HOLD-OFF

is held

SWH

through the

BOOT

SWH

BOOT

SWH

, which

falls to

.

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

V

_

V

Adaptive Gate Drive Circuit

The driver IC advanced design ensures minimum MOSFET dead-time, while eliminating potential shootthrough (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. Figure 29 provides the relevant timing waveforms. To prevent overlap during the LOW-to-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes

V

PWM

GH

to

VSWH

IH_PWM

CCM

V

IL PWM

less than

t

HOLD-OFF

D_HOLD-OFF

t

D

1.7

DCM

V

IH_PWM

t

R_GH

HIGH, Q2 begins to turn off after a propagation delay (t

PD_PHGLL

Q1 begins to turn on after adaptive delay t

). Once the GL pin is discharged below 1.7V,

D_DEADON

.

To preclude overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the GH-to-PHASE pin pair. When the PWM signal goes LOW, Q1 begins to turn off after a propagation delay (t

PD_PLGHL

). Once the voltage across GH-to-PHASE falls below 1.7V, Q2 begins to turn on after adaptive delay t

V

TRI_HI

t

F_GH

IH_PWM

DCM

D_DEADOFF

.

V

IH_PWM

V

TRI_HI

V

TRI_LO

V

IL_PWM

90%

10%

V

IN

V

OUT

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

GL

Notes: t

= propagation delay from external sign al (PWM, ZCD_EN#, etc.) to IC generated sign al. Example (t

PD_xxx

= delay from IC generated signal to IC generated signal. Example (t

t

D_xxx

PWM Exiting 3-state t

= PWM rise to LS VGS fall, V

PD_PHGLL

t

= PWM fall to HS VGS fall, V

PD_PLGHL

t

PD_PHGHH

ZCD_EN# Dead Times

= ZCD_EN# fall to LS VGS fall, V

t

PD_ZLGLL

t

PD_ZHGLH

90%

1.7

t

D_DEADON

t

PD

PLGHL

t

D

IH_PWM

IL_PWM

t

PD_PHGLL

= PWM rise to HS VGS rise, V

= ZCD_EN# rise to LS VGS rise, V

10%

Enter

3 -

t

F_GL

State

t

PD_TSGHH

Exit

3-State

– LS Vgs (GL) LOW to HS Vgs (GH) HIGH)

D_DEADON

t

R

GL

DEADOFF

to 90% LS VGS t

to 90% HS VGS t

to 10% HS VGS (ZCD_EN# held LOW)

IH_PWM

to 90% LS VGS t

IL_ZCD_EN

to 10% LS VGS t

IH_ZCD_EN

t

D_HOLD-OFF

PD_TSGHH

PD_TSGLH

D_DEADON

D_DEADOFF

Figure 29. PWM and 3-StateTiming Diagram

t

PD_TSGHH

Enter

3

-State

PD_PHGLL

= PWM 3-state to HIGH to HS VGS rise, V

= PWM 3-state to LOW to LS VGS rise, V

= LS VGS fall to HS VGS rise, LS-comp trip value (~1.7V GL) to 10% HS VGS

= VSWH fall to LS VGS rise, SW-comp trip value (~1.7V VSWH) to 10% LS VGS

Exit

3- State

– PWM going HIGH to LS Vgs (GL) going LOW)

less than t

D_HOLD-OFF

IH_PWM

IL_PWM

t

D_HOLD-OFF

Enter

3 -State

to 10% HS VGS

to 10% LS VGS

t

PD_TSGLH

Exit

3-State

90%

1

0%

V

Zero Cross Detection Mode (ZCD_EN#)

The Zero Current Detection Mode allows for higher converter efficiency when operating in light-load conditions. When ZCD_EN# is pulled LOW; the low-side MOSFET gate signal pulls LOW when internal circuitry detects positive LS MOSFET drain current, preventing discharge of the output capacitors as the filter inductor current attempts reverse current flow – known as “Diode Emulation” Mode.

When the ZCD_EN# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode. This mode allows for gating of the low-side MOSFET.

When the ZCD_EN# pin is pulled LOW, the low-side MOSFET is gated off automatically during positive LS MOSFET drain current. If the ZCD_EN# pin is pulled LOW by the PWM controller to support light-load PowerSaving Mode, FDMF6708N can actively turn off the lowside MOSFET when it detects the zero crossing of the inductor current. The low-side MOSFET turns on when inductor current is positive (LS MOSFET drain current is negative) and turns off when inductor current is negative (LS MOSFET drain current is positive). Zero-crossing detection of the inductor current and low-side MOSFET on and off are automatically performed on a cycle-by-

cycle basis. Normally this pin is active LOW. See Figure

30 for timing delays.

Table 2. ZCD_EN# Logic

DISB# PWM ZCD_EN# GH GL

0 X X 0 0

1 3-State X 0 0

1 0 0 0 0 (IL<0),1 (IL > 0)

1 1 0 1 0

1 0 1 0 1

1 1 1 1 0

Note:

4. GL = 0, when IL < 0 (Inductor current is negative and flowing in to the DrMOS VSWH node). GL = 1 when IL > 0 (Inductor current is positive and flowing out of the DrMOS VSWH node).

ZCD_EN#

IL_ZCD_EN

V

IH_ZCD_EN

IL_ZCD_EN

V

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

(4)

IH_PWM

90%

V

DCM

low

GS

t

PD_PHGLL

1 0%

V

OUT

PWM

GH to

SWH

VSWH

GL

V

IH_PWM

t

PD_PHGLL

t

D_DEADON

90%

1.7V

t

PD_PLGHL

t

V

IL_PWM

90%

1.7V

D_DEADOFF

10%

> 0

I

L

IL< 0 detected and GL transitions

low.

DCM (IL= 0)

t

PD_ZHGLH

Delay from ZCD_EN#

going high to LS V

10%

t

PD_ZLGLL

Delay from ZCD_EN#

going low to LS V

high

GS

Figure 30. ZCD_EN# Timing Diagram

A

V

Application Information

Supply Capacitor Selection

For the supply inputs (V capacitor is recommended to reduce noise and to supply the peak current. Use at least a 1µF X7R or X5R capacitor. Keep this capacitor close to the VCIN pin and connect it to the GND plane with vias.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor (C

), as shown in Figure 32. A bootstrap capacitance

BOOT

of 100nF X7R or X5R capacitor is usually adequate. A series bootstrap resistor may be needed for specific applications to improve switching noise immunity. The boot resistor may be required when operating above

and is effective at controlling the high-side

15V

IN

MOSFET turn-on slew rate and V values from 0.5 to 3.0Ω are typically effective in reducing VSWH overshoot.

V

5V

), a local ceramic bypass

CIN

overshoot. R

SHW

I

5V

C

VDRV

R

CIN

BOOT

C

VCIN Filter

The VDRV pin provides power to the gate drive of the high-side and low-side power MOSFET. In most cases, it can be connected directly to VCIN, the pin that provides power to the logic section of the driver. For additional noise immunity, an RC filter can be inserted between the VDRV and VCIN pins. Recommended values would be 10Ω and 1µF.

Power Loss and Efficiency

Measurement and Calculation

Refer to Figure 32 for power loss testing method.

Power loss calculations are:

P

=(VIN x IIN) + (V5V x I5V) (W) (1)

IN

P

SW=VSW

P

OUT=VOUT

P

LOSS_MODULE=PIN

P

LOSS_BOARD=PIN

EFF

CIN

x I

(W) (2)

OUT

x I

(W) (3)

OUT

- PSW (W) (4)

- P

(W) (5)

OUT

=100 x PSW/PIN (%) (6)

MODULE

BOARD

C

VIN

=100 x P

I

IN

V

(%) (7)

OUT/PIN

IN

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

DISB#

PWM

Input

OFF

ON

Open -

Drain

Output

DISB#

PWM Input

OFF

Open

Drain

Output

VDRV

DISB#

PWM

ZCD_END#

THWN#

Figure 31. Block Diagram With V

V

5V

ON

-

I

5V

C

VDRV

DISB#

PWM

ZCD_EN#

THWN#

VCIN

FDMF6708N

FDM 67 5

CGND

VDRV

FDMF6708N

CGND

PGND

VCIN

FDM 5

PGND

VIN

R

BOOT

VSWH

PHASE

VIN

BOOT

VSWH

PHASE

R

C

BOOT

VIN

V V

I

C

IN

C

BOOT

SW

BOOT

SW

Filter

CIN

V

I

OUT

I

OUT

V

OUT

L

OUT

C

OUT

IN

L

OUT

C

OUT

Figure 32. Power Loss Measurement

PCB Layout Guidelines

Figure 33 and Figure 34 provide an example of a proper layout for the FDMF6708N and critical components. All of the high-current paths, such as VIN, VSWH, VOUT, and GND copper, should be short and wide for low inductance and resistance. This aids in achieving a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance.

Recommendations for PCB Designers

1. Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the high-current power loop inductance and the input current ripple induced by the power MOSFET switching operation.

2. The V

addition to being the high-frequency current path from the DrMOS package to the output inductor, it serves as a heat sink for the low-side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low-impedance path for the high-frequency, high-current flow between the DrMOS and inductor. The short and wide trace minimizes electrical losses as well as the DrMOS temperature rise. Note that the V voltage and high-frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace acts as a heat sink for the lower MOSFET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission.

3. An output inductor should be located close to the

FDMF6708N to minimize the power loss due to the V

SWH

inductor dissipation does not heat the DrMOS.

4. PowerTrench

stage and are effective at minimizing ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The selected resistor and capacitor need to be the proper size for power dissipation.

5. VCIN, VDRV, and BOOT capacitors should be

placed as close as possible to the VCIN-to-CGND, VDRV-to-CGND, and BOOT-to-PHASE pin pairs to ensure clean and stable power. Routing width and length should be considered as well.

6. Include a trace from the PHASE pin to the VSWH pin

to improve noise margin. Keep this trace as short as possible.

7. The layout should include the option to insert a

small-value series boot resistor between the boot capacitor and BOOT pin. The boot-loop size, including R possible. The boot resistor may be required when operating above 15VIN and is effective at controlling the high-side MOSFET turn-on slew rate and V overshoot. R margin in synchronous buck designs that may have

copper trace serves two purposes. In

SWH

node is a high-

SWH

copper trace. Care should also be taken so the

®

MOSFETs are used in the output

and C

BOOT

can improve noise operating

BOOT

, should be as small as

BOOT

SHW

noise issues due to ground bounce or high positive and negative V

ringing. Inserting a boot

SWH

resistance lowers the DrMOS efficiency. Efficiency versus noise trade-offs must be considered. R

BOOT

values from 0.5Ω to 3.0Ω are typically effective in reducing V

overshoot.

SWH

8. The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative V

SWH

ringing.

9. GND pad and PGND pins should be connected to the GND copper plane with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of the gate driver and MOSFETs.

10. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to the PGND capacitor. This may lead to excess current flow through the BOOT diode.

11. The ZCD_EN# and DISB# pins have weak internal pull-up and pull-down current sources, respectively. These pins should not have any noise filter capacitors. Do not to float these pins unless absolutely necessary.

12. Use multiple vias on the VIN and VOUT copper

areas to interconnect top, inner, and bottom layers to distribute current flow and heat conduction. Do not put many vias on the VSWH copper to avoid extra parasitic inductance and noise on the switching waveform. As long as efficiency and thermal performance are acceptable, place only one VSWH copper on the top layer and use no vias on the VSWH copper to minimize switch node parasitic noise. Vias should be relatively large and of reasonably low inductance. Critical highfrequency components, such as R

BOOT

, C

BOOT

, RC snubber, and bypass capacitors; should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they can be connected from the backside through a network of low-inductance vias.

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 33. PCB Layout Example (Top View)

Figure 34. PCB Layout Example (Bottom View)

Physical Dimensions

B

0.10

2X

0.50

0.40

2.00±0.10

0.10 C

0.08 C

0.40

(0.70)

20

11

C

21

1.10

0.90

6.00

TOP VIEW

FRONT VIEW

4.40±0.10

(2.20)

10

(0.20)

BOTTOM VIEW

0.30

0.20

DETAIL 'A'

SCALE: 2:1

(0.20)

0.05

0.00

0.30

0.20

30

31

2.40±0.10

1.50±0.10

40

1

2.00±0.10

0.50

Figure 35. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

.

PIN#1 INDICATOR

A

6.00

0.10

2X

SEE DETAIL 'A'

0.10 CAB

0.05

(40X)

C

SEATING

PLANE

2.50

0.25

1.60

C

0.60

C

0.20

0.50

0.30

NOTES: UNLESS OTHERWISE SPECIFIED

A) DOES NOT FULLY CONFORM TO JEDEC

B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV2

5.80

4.50

31

40

1

0.50 TYP

2.10

LAND PATTERN

RECOMMENDATION

PIN #1 INDICATOR

(40X)

REGISTRATION MO-220, DATED MAY/2005.

2130

20

11

10

0.35

0.15

2.10

0.40

0.65

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Datasheet FDMF6708N Datasheet (Fairchild)

Specifications and Main Features

Frequently Asked Questions

User Manual