Datasheet FDH038AN08A1 Datasheet (Fairchild)

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FDH038AN08A1

N-Channel PowerTrench® MOSFET
75V, 80A, 3.8mΩ

FDH038AN08A1

February 2003

Features

•r

•Q

• Internal Gate Resistor, Rg = 20Ω (Typ.)

• Low Miller Charge

•Low Q

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

Formerly developmental type 82690

MOSFET Maximum Ra tings T

= 3.5mΩ (Typ.), V

DS(ON)

(tot) = 125nC (Typ.), V

g

Body Diode

RR

= 10V, ID = 80A

GS

= 10V

GS

SOURCE

DRAIN

TO-247

= 25°C unless otherwise noted

C

GATE

Applications

• 42V Automotiv e Load Control

• Starter / Alternator Systems

• Electronic Power Steering Systems

• Elec tr on ic Valve Train Sys tems

• DC-DC converter s and Off-line UPS

• Distributed P ower Arc hitectures and VRMs

• Primary Switch for 24V and 48V systems

D

G

S

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Sou r c e Voltage 75 V
Gate to Source Voltage ±20 V
Drain Curr e nt

I

D

Continuous (T
Continuous (T

< 158oC, VGS = 10V)

C

= 25oC, VGS = 10V, with R

A

= 30oC/W) 22 A

θJA

80 A

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse A valanch e Energy (Note 1) 1.17 J
Power dissipation 450 W

o

Derate above 25

C3.0W/

Operating and Storage Temperature -55 to 175

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

This product ha s been des igned to me et the e xtr eme test c ondit ions and envir onment deman ded by the automot ive indus t ry. For a

All Fairchild Semiconductor prod ucts are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

©2003 Fairchild Semiconductor Corporation

Thermal Resistance Junction t o Case TO-247 0.33
Thermal Resistance Junction to Ambient T O-247 30

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

certification.

FDH038AN08A1 Rev A

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDH038 AN08A1 FDH038 AN08A1 TO-247 Tube N/A 30 unit s

FDH038AN08A1

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain to Sou r c e Br ea k down Voltag e ID = 250µA, VGS = 0V 75 - - V

V

= 60V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- -250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

= 80A, VGS = 10V - 0.0035 0.0038

I

D

I

= 40A, VGS = 6V - 0.0047 0.0071

Drain to S ou r c e On Re si st ance

D

I

= 80A, VGS = 10V,

D

T

= 175oC

J

- 0.0074 0.008

Dynamic Characteristics

C
C
C
Q
Q
Q
Q
Q

ISS
OSS
RSS

g(TOT)
g(TH)
gs
gs2
gd

Input Capacitance
Output Capacitance - 1320 - pF
Reverse Transfer Capacitance - 340 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total Gate Charge at 10V VGS = 0V to 10V
Threshold Gate Charge VGS = 0V to 2V - 17 22 nC
Gate to Source Gate Charg e - 57 - nC
Gate Charge Threshold to Plateau - 42 - nC

V

DD

I

= 80A

D

I

= 1.0m A

g

= 40V

Gate to Drain “Miller” Charge - 30 - nC

- 8665 - pF

125 160 nC

µA

Ω

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 88 - ns
Rise Time - 141 - ns
Turn-Off D elay Time - 23 2 - ns
Fall Time - 126 - ns
Turn-Off Time - - 530 ns

(VGS = 10V)

V

= 40V, ID = 80A

DD

V

= 10V, RGS = 2.4Ω

GS

--345ns

Drain-Source Diode Characteristics

I

= 80A - - 1.2 5 V

V

SD

t

rr

Q

RR

Notes:
1: Starting TJ = 25°C, L = 0.65mH, IAS = 60A.

©2003 Fairchild Semiconductor Corporation FDH038AN08A1 Rev. A

Source to Drain Diode Voltage
Reverse Recovery Time ISD = 75A, dISD/dt = 100A/µs- -50ns

Reverse Recovered Charge ISD = 75A, dISD/dt = 100A/µs- -65nC

SD

= 40A - - 1.0 V

I

SD

FDH038AN08A1

Typical Characteristics T

= 25°C unless otherwise noted

C

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

1

0.5

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

-5

SINGLE PULSE

-4

10

0.01
10

280

240

200

160

120

80

, DRAIN CURRENT (A)

D

I

40

V

GS

150

0

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

= 10V

TC, CASE TEMPERATURE (oC)

Case Temperature

NOTES:
DUTY FACTOR: D = t1/t

PEAK TJ = PDM x Z

-1

10

CURRENT LIMITED
BY PACKAGE

R

θJA

P

DM

2

x R

θJC

θJC

0

10

=30oC/W

t

1

t

2

+ T

C

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

3000

TRANSCONDUCTANCE
MAY LIMIT CURRENT

1000

IN THIS REGION

VGS = 10V

, PEAK CURRENT (A)

DM

I

100

50

-5

10

-4

10

-3

10

t, PULSE WIDTH (s)

-2

10

-1

10

TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:

175 - T

I = I

25

0

10

C

150

1

10

Figure 4. Peak Current Capability

©2003 Fairchild Semiconductor Corporation FDH038AN08A1 Rev. A

FDH038AN08A1

Typical Characteristics T

2000

1000

100

10

OPERATION IN THIS

AREA MAY BE

LIMITED BY r

, DRAIN CURRENT (A)

D

I

1

SINGLE PULSE
TJ = MAX RATED
TC = 25oC

0.1

0.1 1 10 100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

= 25°C unless otherwise noted

C

10µs

100µs

1ms

10ms

DC

Figure 5. Forward Bias Safe Operating Area

160

PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX

V

= 15V

DD

120

TJ = 175oC

80

, DRAIN CURRENT (A)

D

40

I

0

TJ = 25oC

3.0 3.5 4.0 4.5 5.0 5.5 6.0
VGS, GATE TO SOURCE VOLTAGE (V)

TJ = -55oC

500

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV

100

10

, AVALANCHE CURRENT (A)

AS

I

1

0.01 0.1 1 10 100
tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

STARTING TJ = 150oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

160

VGS = 10V

120

VGS = 6V

80

, DRAIN CURRENT (A)

D

40

I

0

0 0 .5 1.0 1.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 7V

VGS = 5V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TC = 25oC

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

6

5

4

3

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

DRAIN TO SOURCE ON RESISTANCE(mΩ)

2

0 20406080

ID, DRAIN CURRENT (A)

VGS = 6V

VGS = 10V

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

©2003 Fairchild Semiconductor Corporation FDH038AN08A1 Rev. A

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 80A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDH038AN08A1

Typical Characteristics T

1.4

1.2

1.0

0.8

0.6

NORMALIZED GATE

THRESHOLD VOLTAGE

0.4

0.2

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

C

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

20000

10000

C

≅ C

+ C

OSS

DS

GD

C

ISS

= CGS + C

GD

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 40V

8

6

1000

C

= C

RSS

GD

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

100

0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Sour ce

Voltage

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

75

0 255075100125

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 80A
ID = 40A

Figure 14. Gat e Charge Waveforms for Constant

Gate Currents

©2003 Fairchild Semiconductor Corporation FDH038AN08A1 Rev. A

Test Circuits and Waveforms

V

DS

L

VARY tP TO OBTAIN
REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

I

AS

DUT

t

0V

P

I

AS

0.01Ω

0

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

DS

V

DD

L

V

I

g(REF)

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

= 2V

Q

gs2

Q

g(TH)

Q

gs

Q

0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

BV

DSS

t

P

t

AV

Q

g(TOT)

V

DS

gd

V

V

GS

FDH038AN08A1

DS

V

DD

V

= 10V

GS

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

10%

90%

PULSE WIDTH

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2003 Fairchild Semiconductor Corporation FDH038AN08A1 Rev. A

PSPICE Electrical Model

.SUBCKT FDH038AN08A1 2 1 3 ; rev January 2003
CA 12 8 1.0e -9
Cb 15 14 3.1e-9
Cin 6 8 8.22e-9

Dbod y 7 5 DbodyMOD
Dbreak 5 11 Db reakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 84.9
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgat e 1 9 4.81e-9

Ldrain 2 5 1.0e -9
Lsource 3 7 4.63e-9

RLgate 1 9 48.1
RLdr ai n 2 5 10
RLsource 3 7 46.3

Mmed 16 6 8 8 M m edMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.0e-4
Rgate 9 20 20
RSLC1 5 51 RSL CM OD 1.0e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2.6e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BM OD
S2a 6 15 14 13 S2AM OD
S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP
+

18
22

20

S1A

12

13814

S1B

EGS EDS

FDH038AN08A1

17
18

-

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

6

-

S2A

13

S2B

13

+

+

6
8

-

-

5

RSLC1

51

+

5

ESLC

51

­50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5
8

-

MMED

8

DBREAK

11

+

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

ESLC 51 50 VALUE = {(V(5,51)/ ABS(V(5,51)))*(PWR(V (5,51)/(1e-6*300),10) )}
.MODEL DbodyMOD D (IS=2.4 E-11 N=1.02 RS= 1. 65e-3 TRS1=3.2e-3 TRS2=2.0e-7

+ CJO=6.0e-9 M= 5.6e-1 TT=2.3 8e-8 XTI=3.9)
.MODEL DbreakMOD D (RS= 1. 5e-1 TRS1=1.0e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.5e-9 IS=1.0e-30 N=10 M=0.47)

.MODEL MmedM OD NMOS (VTO= 3.2 KP =1.5 IS=1.0e-30 N=10 TOX=1 L=1u W=1u RG=20)
.MODEL Mstro M OD NMOS (VTO=3.95 KP=235 IS=1.0e-30 N=10 TOX=1 L=1u W=1u)
.MODEL Mwe akMOD NMOS (VTO=2.73 KP=0.02 IS=1e-30 N=10 TO X = 1 L=1u W=1u RG=200 RS=.01)

.MODEL Rb reakMOD RES (T C1=1.05e-3 TC 2=-9.0e-7)
.MODEL Rd rai nMOD RES (TC 1=1.8e-2 TC2=2.2e-4)
.MODEL RSLCMOD RES (TC1=2.0e-3 TC2=1.0e-5)
.MODEL RsourceMOD RES (TC 1=5.0e-3 TC2=1 .0e-6)
.MODEL RvthresMOD RES (T C1=-4.2e-3 TC 2=-1.8e-5)
.MODEL RvtempMOD RES (TC1=-4.5e-3 TC 2=2.0e-6)

.MODEL S1AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 4 VOFF =-1 .5 )
.MODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1.5 VO FF=- 4)
.MODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 0.5 VO FF=0.5)
.MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= 0 .5 VOFF= -0.5)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. FrankWheatley.

©2003 Fairchild Semiconductor Corporation FDH038AN08A1 Rev. A

SABER Electrical Model

REV January 2003
template FDH 038AN08A1 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.4e-11,nl=1.02,rs=1.65e-3,trs1=3.2e-3,trs2=2.0e-7,cjo=6.0e-9,m=5.6e-1,tt=2.38e-8,xti=3.9)
dp..model dbreakmod = (rs=1.5e-1,trs1=1.0 e-3,trs2=-8.9e-6)
dp..m odel dpl capmod = (cjo=1.5 e-9,isl= 10e-3 0,nl=10 , m = 0.47)
m..model mmedmod = (type=_n,vto=3.2,kp=1.5,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.95,kp=235,is=1.0e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.73,kp=0.02,is=1.0e-30, tox=1,rs=0.1)
sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0.1, von=-4,voff=-1.5)
sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0.1, von=-1.5,voff= -4)
sw_vcsp.. mo del s2amod = (ron=1e- 5,roff=0.1,vo n=-0.5,voff=0. 5)
sw_vcsp.. mo del s2bmod = (ron=1e- 5,roff=0.1,vo n=0.5,voff=-0. 5)
c.ca n12 n8 = 1.0e -9
c.cb n15 n14 = 3.1e-9
c.cin n6 n8 = 8.22 e-9

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplca pm od

spe.ebreak n11 n7 n17 n18 = 84.9
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1

GATE

1

LGATE

9

RLGATE

RGATE

ESG

EVTEMP
+

18
22

20

l.lgate n1 n9 = 4.81e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 4.63e-9

res.rlgate n1 n9 = 48.1
res.rldrai n n2 n5 = 10
res.rlsource n3 n7 = 46.3

m.mmed n16 n6 n8 n8 = m odel=mmedm od, l= 1u, w=1u
m.mstrong n16 n6 n8 n8 = model=ms tr ongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakm od, l=1u, w=1u

12

CA

S1A

S1B

EGS EDS

res.rbreak n17 n18 = 1, tc1=1.05e -3, tc2=-9.0e-7
res.rdrain n50 n16 = 2.0e-4, tc1=1.8e-2,tc2=2.2e-4
res.rgate n9 n20 = 20
res.rslc1 n5 n51 = 1e-6, tc1=2.0e-3,tc2=1.0e-5
res.rslc2 n5 n50 = 1.0e3
res.rsour ce n8 n7 = 2.6e-3, tc1=5.0e-3,tc2=1.0e-6
res.rvthres n22 n8 = 1, tc1=-4.2e-3,tc2=-1.8e-5
res.rvtemp n18 n19 = 1, tc1=-4.5e-3,tc2=2.0e-6
sw_vcsp.s1 a n6 n12 n13 n8 = model= s1amod
sw_vcsp.s1 b n13 n12 n13 n8 = model =s1bmod
sw_vcsp.s2 a n6 n15 n14 n13 = model =s2amod
sw_vcsp.s2 b n13 n15 n14 n13 = model =s2bmod

10

-

6
8

+

-

13814

13

+

+

-

-

DPLCAP

RSLC2

EVTHRES

6

S2A

13

S2B

6
8

5

RSLC1

51

ISCL

8

MMED

8

DBREAK

11

MWEAK

EBREAK

+

RSOURCE

RBREAK

17 18

IT

RVTHRES

50

RDRAIN

16

+

21

-

19

8

MSTRO

CIN

15

CB

14

+

5
8

-

17
18

­7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDH038AN08A1

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5, n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/300))** 10))
}
}

©2003 Fairchild Semiconductor Corporation FDH038AN08A1 Rev. A

FDH038AN08A1

SPICE Thermal Model

REV 23 January 2003
FDH038AN08A1T
CTHERM1 TH 6 5.5e-3

CTHERM2 6 5 6. 0e-3
CTHERM3 5 4 7. 4e-3
CTHERM4 4 3 7. 65e-3
CTHERM5 3 2 5. 85e-2
CTHERM6 2 TL 6.0e-1

RTHERM1 TH 6 9.0e-3
RTHERM2 6 5 2. 08e-2
RTHERM3 5 4 2. 28e-2
RTHERM4 4 3 7. 0e-2
RTHERM5 3 2 7. 5e-2
RTHERM6 2 TL 8.5e-2

SABER Thermal Model

SABER therm a l model FDH038A N08A1T
template thermal_model th tl
thermal_ c th , tl
{
ctherm.c th erm 1 th 6 =5.5e-3
ctherm.ctherm2 6 5 =6.0e-3
ctherm.ctherm3 5 4 =7.4e-3
ctherm.ctherm4 4 3 =7.65e-3
ctherm.ctherm5 3 2 =5.85e-2
ctherm.ctherm6 2 tl =6.0e-1

rtherm.rtherm1 th 6 =9.0e-3
rtherm.rt herm2 6 5 =2.08e-2
rtherm.rt herm3 5 4 =2.28e-2
rtherm.rt herm4 4 3 =7.0e-2
rtherm.rt herm5 3 2 =7.5e-2
rthe r m.rtherm6 2 tl =8.5 e-2
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

RTHERM6

2

CTHERM6

tl

CASE

©2003 Fairchild Semiconductor Corporation FDH038AN08A1 Rev. A

TRADEMARKS

The following are registe red and unr egistered trademarks Fairchild Semiconductor owns or is aut horized to use and is not
intended to be an exhaustive list of all such trademarks.

ACEx™
ActiveArray™
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
EcoSPARK™

2

E

CMOS™
EnSigna™
Across the board. Around the world.™
The Power Fr anchise™
Programma ble Active Droop™

FACT™
FACT Quiet Series™

®

FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™

2

I

C™

ImpliedDisconnect™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC

®

OPTOPLANAR™

PACMAN™
POP™
Power247™
PowerTrench

®

QFET™
QS™
QT Optoelectronics™
Quiet Ser ies™
RapidConfigure™
RapidConnect™
SILENT SWITCHER
SMART START™

SPM™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic
TruTranslation™
UHC™
UltraFET

®

VCX™

®

®

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems
which, (a) ar e int ende d fo r s urgic al i mpla nt into the bo dy,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

2. A c r it ic al c om ponent i s an y c om ponent o f a life s u pp or t
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Adva nce Information Formative or I n

Design

Preliminary First Production This datasheet co ntains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

supple m entary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

Semiconductor reserves the righ t to make chan ges at
any time without notice in order to improve design.

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. I2