Page 1
INTEGRATED CIRCUITS
FBL22040
3.3V BTL8-bit TTL to BTL transceiver
Product specification
IC23 Data Handbook
1998 Dec 07
Page 2
Philips Semiconductors Product specification
V
In ut voltage
V
I
mA
FBL220403.3V BTL 8-bit TTL to BTL transceiver
FEA TURES
•Resistor version of FB2040
•8-bit BTL transceivers
•Separate I/O on TTL A-port
•Inverting
•Drives heavily loaded backplanes with equivalent load
impedances down to 10Ω.
•High drive 100mA BTL open collector drivers on B-port
•Allows incident wave switching in heavily loaded backplane buses
•Reduced BTL voltage swing produces less noise and reduces
power consumption
•Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
•Compatible with IEEE Futurebus+ or proprietary BTL backplanes
QUICK REFERENCE DATA
SYMBOL PARAMETER TYPICAL UNIT
t
PLH
t
PHL
t
PLH
t
PHL
C
I
I
OB
OL
CC
Propagation delay
AIn to Bn
Propagation delay
Bn to AOn
Output capacitance (B0 – B7 only) 4 pF
Output current (B0 – B7 only) 100 mA
Supply current
•Controlled output ramp and multiple GND pins minimize ground
bounce
•Each BTL driver has a dedicated Bus GND for a signal return
•Glitch-free power up/power down operation
•Low I
current
CC
•Tight output skew
•Supports live insertion
•Pins for the optional JTAG boundary scan function are provided
•High density packaging in plastic Quad Flat Pack
•Same pin and function as FBL2040 except for a 30Ω series
termination resistor
•The A outputs include a series resistor of 30Ω making external
terminating resistors unnecessary
4.4
3.1
3.4
3.2
Standby 4
AIn to Bn
(outputs Low )
Bn to AOn
(outputs Low)
AIn to Bn
(outputs High)
Bn to AOn
(outputs High)
8
18
13
16
ns
ns
mA
ORDERING INFORMATION
PACKAGES
52-pin Plastic Quad Flat Pack (QFP) FBL22040BB SOT379-1
COMMERCIAL RANGE
VCC = 3V±10%; T
= –40°C to +85°C
amb
DRAWING
NUMBER
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.
SYMBOL
V
CC
IN
I
IN
V
OUT
OUT
T
amb
T
STG
1998 Dec 07 853-2137 20493
Supply voltage -0.5 to +4.6 V
p
Input current -18 to +5.0 mA
Voltage applied to output in High output state -0.5 to +7.0 V
Current applied to output in Low
output state
Operating free-air temperature range -40 to +85 °C
Storage temperature -65 to +150 °C
PARAMETER RATING UNIT
AI0 – AI7, OEB0, OEB1, OEA -0.5 to +7.0
B0 – B7 -0.5 to +3.5
A0 – A7 24, –24
B0 – B7 200
2
Page 3
Philips Semiconductors Product specification
FBL220403.3V BTL 8-bit TTL to BTL transceiver
PIN CONFIGURATION
CC
LOGIC V
AI0
AO1
AO0
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND
LOGIC GND
LOGIC GND
LOGIC GND
LOGIC GND
AI1
AI2
AO2
AO3
AI3
AI4
AO4
AO5
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
AI5
8-Bit Transceiver
52-lead PQFP
CC
AO6
BG V
LOGIC GND
DESCRIPTION
The FBL22040 is an 8-bit bidirectional BTL transceiver and is
intended to provide the electrical interface to a high performance
wired-OR bus. The FBL22040 is an inverting transceiver.
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V .
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.
The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEA goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEA goes Low, A-port drivers become High impedance
without any extra delay. During power on/of f cycles, the A-port
drivers are held in a High impedance state when V
The B-port has two output enables, OEB0 and OEB1. When OEB0
is High and OEB1
is Low the output is enabled. When OEB0 is Low
is below 1.3V.
CC
OEA
BIAS V
OEB0
FBL22040
AI6
AO7
BG GND
CC
TMS (option)
TCK (option)
OEB1
TDI (option)
TDO (option)
or if OEB1
BUS V
CC
BUS V
is High, the B-port is inactive and is at the level of the
AI7
B0/B0
BUS GND
39
38
37
36
35
34
33
32
31
30
29
28
27
B7
NC
BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND
B5
BUS GND
B6
BUS GND
SG00114
backplane signal.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while V
BIAS V pin should be tied to a V
is Low. If live insertion is not a requirement, the
CC
CC
pin.
The LOGIC GND and BUS GND pins are isolated in the package to
minimize noise coupling between the BTL and TTL sides. These
pins should be tied to a common ground external to the package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble-shoot.
The LOGIC V
and BUS VCC pins are also isolated internally to
CC
minimize noise and may be externally decoupled separately or
simply tied together.
JTAG boundary scan pins are provided with signals TMS, TCK, TDI
and TDO. TMS and TCK are no-connects (no bond wires) and TDI
and TDO are shorted together internally. Boundary scan
functionality is not implemented at this time.
1998 Dec 07
3
Page 4
Philips Semiconductors Product specification
MODE
AIn to Bn
Disable Bn out uts
Bn to AOn
FBL220403.3V BTL 8-bit TTL to BTL transceiver
PIN DESCRIPTION
SYMBOL PIN NUMBER TYPE NAME AND FUNCTION
AI0 – AI7 51, 2, 3, 8, 9, 14, 18, 24 Input Data inputs (TTL)
AO0 – AO7 50, 52, 4, 6, 10, 12, 16, 20 Output 3-state outputs (TTL)
B0 – B7
OEB0 46 Input Enables the B outputs when High
OEB1 45 Input Enables the B outputs when Low
OEA 47 Input Enables the A outputs when High
BUS GND 41, 39, 37, 35, 33, 31, 29, 27 GND Bus ground (0V)
LOGIC GND 1, 5, 7, 11, 13, 15 GND Logic ground (0V)
BUS V
CC
LOGIC V
CC
BG V
CC
BG GND 19 GND Band Gap threshold voltage reference ground
BIAS V 48 Power Live insertion pre-bias pin
TMS 42 Input Test Mode Select (optional, if not implemented then no-connect)
TCK 44 Input Test Clock (optional, if not implemented then no-connect)
TDI 22 Input Test Data In (optional, if not implemented then shorted to TDO)
TDO 21 Output Test Data Out (optional, if not implemented then shorted to TDI)
NC 25 NC No Connect
40, 38, 36, 34,
32, 30, 28, 26
23, 43 Power Positive supply voltage
49 Power Positive supply voltage
17 Power Band Gap threshold voltage reference
I/O Data inputs/Open Collector outputs. High current drive (BTL)
FUNCTION TABLE
INPUTS OUTPUTS
AIn Bn* OEB0 OEB1 OEA AOn Bn*
L — H L L Z H**
H — H L L Z L
L — H L H L H**
H — H L H H L
p
Disable AOn outputs — X X X L Z X
H** = Goes to level of pull-up voltage
B* = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
X X L X X X H**
X X X H X X H**
X L L X H H Input
X H X H H L Input
X L X H H H Input
X H L X H L Input
1998 Dec 07
4
Page 5
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
V
High-level in ut voltage
V
V
Low-level in ut voltage
V
I
Low-level out ut current
mA
SYMBOL
PARAMETER
UNIT
I
(
BIASV
)
IOLOFF
Power up current
A
FBL220403.3V BTL 8-bit TTL to BTL transceiver
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN NOM MAX
V
CC
IH
IL
I
IK
I
OH
OL
C
OB
T
amb
LIVE INSERTION SPECIFICA TIONS
V
BIASV
BIASV
V
Bn
I
LM
I
HM
IBnPEAK
t
GR
Supply voltage 3.0 3.3 3.6 V
p
p
Except B0–B7 2.0
B0 – B7 1.62 1.55
Except B0–B7 0.8
B0 – B7 1.47
Input clamp current -18 mA
High-level output current AO0 – AO7 -12 mA
p
AO0 – AO7 +12
B0 – B7 100
Output capacitance on B port 6 7 pF
Operating free-air temperature range –40 +85 °C
LIMITS
MIN TYP MAX
Bias pin voltage
Bias pin (I
DC current
BIASV
) input
Voltage dif ference between the Bias voltage
and VCC after the PCB is plugged in.
– – 0.5 V
VCC = 0 V, Bias V = 3.6V 1.2 mA
VCC = 3.3V, Bias V = 3.6V 10 µA
Bus voltage during prebias B0 – B8 = 0V, Bias V = 3.3V 1.62 2.1 V
Fall current during prebias B0 – B8 = 2V, Bias V = 1.3 to 2.5V 1 µA
Rise current during prebias B0 – B8 = 1V, Bias V = 3 to 3.6V -1 µA
Peak bus current during
insertion
p
VCC = 0 to 3.3V, B0 – B8 = 0 to 2.0V,
Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns
V
= 0 to 3.3V, OEB0 = 0.8V 100
CC
V
= 0 to 1.2V, OEB0 = 0 to 5V 100
CC
10 mA
µ
Input glitch rejection VCC = 3.3V 1.0 1.35 ns
1998 Dec 07
5
Page 6
Philips Semiconductors Product specification
FBL220403.3V BTL 8-bit TTL to BTL transceiver
LOGIC DIAGRAM FOR FBL2040
46
OEB0
45
OEB1
47
OEA
AI0
AO0
AI1
AO1
AI2
AO2
51
50
2
52
3
4
40
B0
38
B1
36
B2
TTL
Levels
AO3
AO4
AO5
AO6
AO7
TMS
TCK
TDI
TDO
AI3
AI4
AI5
AI6
AI7
8
6
9
10
14
12
18
16
24
20
42
44
(Future JTAG Boundary Scan option)
22
21
34
B3
BTL
Levels
32
B4
30
B5
28
B6
26
B7
NC = 25
LOGIC V
LOGIC GND = 1, 5, 7, 11, 13, 15
BUS V
BUS GND = 27, 29, 31, 33, 35, 37, 39, 41
BIAS V = 48
BG V
BG GND = 19
CC
CC
CC
=49
= 23, 43
=17
1998 Dec 07
SG00077
6
Page 7
Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITIONS
1
UNIT
I
Power-off output current
B0
B7
A
V
High level out ut
AO0
AO7
3
AO0
AO7
3
V
µ
I
g
µ
V
MAX, V
9V
100µA
mA
IILLow-level input current
B0
B7
V
MAX, V
75V
100µA
CCH
Su ly current (total)
B→A
CCH
Su ly current (total)
A→B
FBL220403.3V BTL 8-bit TTL to BTL transceiver
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
LIMITS
MIN TYP2MAX
I
OFF
V
V
I
OZH
I
OZL
I
CCZ
I
I
CCL
I
I
CCL
High level output current B0 – B7 VCC = MAX, VIL = MAX, VOH = 1.9V 100 µA
OH
VCC = 0V, VIL = MAX, VOH = 1.9V 100
VCC = 0V, VIL = MAX, VOH = 1.9V@85°C 300
V
VCC = MIN to MAX; IOH = -100µA
CC
–0.2
VCC = MIN; IOH = -4mA 2.4 V
OH
p
High-level output
voltage
–
–
VCC = MIN; IOH = -12mA 2.0 V
VCC = MIN; IOL = 4mA 0.4 V
VCC = MIN; IOL = 12mA 0.8 V
Low-level output voltage
OL
–
B0 – B7 VCC = MIN, IOL = 4mA 0.5
VCC = MIN, IOL = 100mA 0.75 1.0 1.20
Input clamp voltage VCC = MIN, II = I
IK
= –18mA –0.85 -1.2 V
IK
Control pins VCC = 3.6V; VI = VCC or 100mV ±1.0
I
Input leakage current
I
Control/
AI0 – AI7
AI0 – AI7 VCC = 3.6V; VI = V
VCC = 0V or 3.6V; VI = 5.5V 10
CC
Note 4 VCC = 3.6V; VI = 100mV –5
=
CC
I
High-level input current B0 – B7 VCC = MAX, VI = 3.5V , note 5 100
IH
= 1.
I
VCC = MAX, VI = 3.75V, Note 5 @ –40°C 100
p
–
CC
=
= 0.
I
Off-state output current AO0 – AO7 VCC = MAX, VO =3V 5 µA
Off-state output current AO0 – AO7 VCC = MAX, VO = 0.5V -5 µA
Supply current VCC = MAX, outputs disabled, VI = GND or 0.0 16 31
CCH
CCH
pp
pp
VCC = MAX, outputs High, VI = GND or 0.0 16 35
VCC = MAX, outputs Low, VI = GND or 0.0 18 39 mA
VCC = MAX, outputs High, VI = GND or 0.0 13 30
VCC = MAX, outputs Low, VI = GND or 0.0 8 16
µ
V
A
1
-
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V
3. Due to test equipment limitations, actual test conditions are V
4. Unused pins are at V
5. For B port input voltage between 3 and 5 volt; I
is Active). This is not a tested condition.
1998 Dec 07
= 3.3V, TA = 25°C.
CC
or GND.
CC
will be greater than 100mA but the part will continue to function normally (clamping circuit
IH
= 1.8V and VIL = 1.3V for the B side.
IH
7
Page 8
Philips Semiconductors Product specification
FBL220403.3V BTL 8-bit TTL to BTL transceiver
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
T
= –40 to +85°C,
amb
VCC = 3.3V±10%,
R
= 9Ω
L
1.0
1.0
1.0
1.9
1.0
1.1
3.5
3.5
6.3
5.6
6.1
6.9
6.0
5.8
0.5
0.5
UNIT
ns
ns
ns
ns
SYMBOL PARAMETER TEST CONDITION
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
TLH
t
THL
tSK(O)
tSK(P)
Propagation delay,
AIn to Bn
OEB0 to Bn
OEB1 to Bn
Transition time, Bn Port
(1.3V to 1.8V)
Output skew between receivers
in same package
Pulse skew
|t
– t
PLH
| MAX
PHL
T
= +25°C, VCC = 3.3V,
amb
R
= 9Ω
L
MIN TYP MAX MIN MAX
1.0
1.2
1.4
2.0
1.5
1.4
1.0
1.2
2.7
3.0
3.1
4.1
3.3
3.2
1.7
1.9
5.7
5.1
5.0
6.4
5.3
5.0
2.5
2.5
0.5 1.0 1.5 ns
0.3 1.0 1.5 ns
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
T
= +25°C, VCC = 3.3V,
amb
R
= 16.5Ω
SYMBOL PARAMETER TEST CONDITION
L
MIN TYP MAX MIN MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
TLH
t
THL
tSK(O)
tSK(P)
Propagation delay,
AIn to Bn
OEB0 to Bn
OEB1 to Bn
Transition time, Bn Port
(1.3V to 1.8V)
Output skew between receivers
in same package
Pulse skew
|t
– t
PLH
| MAX
PHL
1.2
1.2
1.8
1.8
1.6
1.3
1.0
1.2
2.8
2.8
3.6
3.8
3.4
3.0
1.7
1.9
4.4
4.6
5.6
5.9
6.2
4.8
2.5
2.5
0.5 1.0 1.5 ns
0.3 1.0 1.5 ns
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (B TO A)
T
= +25°C, VCC = 3.3V
SYMBOL PARAMETER TEST CONDITION
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
TLH
t
THL
tSK(O)
tSK(P)
Propagation delay,
Bn to AOn
OEA to AOn
OEA to AOn
Transition time, AOn Port
(10% to 90% or 90% to 10%)
Output skew between receivers
in same package
Pulse skew
|t
– t
PLH
| MAX
PHL
amb
MIN TYP MAX MIN MAX
2.4
2.3
2.9
2.2
2.8
1.2
1.3
1.7
4.4
4.2
4.9
4.1
4.7
2.9
2.2
2.6
6.6
6.3
7.0
6.1
6.7
4.6
2.5
2.5
0.5 1.0 1.5 ns
0.3 1.0 1.5 ns
T
= –40 to +85°C,
amb
VCC = 3.3V±10%,
R
= 16.5Ω
L
1.0
1.1
1.2
1.7
1.0
1.0
0.5
0.5
T
= –40 to +85°C,
amb
V
= 3.3V±10%
CC
2.1
2.1
2.5
1.4
2.5
1.0
0.9
0.8
5.2
5.1
6.5
6.2
6.0
5.6
3.0
3.0
7.4
7.3
7.9
6.7
7.3
5.3
3.0
3.0
UNIT
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
1998 Dec 07
8
Page 9
Philips Semiconductors Product specification
FBL220403.3V BTL 8-bit TTL to BTL transceiver
AC WAVEFORMS
AIn, Bn
OEB1
AOn, Bn
V
M
t
PLH
V
M
t
PHL
V
M
V
M
Waveform 1. Propagation Delay for Data
or Output Enable to Output
AIn, Bn
AOn, Bn
Waveform 3. Output Skews
OEA
AOn
V
M
t
PZH
V
M
t
PHZ
V
M
VOH -0.3V
OV
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
NOTE: V
= 1.55V for Bn, V
M
V
M
tSK(o)
AIn, Bn
OEB0
AOn, Bn
V
M
t
PHL
V
M
t
PLH
V
M
Waveform 2. Propagation Delay for Data
or Output Enable to Output
V
M
OEA
AOn
V
M
t
PZL
V
M
t
PLZ
V
M
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
= 1.5V for all others.
M
V
M
VOL +0.3V
SG00078
1998 Dec 07
9
Page 10
Philips Semiconductors Product specification
FBL220403.3V BTL 8-bit TTL to BTL transceiver
TEST CIRCUIT AND WAVEFORMS
V
CC
BIAS
V
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
Test Circuit for 3-State Outputs on A Port
SWITCH POSITION
TEST SWITCH
PULSE
GENERATOR
t
t
PLZ,
PZL
All other
V
IN
BIAS
V
V
D.U.T.
closed
open
CC
V
OUT
R
L
R
C
L
L
2.0V (for RU = 9 Ω)
2.1V (for RU = 16.5 Ω)
R
U
7.0V
NEGATIVE
PULSE
POSITIVE
PULSE
Family
FB+
A Port
90%
10%
t
W
10%
90%
V
M
V
V
M
10%
(tf)
t
THL
t
(tr)
TLH
90%
V
M
t
W
VM = 1.55V for Bn, VM = 1.5V for all others.
Input Pulse Definitions
INPUT PULSE REQUIREMENTS
Low V
0.0V
1.0VB Port
Rep. RateAmplitude t
1MHz3.0V
1MHz2.0V
t
500ns
M
W
2.5ns
2.5ns500ns
V
t
TLH
t
THL
LOW V
(tr)
(tf)
V
LOW V
IN
IN
90%
10%
TLHtTHL
2.5ns
2.5ns
R
T
Test Circuit for Outputs on B Port
C
D
DEFINITIONS:
RL= Load Resistor; see AC CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
CD= Load capacitance includes jig and probe capacitance; see AC
of pulse generators.
OUT
CHARACTERISTICS for value.
RU= Pull up resistor; see AC CHARACTERISTICS for value.
SG00059
1998 Dec 07
10
Page 11
Philips Semiconductors Product specification
3.3V BTL 8-bit TTL TO BTL transceiver
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm SOT379-1
74FBL22040
1998 Dec 07
11
Page 12
Philips Semiconductors Product specification
3.3V BTL 8-bit TTL TO BTL transceiver
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74FBL22040
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04972
1998 Dec 07
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