Datasheet FBL22031BB Datasheet (Philips)

INTEGRATED CIRCUITS

FBL22031

9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver with 30Ω
termination

Product specification 1998 Sep 04
IC23 data handbook

Philips Semiconductors

Philips Semiconductors Product specification

mA

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

FEA TURES

•Latched, registered or straight through in either A to B or B to A

path

•Drives heavily loaded backplanes with equivalent load

impedances down to 10Ω.

•High drive 100mA BTL open collector drivers on B-port

•Allows incident wave switching in heavily loaded backplane buses

•Reduced BTL voltage swing produces less noise and reduces

power consumption

•Built-in precision band-gap reference provides accurate receiver

thresholds and improved noise immunity

•Compatible with IEEE Futurebus+ or proprietary BTL backplanes

•Each BTL driver has a dedicated Bus GND for a signal return

•Controlled output ramp and multiple GND pins minimize ground

bounce

•Glitch-free power up/power down operation

•Low I

current

CC

•Tight output skew

•Supports live insertion

•Pins for the optional JTAG boundary scan function are provided

•High density packaging in plastic Quad Flatpack

•5V compatible I/O on A-port

•Same pinout and function as the FBL2033 except for 30Ω sereis

•The A output includes a a series resistor of 30Ω making external

DESCRIPTION

The FBL22031 is a 9-bit latched/registered transceiver featuring a
latched, registered or pass-thru mode in either the A-to-B or B-to-A
direction.

The FBL22031 is designed with a 30Ω series resistor in both the
HIGH and LOW states of the output.

The FBL22031 is intended to provide the electrical interface to a
high performance wired-OR bus.

FBL22031

termination

terminating resistors unnecessary

QUICK REFERENCE DATA

SYMBOL PARAMETER TYPICAL UNIT

t

PLH

t

PHL

t

PLH

t

PHL

C
I

I

O

OL

CC

Propagation delay
An to Bn

Propagation delay
Bn to An

Output capacitance (B0 – Bn only) 6 pF
Output current (B0 – Bn only) 100 mA

AIn to Bn (outputs Low or High) 11

Supply current

Bn to AOn (outputs Low) 22
Bn to AOn (outputs High) 18

2.7 ns

4.4

4.2

ORDERING INFORMATION

PACKAGE VCC = 3.3V±10%; T

52-pin Plastic Quad Flat Pack (PQFP) FBL22031BB SOT379-1

= –40°C to +85°C

amb

ns

DWG

No.

1998 Sep 04 853-21 19 19967

2

Philips Semiconductors Product specification

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

PIN CONFIGURATION

CC

V

LOGIC GND

LOGIC GND

LOGIC GND

LOGIC GND

LOGIC GND

LOGIC GND

LOGIC GND

LOGIC GND

A1

A0

52 51 50 49 48 47 46 45 44 43 42 41 40

1
2

A2

3
4

A3

A4

A5

A6

A7

9-Bit latched/registered transceiver

5
6

7
8

9
10
11

12
13

14 15 16 17 18 19 20 21 22 23 24 25 26

A8

SEL1

LCBA

OEA

BIAS V

FBL22031

52-lead PQFP

CC

LCAB

BG V

BG GND

OEB1

OEB0

SEL0

TDO (option)

CC

TMS (option)

TCK (option)

V

B8

CC

V

TDI (option)

B0

BUS GND

39
38
37
36
35

34
33
32
31
30
29
28
27

B7

BUS GND

FBL22031

BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND
B5
BUS GND
B6
BUS GND

SG00091

DESCRIPTION

The TTL-level side (A port) has a common I/O. The common I/O,
open collector B port operates at BTL signal levels. The logic
element for data flow in each direction is controlled by two mode
select inputs (SEL0 and SEL1). A “00” configures latches in both
directions. A “10” configures thru mode in both directions. A “01”
configures register mode in both directions. A “11” configures
register mode in the A-to-B direction and latch mode in the B-to-A
direction.

When configured in the buffer mode, the inverse of the input data
appears at the output port. In the register mode, data is stored on
the rising edge of the appropriate clock input (LCAB or LCBA). In the
latch mode, clock pins serve as transparent-Low latch enables.
Regardless of the mode, data is inverted from input to output.

The 3-State A port is enabled by asserting a High level on OEA. The
B port has two output enables, OEB0 and OEB1
is High and OEB1

When either OEB0 is Low or OEB1

is Low is the output enabled.

is High, the B port is inactive
and is pulled to the level of the pullup voltage. New data can be
entered in the register and latched modes or can be retained while
the associated outputs are in 3-State (A port) or inactive (B port).

The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V .

The B-port interfaces to “Backplane Transceiver Logic” (see the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading by placing an internal series diode on the

. Only when OEB0

drivers. BTL also provides incident wave switching, a necessity for
high performance backplanes.

Output clamps are provided on the BTL outputs to further reduce
switching noise. The “V
during a Low-to-High transition. The “V
The other clamp, the “trapped reflection” clamp, clamps out ringing
below the BTL 0.5V V
approximately 100ns after a High-to-Low transition.

” clamp reduces inductive ringing effects

OH

level. This clamp remains active for

OL

” clamp is always active.

OH

To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch- free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a

3.3V level while V
which will reverse-bias the BTL driver series Schottky diode, and

is Low. The BIAS V pin is a low current input

CC

also bias the B port output pins to a voltage between 1.62V and

2.1V. This bias function is in accordance with IEEE BTL Standard

1194.1. If live insertion is not a requirement, the BIAS V pin should
be tied to a V

CC

pin.

The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
package.

Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be
infrequent and impossible to troubleshoot.

As with any high power device, thermal considerations are critical. It
is recommended that airflow (300Ifpm) and/or thermal mounting be
used to ensure proper junction temperature.

1998 Sep 04

3

Philips Semiconductors Product specification

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

P ACKAGE THERMAL CHARACTERISTICS

PARAMETER CONDITION 52-PIN PLASTIC QFP

θja Still air 80°C/W
θja 300 Linear feet per minute air flow 58°C/W
θjc Thermally mounted on one side to heat sink 20°C/W

PIN DESCRIPTION

SYMBOL PIN NUMBER TYPE NAME AND FUNCTION

A0 – A8 50, 52, 2, 4, 6, 8, 10, 12, 14 I/O BiCMOS data inputs/3-State outputs (TTL)
B0 – B8

OEB0 46 Input Enables the B outputs when High
OEB1 45 Input Enables the B outputs when Low

OEA 47 Input Enables the A outputs when High

BUS GND

LOGIC GND 51, 1, 3, 5, 7, 9, 11, 13 GND Logic ground (0V)

V

CC

BIAS V 48 Power Live insertion pre-bias pin

BG V

CC

BG GND 19 GND Band Gap threshold voltage reference ground

SEL0 20 Input Mode select

SEL1 15 Input Mode select
LCAB 18 Input A to B clock/latch enable (transparent latch when Low)
LCBA 16 Input B to A clock/latch enable (transparent latch when Low)

TMS 42 Input Test Mode Select (optional, if not implemented then no connect)

TCK 44 Input Test Clock (optional, if not implemented then no connect)

TDI 22 Input Test Data In (optional, if not implemented then no connect)

TDO 21 Output Test Data Out (optional, if not implemented then shorted to TDI)

40, 38, 36, 34, 32,

30, 28, 26, 24

25, 27, 29, 31, 33,

35, 37, 39, 41

23, 43, 49 Power Positive supply voltage

17 Power Band Gap threshold voltage reference

I/O Data inputs/Open Collector outputs, High current drive (BTL)

GND Bus ground (0V)

FBL22031

1998 Sep 04

4

Philips Semiconductors Product specification

MODE

An to Bn thru mode

An to Bn transparent latch

An to Bn latch and read

An to Bn register

Bn to An thru mode

Bn to An transparent latch

Bn to An latch and read

Bn to An register

Disable Bn outputs

Latch mode (Bn to An)

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

FUNCTION TABLE

INPUTS OUTPUTS

An Bn* OEB0 OEB1 OEA LCAB LCBA SEL0 SEL1 An Bn

L — H L L X X H L input H**

H — H L L X X H L input L

p

Bn outputs latched and read
(preconditioned latch)

p

An outputs latched and read
(preconditioned latch)

p

Disable An outputs X X X X L X X X X Z X

L — H L L L X L L input H**

H — H L L L X L L input L

l — H L L ↑ X L L input H**

h — H L L ↑ X L L input L

X — H L X H X L L X

l — H L L ↑ X X H input H**

h — H L L ↑ X X H input L
— L Disable H X X H L H input
— H Disable H X X H L L input
— L Disable H X L L L H input
— H Disable H X L L L L input
— L Disable H X L H H H input
— H Disable H X L H H L input
— l Disable H X ↑ L L H input
— h Disable H X ↑ L L L input
— l Disable H X ↑ H H H input
— h Disable H X ↑ H H L input

— X X X H X H L L

— X X X H X H H H
— l Disable H X ↑ L H H input

— h Disable H X ↑ L H L input

X X L X X X X X X X H**
X X X H X X X X X X H**

FBL22031

latched

data

latched

data

latched

data

X

X

FUNCTION SELECT TABLE

NOTES:

H = High voltage level
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High
LCXX transition
h = High voltage level one set-up time prior to the Low-to-High
LCXX transition
X = Don’t care

1998 Sep 04

MODE SELECTED SEL0 SEL1

Thru mode H L
Register mode (An to Bn) X H
Latch mode (An to Bn) L L
Register mode (Bn to An) L H

L L

H H

Z = High-impedance (OFF) state
— = Input not externally driven
↑ = Low-to-High transition
H** = Goes to level of pull-up voltage

* = Precaution should be taken to ensure B inputs do not float.

Bn
If they do, they are equal to Low state.
Disable = OEB0 is Low or OEB1

5

is High.

Philips Semiconductors Product specification

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

LOGIC DIAGRAM

46

OEB0

45

OEB1

47

OEA

DQ
E
DQ

14

A8

12

A7

Clk

MUX

A ⇐ B

DQ
E

DQ
Clk

MUX

A ⇒ B

MUX

A ⇒ B

DQ

QD

E

DQ

Clk

FBL22031

24

B8

26

B7

28

TTL

LCAB

SEL0
SEL1

LCBA

10

8

6

4

2

52

A1

50

A0

18

20
15

16

DQ
E

DQ
Clk

DQ
E
DQ
Clk

Decode

OutIn

MUX

A ⇐ B

MUX

A ⇐ B

MUX

A ⇐ B

DQ

E

DQ

Clk

MUX

A ⇒ B

DQ

E

DQ

Clk

MUX

A ⇒ B

DQ

E

DQ

Clk

30

32

BTL

34

36

38

B1

40

B0

1998 Sep 04

TMS
TCK

TDI

TDO

42

(JTAG Boundary Scan pins)

44
22
21

LOGIC GND = 1, 3, 5, 7, 9, 11, 13, 51
BUS GND = 25, 27, 29, 31, 33, 35, 37, 39, 41
BIAS V = 48

V

CC

BG V
BG GND = 19

CC

= 23, 43, 49
=17

SG00061

6

Philips Semiconductors Product specification

V

In ut voltage

I

V

High-level in ut voltage

V

Low-level in ut voltage

I

Low-level out ut current

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

ABSOLUTE MAXIMUM RATINGS

Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.

SYMBOL

V

V

T

CC

IN

I

IN

OUT

OUT

STG

Supply voltage -0.5 to +4.6 V

p

Input current
Voltage applied to output in High output state -0.5 to +7.0 V

Current applied to output in AO0 – AO8 24, –24 mA
Low output state/High output state B0 – B8 200
Storage temperature -65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

SYMBOL

V

CC

IH

IL

I

IK

I

OH

OL

C

OB

T

amb

Supply voltage 3.0 3.3 3.6 V

p

p

Input clamp current -18 mA
High-level output current AO0 – AO8 -12 mA

p

Output capacitance on B port 6 7 pF
Operating free-air temperature range 0 +70 °C

PARAMETER

PARAMETER RATING UNIT

AI0 – AI6, OEB0, OEBn, OEAn -0.5 to +7.0 V

B0 – B8 -0.5 to +3.5
VIN  0

COMMERCIAL LIMITS

VCC = 3.3V±10%;

T

= –40 to +85°C

amb

MIN TYP MAX

Except B0–B8 2.0 V
B0 – B8 1.62 1.55
Except B0–B8 0.8 V
B0 – B8 1.47

AO0 – AO8 +12 mA
B0 – B8 100

FBL22031

-50

UNIT

1998 Sep 04

7

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

I

(

BIASV

)

IOLOFF

Power u current

µA

1

SYMBOL

PARAMETER

TEST CONDITIONS

1

UNIT

I

Power-off out ut current

B0

B8

µA

V

g

AO0

AO8

3
3

AO0

AO8

3

V

I

g

µ

mA

IILLow-level in ut current

B0

B8

V

MAX, V

75V

100

µA

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

LIVE INSERTION SPECIFICA TIONS

LIMITS

MIN TYP MAX

V

BIASV

BIASV

V

I
I

IBnPEAK

Bias pin voltage
Bias pin (I

DC current
Bus voltage during prebias B0 – B8 = 0V, Bias V = 3.3V 1.62 2.1 V

Bn

Fall current during prebias B0 – B8 = 2V, Bias V = 1.3 to 2.5V 1 µA

LM

Rise current during prebias B0 – B8 = 1V, Bias V = 3 to 3.6V -1 µA

HM

BIASV

) input

Peak bus current during
insertion

p

t

Input glitch rejection VCC = 3.3V 1.0 1.35 ns

GR

DC ELECTRICAL CHARACTERISTICS

Over recommended operating free-air temperature range unless otherwise noted.

I

OFF

V

V

I

OZH

I

OZL

I

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.

2. All typical values are at V

3. Due to test equipment limitations, actual test conditions are V

4. Unused pins are at V

5. For B port input voltage between 3 and 5 volt; I
is active).

High level output current B0 – B8 VCC = MAX, VIL = MAX, VOH = 1.9V 100 µA

OH

p

High-level output

OH

voltage

Low-level output voltage

OL

Input clamp voltage VCC = MIN, II = I

IK

I

Input leakage current

I

I

High-level input current B0 – B8

IH

p

Off-state output current AO0 – AO8 VCC = MAX, VO =3V 5 µA
Off-state output current AO0 – AO8 VCC = MAX, VO = 0.5V -5 µA

Supply current (total)

CC

= 3.3V, TA = 25°C.

CC

or GND.

CC

Voltage dif ference between the Bias voltage
and VCC after the PCB is plugged in.

– – 0.5 V

VCC = 0 V, Bias V = 3.6V 1.2 mA
VCC = 3.3V, Bias V = 3.6V 10 µA

VCC = 0 to 3.3V, B0 – B8 = 0 to 2.0V,
Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns

V

= 0 to 3.3V, OEB0 = 0.8V 100

CC

V

= 0 to 1.2V, OEB0 = 0 to 5V 100

CC

MIN TYP2MAX

–

–

VCC = 0V, VIL = MAX, VOH = 1.9V 100
VCC = 0V, VIL = MAX, VOH = 1.9V @ 85°C 300

V

VCC = MIN to MAX, IOH = –100µA

CC

–0.2
VCC = MIN; IOH = –4mA 2.4 V
VCC = MIN; IOH = –12mA 2.0 V

–

VCC = MIN; IOL = 4mA 0.4 V
VCC = MIN; IOL = 12mA 0.8 V

B0 – B8 VCC = MIN, IOL = 4mA 0.5

VCC = MIN, IOL = 100mA 0.75 1.0 1.20

= –18mA –0.85 -1.2 V

IK

Control pins VCC = 3.6V; VI = VCC or 100mV ±1.0
Control/

AI0 – AI8
AI0 – AI8 VCC = 3.6V; VI = V

VCC = 0V or 3.6V; VI = 5.5V 10

CC

Note 4 VCC = 3.6V; VI = 100mV –5

VCC = MAX, VI = 1.9V 100 µA
VCC = MAX, VI = 3.5V , note 5 100
VCC = MAX, VI = 3.75V, note 5 @ –40°C 100

–

I

B to A VCC = MAX, outputs High 18 32

CCH

I

B to A VCC = MAX, outputs Low 22 37

CCL

I

A to B VCC = MAX, outputs High 11 16

CCH

I

A to B VCC = MAX, outputs Low 11 16

CCL

I

CCZ

will be greater than 100mA but the part will continue to function normally (clamping circuit

IH

CC

=

= 0.

I

VCC = MAX 18 32

= 1.8V and VIL = 1.3V for the B side.

IH

FBL22031

10 mA

LIMITS

V

µA

1

-

mA

1998 Sep 04

8

Philips Semiconductors Product specification

Waveform 1, 2

ns

Waveform 1, 2

ns

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

AC ELECTRICAL CHARACTERISTICS

B TO A SPECIFICATIONS

SYMBOL PARAMETER

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PHZ

t

PZL

t

PLZ

t

TLH

t

THL

tSK(o)

tSK(p)

Maximum clock frequency Waveform 4 120 150 MHz
Propagation delay (thru mode)

Bn to An
Propagation delay (transparent latch)

Bn to An
Propagation delay

LCBA to An (latch)
Propagation delay

LCBA to An (register)
Propagation delay

SEL0 or SEL1 to An (inverting)
Propagation delay

SEL0 or SEL1 to An (non-inverting)
Output enable time from High or Low

OEA to An
Output disable time to High or Low

OEA to An
Output transition time, An Port

10% to 90%, 90% to 10%
Output to output skew for multiple

channels
Pulse skew

 t

PHL

– t

1

PLH

2



MAX

TEST

CONDITION

Waveform 1, 2

Waveform 1, 2

Waveform 5, 6

Waveform 5, 6

Test Circuit and

Waveforms

Waveform 3 0.5 1.0 1.5 ns

Waveform 2 0.5 1.0 1.5 ns

NOTES:

1.  t

actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL.

PN

Skew times are valid only under same test conditions (temperature, V
other path or compares t

2. t

(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

SK

duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

on a given path to t

PHL

on any other path.

PHL

, loading, etc.). tSK (0) compares t

CC

T

= +25°C,

amb

VCC = 3.3V,

T

amb

VCC = 3.3V±10%,

MIN TYP MAX MIN MAX

2.3

2.6

3.2

3.5

6.8

5.5

2.1

2.3

2.7

2.5

2.4

2.6

2.6

3.4

2.1

1.2

5.4

5.6

6.5

6.3

10.4

9.8

4.9

5.2

6.5

6.3

6.6

6.2

5.8

5.4

5.4

3.1

8.9

9.1

10.1

9.3

14.4

14.7

8.4

8.3

10.7

10.5

11.3

10.2

9.3

7.5

9.1

5.4

on a given path to t

PLH

FBL22031

= –40 to +85°C,

1.7

2.1

2.4

2.9

5.1

4.3

1.2

1.8

1.8

2.0

1.8

2.1

1.9

2.9

1.6

1.0

0.7

0.5

10.1

10.3

11.6

10.3

16.9

16.8

9.7

9.4

12.8

11.8

13.0

11.6

10.7

9.0

10.1

6.0

3.0

2.0

PLH

UNIT

ns

ns

ns

ns

ns

on any

1998 Sep 04

9

Philips Semiconductors Product specification

Waveform 1, 2

ns

Waveform 1, 2

ns

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

AC ELECTRICAL CHARACTERISTICS

A TO B 9 Ω LOAD SPECIFICATIONS

SYMBOL PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

TLH

t

THL

tSK(o)

tSK(p)

Propagation delay (thru latch)
An to Bn

Propagation delay (transparent latch)
An to Bn

Propagation delay
LCAB to Bn (latch)

Propagation delay
LCAB to Bn (register)

Propagation delay
SEL0 or SEL1 to Bn (inverting)

Propagation delay
SEL0 or SEL1 to Bn (non-inverting)

OEBn to Bn Waveform 1, 2
Output transition time, Bn Port

(1.3V to 1.8V)
Output to output skew for multiple

channels
Pulse skew

 t

PHL

– t

1

PLH

2



MAX

TEST

CONDITION

Waveform 1, 2

Waveform 1, 2

Test Circuit and

Waveforms

Waveform 3 0.4 1.0 2.0 ns

Waveform 2 0.3 1.0 1.5 ns

NOTES:

actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or

1.  t

PN

HL. Skew times are valid only under same test conditions (temperature, V
any other path or compares t

(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

2. t

SK

duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

on a given path to t

PHL

on any other path.

PHL

, loading, etc.). tSK (0) compares t

CC

T

= +25°C,

amb

VCC = 3.3V,

T

amb

VCC = 3.3V±10%,

MIN TYP MAX MIN MAX

1.2

1.2

1.2

1.3

7.2

7.2

1.2

1.4

1.2

1.6

1.9

1.9

1.2

1.2

3.5

3.1

3.8

4.0

12.0

11.1

4.4

4.3

5.1

4.6

5.6

4.7

4.0

3.7

8.1

6.5

8.6

7.7

17.4

15.5

8.8

7.5

9.8

8.1

9.9

7.9

8.4

6.7

PLH

FBL22031

= –40 to +85°C,

1.0

1.0

1.0

1.0

5.3

5.6

1.0

1.0

1.0

1.1

1.0

1.3

1.0

1.0

1.2

0.4

on a given path to t

9.1

6.9

9.5

8.4

20.5

17.8

10.2

8.4

11.4

9.9

11.2

9.0

9.8

8.0

3.0

1.5

UNIT

ns

ns

ns

ns

PLH

on

1998 Sep 04

10

Philips Semiconductors Product specification

Waveform 1, 2

ns

Waveform 1, 2

ns

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

AC ELECTRICAL CHARACTERISTICS

A TO B 16.5 Ω LOAD SPECIFICATIONS

SYMBOL PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

TLH

t

THL

tSK(o)

tSK(p)

Propagation delay (thru latch)
An to Bn

Propagation delay (transparent latch)
An to Bn

Propagation delay
LCAB to Bn (latch)

Propagation delay
LCAB to Bn (register)

Propagation delay
SEL0 or SEL1 to Bn (inverting)

Propagation delay
SEL0 or SEL1 to Bn (non-inverting)

OEBn to Bn Waveform 1, 2
Output transition time, Bn Port

(1.3V to 1.8V)
Output to output skew for multiple

channels
Pulse skew

 t

PHL

– t

1

PLH

2



MAX

TEST

CONDITION

Waveform 1, 2

Waveform 1, 2

Test Circuit and

Waveforms

Waveform 3 0.4 1.0 2.0 ns

Waveform 2 0.3 1.0 1.5 ns

NOTES:

actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or

1.  t

PN

HL. Skew times are valid only under same test conditions (temperature, V
any other path or compares t

(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

2. t

SK

duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

on a given path to t

PHL

on any other path.

PHL

, loading, etc.). tSK (0) compares t

CC

T

= +25°C,

amb

VCC = 3.3V,

T

amb

VCC = 3.3V±10%,

MIN TYP MAX MIN MAX

1.2

1.3

1.2

1.6

6.6

6.7

1.2

1.2

1.3

1.7

1.8

1.8

1.3

1.7

4.1

3.5

4.3

4.3

11.8

10.9

4.3

4.1

5.3

4.9

5.6

4.7

4.4

4.0

7.4

5.9

8.0

7.3

17.6

15.7

8.8

7.6

9.7

8.6

9.8

7.9

8.1

6.7

PLH

FBL22031

= –40 to +85°C,

1.0

1.1

1.0

1.2

4.8

5.2

1.0

1.0

1.0

1.3

1.0

1.1

1.0

1.0

1.2

0.4

on a given path to t

8.7

6.4

9.3

8.1

20.6

18.1

10.1

8.5

11.2

9.6

11.3

9.0

9.4

7.8

3.0

1.5

UNIT

ns

ns

ns

ns

PLH

on

1998 Sep 04

11

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

AC SETUP REQUIREMENTS (Commercial)

TEST

CONDITION

ts(H)

ts(L)

th(H)

th(L)

ts(H)

t

(L)

s

th(H)

th(L)

tw(H)
tw(L)

AC WAVEFORMS

Setup time
An to LCAB

Hold time
An to LCAB

Setup time
Bn

to LCBA

Hold time
Bn to LCBA

Pulse width, High or Low
LCAB or LCBA

Waveform 4

Waveform 4

Waveform 4

Waveform 4

Waveform 4

LIMITS

T

T

= +25°C, VCC = 3.3V,

amb

amb

VCC = 3.3V±10%,

CL = 50pF (A side) / CD = 30pF (B side)

RL = 500Ω (A side) / RU = 16.5Ω (B side)

MIN TYP MIN

1.0

1.0

1.0

1.0

2.0

2.0

0.0

0.0

3.0

3.0

FBL22031

= –40 to +85°C,

1.5

1.0

2.0

1.0

3.0

3.0

0.0

0.0

3.0

3.0

ns

ns

ns

ns

ns

Input

Output

V

M

t

PLH

V

M

t

PHL

V

M

V

M

Waveform 1. Propagation Delay for Data

or Output Enable to Output

An, Bn

An, Bn

V

M

tSK(o)

V

M

Waveform 3. Output to Output Skew

OEA

An

V

M

t

PZH

V

M

t

PHZ

V

M

VOH -0.3V

OV

Waveform 5. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

NOTE: V

= 1.55V for Bn, V

M

The shaded areas indicate when the input is permitted to change for predictable output performance.

= 1.5V for all others.

M

Input

Output

V

M

t

(input)

w

t

PHL

V

M

t

(output)

w

V

M

t

PLH

V

M

Waveform 2. Propagation Delay for Data

or Output Enable to Output

V

An, Bn

LCAB, LCBA

M

t

t

s

h

V

M

t

(H)

w

1/f

MAX

tst

h

t

(L)

w

V

M

Waveform 4. Setup and Hold Times,

Pulse Widths and Maximum Frequency

OEA

V

M

t

PZL

An

V

M

t

PLZ

V

M

VOL +0.3V

Waveform 6. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

SG00062

1998 Sep 04

12

Philips Semiconductors Product specification

3.3V BTL 9-bit latched/registered/pass-thru
universal transceiver with 30Ω termination

TEST CIRCUIT AND WAVEFORMS

V

CC

7.0V
NEGATIVE
PULSE

POSITIVE
PULSE

Family

FB+

A Port

DEFINITIONS:

RL= Load Resistor; see AC CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance; see AC

CHARACTERISTICS for value.

R

= Termination resistance should be equal to Z

T

CD= Load capacitance includes jig and probe capacitance; see AC

CHARACTERISTICS for value.

RU= Pull up resistor; see AC CHARACTERISTICS for value.

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

Test Circuit for 3-State Outputs on A Port

SWITCH POSITION

TEST SWITCH

t

PLZ,

All other

PULSE

GENERATOR

t

PZL

V

IN

Test Circuit for Outputs on B Port

BIAS

V

R

T

closed

open

V

CC

D.U.T.

V

OUT

R

L

R

C

L

L

2.0V (for RU = 9 Ω)

2.1V (for RU = 16.5 Ω)

R

U

C

D

90%

10%

t

W

V

M

10%

(tf)

t

THL

t

(tr)

TLH

90%

V

M

t

W

VM = 1.55V for Bn, VM = 1.5V for all others.

10%

90%

V

M

V

Input Pulse Definitions

INPUT PULSE REQUIREMENTS

Low V

0.0V

1.0VB Port

Rep. RateAmplitude t

1MHz3.0V
1MHz2.0V

t

W

500ns

of pulse generators.

OUT

FBL22031

90%

t

TLH

t

THL

M

10%

TLHtTHL

2.5ns

2.0ns500ns

2.5ns

2.0ns

AMP (V)

LOW V

(tr)

(tf)

AMP (V)

LOW V

SG00063

1998 Sep 04

13

Philips Semiconductors Product specification

3.3V BTL 9-bit latched/registered/pass-thru

FBL22031

universal transceiver with 30Ω termination

Q30FP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm SOT379-1

1998 Sep 04

14

Philips Semiconductors Product specification

3.3V BTL 9-bit latched/registered/pass-thru
Futurebus+ transceiver with 30Ω termination

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

FBL22031

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 06-98
Document order number: 9397-750-04398

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