Datasheet FBL2041BB Datasheet (Philips)

INTEGRATED CIRCUITS

FBL2041
FBL2041I

3.3V BTL 7-bit Futurebus+ transceiver
(standard A-port)

Product specification
Supersedes data of 1998 Feb 13
IC23 Data Handbook




1998 May 11

Philips Semiconductors Product specification

ns

ns

ICCSu ly Current

mA

3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

FEA TURES

• 7-bit BTL transceiver

• Separate I/O on TTL A-port

• Inverting

• Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit

arrangement

• Drives heavily loaded backplanes with equivalent load

impedances down to 10Ω.

• High drive 100mA BTL open collector drivers on B-port

• Allows incident wave switching in heavily loaded backplane buses

• Reduced BTL voltage swing produces less noise and reduces

power consumption

• Built-in precision band-gap reference provides accurate receiver

thresholds and improved noise immunity

• Compatible with IEEE Futurebus+ or proprietary BTL backplanes

• Controlled output ramp and multiple GND pins minimize ground

bounce

• Each BTL driver has a dedicated Bus GND for a signal return

• Glitch-free power up/power down operation

• Low I

current

CC

• Tight output skew

• Supports live insertion

• Pins for the optional JTAG boundary scan function are provided

• High density packaging in plastic Quad Flatpack

• 5V compatible I/O on A-port

• Industrial temperature range option available as FBL2041I

DESCRIPTION

The FBL2041/FBL2041I is a 7-bit bidirectional BTL transceiver and
is intended to provide the electrical interface to a high performance
wired-OR bus. The FBL2041 is an inverting transceiver.

The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V .

The FBL2041/FBL2041I is pin and function compatible with FB2041
but operates at a 3.3V supply voltage, greatly reducing power
consumption.

The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.

There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement. The TTL/BTL output drivers for bit 0 are enabled with
OEA1/OEB1
OEA2/OEB2
OEA3/OEB3

The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEAn goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEAn goes Low, A-port drivers become High impedance
without any extra delay. During power on/of f cycles, the A-port
drivers are held in a High impedance state when V

The B-port has an output enable, OEB0, which affects all seven
drivers. When OEB0 is High and OEBn
be enabled. When OEB0 is Low or if OEBn
drivers will be inactive and at the level of the backplane signal.

To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a

3.3V level while V
BIAS V pin should be tied to a V

The LOGIC GND and BUS GND pins are isolated in the package to
minimize noise coupling between the BTL and TTL sides. These
pins should be tied to a common ground external to the package.

Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble-shoot.

JTAG boundary scan functionality is provided as an option with
signals TMS, TCK, TDI and TDO. When this option is not present,
TMS and TCK are no-connects (no bond wires) and TDI and TDO
are shorted together internally.

, output drivers for bits 1–2–3 are enabled with
and output drivers for bits 4–5–6 are enabled with
.

is Low. If live insertion is not a requirement, the

CC

FBL2041

FBL2041I

CC

is Low the output driver will

is High, the B-port

pin.

CC

is below 1.3V.

QUICK REFERENCE DATA

SYMBOL PARAMETER TYPICAL UNIT

t

PLH

t

PHL

t

PLH

t

PHL

C

I

OB

OL

pp

Propagation delay 4.2

AIn to Bn 3.5

Propagation delay 4.8

Bn to AOn 4.9

Output capacitance (B0 - B6 only) 6 pF

Output current (B0 - B6 only) 100 mA

Standby 5.2

AIn to Bn (outputs Low or High) 3.2

Bn to AOn (outputs Low) 13.5

Bn to AOn (outputs High) 10.7

ORDERING INFORMATION

PACKAGE

52-pin Plastic Quad Flatpack FBL2041 BB FBL2041I BB SOT379-1

1998 May 11 853-2040 19355

COMMERCIAL RANGE

VCC = 3.3V±10%; T

= 0 to +70°C

amb

VCC = 3.3V±10%; T

2

INDUSTRIAL RANGE

= –40 to +85°C

amb

DWG

No.

Philips Semiconductors Product specification

3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

PIN CONFIGURATION

CC

V

OEB1

TCK (option)

CC

V

TDI (option)

TDO (option)

TMS (option)

BUS GND

OEB2

OEA3

LOGIC GND

AI2

AO2

LOGIC GND

AO3

LOGIC GND

AI4

AO4

LOGIC GND

AO5

LOGIC GND

AI1

AI3

CC

V

AI0

AO1

52 51 50 49 48 47 46 45 44 43 42 41 40

1
2
3
4
5
6
7

8

9
10
11
12
13

14 15 16 17 18 19 20 21 22 23 24 25 26

AI5

LOGIC GND

BIAS V

AO0

OEA1

OEB0

7-Bit Transceiver

52-lead PQFP

CC

AI6

AO6

BG V

OEA2

BG GND

B0

39
38
37
36
35
34
33

32
31
30
29
28
27

OEB3

FBL2041

FBL2041I

BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND

B5
BUS GND
B6
N/C

SG00084

PIN DESCRIPTION

SYMBOL PIN NUMBER TYPE NAME AND FUNCTION

AI0 – AI6 51, 2, 3, 8, 9, 14, 18 Input Data inputs (TTL)

AO0 – AO6 50, 52, 4, 6, 10, 12, 16 Output 3-State outputs (TTL)

B0 – B6 40, 38, 36, 34, 32, 30, 28 I/O Data inputs/Open Collector outputs, High current drive (BTL)

OEB0 46 Input Enables the Bn outputs when High
OEB1 45 Input Enables the B0 output when Low
OEB2 25 Input Enables the B1 – B3 outputs when Low
OEB3 26 Input Enables the B4 – B6 outputs when Low
OEA1 47 Input Enables the A0 outputs when High
OEA2 20 Input Enables the A1 – A3 outputs when High
OEA3 24 Input Enables the A4 – A6 outputs when High

BUS GND 41, 39, 37, 35, 33, 31, 29 GND Bus ground (0V)

LOGIC GND 1, 5, 7, 11, 13, 15 GND Logic ground (0V)

LOGIC/bus V

BG V

CC

CC

BIAS V 48 Power Positive supply voltage

TMS 42 Input Test Mode Select (no-connect)
TCK 44 Input Test Clock (no-connect)

TDI 22 Input Test Data In (shorted to TDO)

TDO 21 Output Test Data Out (TDI)

BG GND 19 GND BAND GAP GROUND (0V)

23, 43, 49 Power Positive supply voltage

17 Power Positive supply voltage BAND GAP

1998 May 11

3

Philips Semiconductors Product specification

MODE

3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

FBL2041

FBL2041I

FUNCTION TABLE

INPUTS OUTPUTS

AIn Bn* OEB0 OEB1 OEB2 OEB3 OEA1 OEA2 OEA3 AOn Bn*

L — H L L L L L L Z H**

AIn to Bn H — H L L L L L L Z L

L — H L L L H H H L H**

H — H L L L H H H H L

L — H L X X L L L Z H**

AI0 to B0 H — H L X X L L L Z L

L — H L X X H H H L H**

H — H L X X H H H H L

L — H X L X L L L Z H**

AI1 – AI3 to B1 – B3 H — H X L X L L L Z L

L — H X L X H H H L H**

H — H X L X H H H H L

L — H X X L L L L Z H**

AI4 – AI6 to B4 – B6 H — H X X L L L L Z L

L — H X X L H H H L H**

H — H X X L H H H H L

Disable Bn outputs X X L X X X X X X X H**

X X X H H H X X X X H**
Disable B0 outputs X X H H X X X X X X H**
Disable B1 – B3 outputs X X H X H X X X X X H**
Disable B4 – B6 outputs X X H X X H X X X X H**

X L L X X X H H H H Input
Bn to AOn X H L X X X H H H L Input

X L X H H H H H H H Input

X H X H H H H H H L Input

X L L X X X H X X H Input
B0 to AO0 X H L X X X H X X L Input

X L X H H H H X X H Input

X H X H H H H X X L Input

X L L X X X X H X H Input
B1 – B3 to AO1 – AO3 X H L X X X X H X L Input

X L X H H H X H X H Input

X H X H H H X H X L Input

X L L X X X X X H H Input
B4 – B6 to AO4 – AO6 X H L X X X X X H L Input

X L X H H H X X H H Input

X H X H H H X X H L Input
Disable AOn outputs X X X X X X L L L Z X
Disable AO0 outputs X X X X X X L X X Z X
Disable AO1 – AO3 outputs X X X X X X X L X Z X
Disable AO4 – AO6 outputs X X X X X X X X L Z X

NOTES:

H = High voltage level
L = Low voltage level
X = Don’t care
Z = High-impedance (OFF) state
— = Input not externally driven
H** = Goes to level of pull-up voltage
B* = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.

1998 May 11

4

Philips Semiconductors Product specification

3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

LOGIC DIAGRAM

46

OEB0

45

OEB1

47

OEA1

51

AI0

50

AO0

25

OEB2

20

OEA2

2

AI1

52

AO1

3

AI2

4

AO2

TTL

Levels

AI3

AO3

8

6

FBL2041

FBL2041I

40

B0

38

B1

36

B2

34

BTL

Levels

B3

26

OEB3

24

OEA3

9

AI4

10

AO4

14

AI5

12

AO5

18

AI6

16

AO6

42

TMS

44

TCK

22

TDI

TDO

21

LOGIC V
LOGIC GND = 1, 5, 7, 11, 13, 15, 19
BUS V
BUS GND = 27, 29, 31, 33, 35, 37, 39, 41
BIAS V = 48

= 17, 49

CC

= 23, 43

CC

(Future JTAG Boundary Scan option)

32

B4

30

B5

28

B6

1998 May 11

SG00071

5

Philips Semiconductors Product specification

V

In ut voltage

I

mA

VIHHigh-level in ut voltage

V

VILLow-level in ut voltage

V

IOLLow-level out ut current

mA

3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

ABSOLUTE MAXIMUM RATINGS

Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.

SYMBOL

V

T

V

I

OUT

OUT

STG

CC

IN

IN

Supply voltage –0.5 to +4.6 V

p

Input current VIN  0 –50
Voltage applied to output in High output state –0.5 to +7.0 V
Current applied to output in AO0 – AO6 64, –64
Low output state/High output state B0 – B6 200
Storage temperature –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER

T

V

I

C

amb

Supply voltage 3.0 3.3 3.6 3.0 3.3 3.6 V

CC

p

p

I

Input clamp current –18 –18 mA

IK

High-level output current AO0 – AO6 –32 –32 mA

OH

p

Output capacitance on B port 6 7 6 7 pF

OB

Operating free-air temperature range 0 +70 –40 +85 °C

PARAMETER RATING UNIT

AI0 – AI6, OEB0, OEBn, OEAn –0.5 to +7.0

B0 – B6 –0.5 to +3.5 V

COMMERCIAL LIMITS

VCC = 3.3V±10%;

T

= 0 to +70°C

amb

MIN TYP MAX MIN TYP MAX

Except B0–B6 2.0 2.0
B0 – B6 1.62 1.55 1.62 1.55
Except B0–B6 0.8 0.8
B0 – B6 1.47 1.47

AO0 – AO6 +32 +32
B0 – B6 100 100

INDUSTRIAL LIMITS

VCC = 3.3V±10%;

T

= –40 to +85°C

amb

FBL2041

FBL2041I

UNIT

1998 May 11

6

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

I

(

BIASV

)

IOLOFF

Power up current

A

SYMBOL

PARAMETER

TEST CONDITIONS

1

UNIT

I

Power-off output current

B0

B6

3

voltage

AO0

AO6

3

B0

B6

V

IIInput leakage current

A

ICCSupply current (total)

mA

3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

FBL2041

FBL2041I

LIVE INSERTION SPECIFICA TIONS

LIMITS

MIN TYP MAX

V

BIASV

BIASV

V

I

I

Bias pin voltage

Bias pin (I
DC current

Bus voltage during prebias B0 – B8 = 0V, Bias V = 3.3V 1.62 2.1 V

Bn

Fall current during prebias B0 – B8 = 2V, Bias V = 1.3 to 2.5V 1 µA

LM

Rise current during prebias B0 – B8 = 1V, Bias V = 3 to 3.6V –1 µA

HM

BIASV

) input

IBnPEAK Peak bus current during insertion

p

t

Input glitch rejection VCC = 3.3V 1.0 1.35 ns

GR

DC ELECTRICAL CHARACTERISTICS

Over recommended operating free-air temperature range unless otherwise noted.

I

OFF

V

V

V

I

I

OZH

I

OZL

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.

2. All typical values are at V

3. Due to test equipment limitations, actual test conditions are V

4. Unused pins are at V

5. For B port input voltage between 3 and 5 volt; I
is active).

High level output current B0 – B6 VCC = MAX, VIL = MAX, VOH = 1.9V 100 µA

OH

p

High-level output

OH

Low-level output voltage

OL

Input clamp voltage VCC = MIN, II = I

IK

AO0 – AO6

Control pins VCC = 3.6V; VI = VCC or GND ±1.0

p

Control/ AI0 – AI6 VCC = 0V or 3.6V; VI = 5.5V 10
AI0 – AI6 VCC = 3.6V; VI = V
Note 4 VCC = 3.6V; VI = 0V –5

High-level input current B0 – B6

IH

I

Low-level input current B0 – B6 VCC = MAX, VI = 0.75V -100 µA

IL

Off-state output current AO0 – AO6 VCC = MAX, VO =3V 5 µA
Off-state output current AO0 – AO6 VCC = MAX, VO = 0.5V -5 µA

I

CCZ

I

pp

= 3.3V, TA = 25°C.

CC

or GND.

CC

CCB

I

CCL

I

CCH

Voltage dif ference between the Bias voltage and
VCC after the PCB is plugged in.

– – 0.5 V

VCC = 0 V, Bias V = 3.6V 1.2 mA
VCC = 3.3V, Bias V = 3.6V 10 µA

VCC = 0 to 3.3V, B0 – B8 = 0 to 2.0V,
Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns

V

= 0 to 3.3V, OEB0 = 0.8V 100

CC

V

= 0 to 1.2V, OEB0 = 0 to 5V 100

CC

LIMITS

2

–

MIN TYP

VCC = 0V, VIL = MAX, VOH = 1.9V 100 µA
VCC = 0V , VIL = MAX, VOH = 1.9V @ 85°C 300 µA
VCC = MIN to MAX; IOH = -100µA VCC –0.2 V
VCC = MIN; IOH = -8mA 2.4 V
VCC = MIN; IOH = -32mA 2.0 V

–

–

VCC = MIN; IOL = 16mA 0.4 V
VCC = MIN; IOL = 32mA 0.5 V
VCC = MIN, IOL = 4mA 0.5
VCC = MIN, IOL = 100mA 0.75 1.0 1.20

= –18mA –0.85 -1.2 V

IK

CC

VCC = MAX, VI = 1.9V 100 µA
VCC = MAX, VI = 3.5V , note 5 100 mA
VCC = MAX; VI = 3.75V @ –40°C 100 mA

VCC = MAX 5.2 13.5
VCC = MAX, outputs Low or High 3.2 9.0
VCC = MAX, outputs Low 13.5 19.5
VCC = MAX, outputs High 10.7 16.0

= 1.8V and VIL = 1.3V for the B side.

IH

will be greater than 100mA but the part will continue to function normally (clamping circuit

IH

10 mA

µ

MAX

1

µ

1998 May 11

7

Philips Semiconductors Product specification

TEST

amb

,

3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

AC ELECTRICAL CHARACTERISTICS

A PORT LIMITS

FBL2041

COMMERCIAL

T

= 0 to +70°C,

amb

VCC = 3.3V±10%,

SYMBOL PARAMETER

CONDITION

Tm = +25°C,

Vcc = 3.3V,

CL = 50pf, RL = 500Ω

CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX MIN MAX

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

TLH

t

THL

Propagation delay,
Bn to AOn

Output enable time,
OEA to AOn

Output disable time,
OEA to AOn

Transition time, AOn Port
(10% to 90%
or 90% to 10%)

Waveform 1, 2

Waveform 4, 5

Waveform 4, 5

Test Circuit

and Waveforms

3.9

4.0

5.3

2.4

3.5

2.3

0.7

0.5

4.8

4.9

6.6

4.4

4.8

3.1

1.8

1.6

5.8

6.0

8.0

8.0

6.0

3.9

3.0

2.0

3.7

3.8

5.0

2.1

3.4

2.2

0.7

0.5

6.4

6.7

8.6

8.5

6.5

4.3

3.0

2.0

Output skew between

tSK(o)

receivers in same
package

1

Waveform 3 0.7 1.5 1.5 1.5 ns

B PORT LIMITS

SYMBOL PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

TLH

t

THL

tSK(o)

Propagation delay,
AIn to Bn

Enable/disable time,
OEB0 to Bn

Enable/disable time,
OEB1 to Bn

Transition time, Bn Port
(1.3V to 1.8V)

Output skew between
drivers in same package

SYMBOL PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

TLH

t

THL

tSK(o)

Propagation delay,
AIn to Bn

Enable/disable time,
OEB0 to Bn

Enable/disable time,
OEB1 to Bn

Transition time, Bn Port
(1.3V to 1.8V)

Output skew between
drivers in same package

TEST

CONDITION

Waveform 1, 2

Waveform 2

Waveform 1

Test Circuit

and Waveforms

Waveform 3 1.5 1.5 1.5 ns

1

TEST

CONDITION

Waveform 1, 2

Waveform 2

Waveform 1

Test Circuit

and Waveforms

Waveform 3 1.5 1.5 1.5 ns

1

T

= +25°C,

amb

VCC = 3.3V,

CD = 30pF, RU = 9Ω

3.3

4.2

3.5

4.9

4.3

5.1

3.8

2.4

0.9

5.2

4.5

5.8

5.3

6.1

4.7

3.0

1.5

2.7

4.0

3.4

4.2

2.9

1.2

0.4

T

= 0 to +70°C,

amb

VCC = 3.3V±10%,

CD = 30pF, RU = 9Ω

2.9

2.5

3.6

3.1

3.9

2.6

1.2

0.4

6.0

5.0

6.6

6.0

6.9

5.5

3.0

1.5

RU = 16.5Ω RU = 16.5Ω RU = 16.5Ω UNIT

3.3

4.2

2.7

4.0

3.4

4.2

2.9

1.2

0.4

3.6

4.9

4.3

5.1

3.8

2.4

0.9

5.1

4.5

5.8

5.3

6.1

4.7

3.0

1.5

3.0

2.5

3.6

3.1

3.9

2.6

1.2

0.4

6.0

5.0

6.6

6.0

6.8

5.5

3.0

1.5

NOTES:

1.  t

actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or

PN

HL. Skew times are valid only under same test conditions (temperature, V

, loading, etc.).

CC

FBL2041I

INDUSTRIAL

T

= –40 to +85°C,

amb

VCC = 3.3V±10%,

CL = 50pF, RL = 500Ω

2.8

2.7

4.5

1.1

2.7

1.4

0.7

0.5

T

= –40 to +85°C,

amb

VCC = 3.3V±10%,

CD = 30pF, RU = 9Ω

1.8

1.7

2.8

2.5

2.9

1.9

1.2

0.4

1.8

1.7

2.7

2.5

3.0

1.9

1.2

0.4

FBL2041

FBL2041I

UNIT

6.9

7.0

9.0

9.0

7.0

4.7

3.0

2.0

6.7

5.6

7.1

6.4

7.3

6.0

3.0

1.5

6.7

5.6

7.1

6.4

7.3

6.0

3.0

1.5

ns

ns

ns

ns

UNIT

ns

ns

ns

ns

ns

ns

ns

ns

1998 May 11

8

Philips Semiconductors Product specification

3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

AC WAVEFORMS

VM = 1.55V for Bn, VM = 1.5V for all others.

V

AIn, Bn or Bn

OEBn

AOn or Bn

M

t

PLH

Waveform 1. Propagation Delay for Data or

Output Enable to Output

AIn, Bn

OEB0

AOn, Bn

V

M

t

PHL

V

M

t

PHL

V

M

V

M

SG00101

OEA

AOn

Waveform 4. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

V

M

t

PLH

V

M

V

M

OEA

AOn

FBL2041

FBL2041I

V

M

t

PZH

V

M

t

PZL

V

M

t

PHZ

V

M

V

M

t

V

M

VOH -0.3V

OV

SG00104

PLZ

VOL +0.3V

SG00102

Waveform 2. Propagation Delay for Data or

Output Enable to Output

AIn, Bn

AOn, Bn

V

M

tSK(o)

V

M

SG00103

Waveform 3. Output Skews

SG00105

Waveform 5. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

1998 May 11

9

Philips Semiconductors Product specification

3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

TEST CIRCUIT AND WAVEFORMS

V

CC

BIAS

V

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

Test Circuit for 3-State Outputs on A Port

SWITCH POSITION FOR ALL A-PORTS

TEST SWITCH

t
t

t

PULSE

GENERATOR

PLH,
PLZ,

PHZ,

t

PHL

t

PZL

t

PZH

V

IN

BIAS

V

R

T

OPEN

CLOSED

GND

V

CC

D.U.T.

2.0V (for RU = 9 Ω)

2.1V (for RU = 16.5 Ω)

V

OUT

Test Circuit for Outputs on B Port

R

R

C

L

R

U

C

D

6.0V

L

L

NEGATIVE
PULSE

POSITIVE
PULSE

Family

FB+

90%

10%

V

M

10%

90%

V

M

VM = 1.55V for Bn, VM = 1.5V for all others.

INPUT PULSE REQUIREMENTS

Low V

A Port

DEFINITIONS:

RL= Load Resistor; see AC CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance; see AC

CHARACTERISTICS for value.

R

= Termination resistance should be equal to Z

T

CD= Load capacitance includes jig and probe capacitance; see AC

CHARACTERISTICS for value.

RU= Pull up resistor; see AC CHARACTERISTICS for value.

t

W

(tf)

t

THL

t

(tr)

TLH

t

W

Input Pulse Definitions

Rep. RateAmplitude t

0.0V

1.0VB Port

1MHz3.0V
1MHz2.0V

FBL2041

FBL2041I

90%

V

M

10%

90%

V

M

10%

t

TLHtTHL

W

2.5ns

500ns

2.5ns500ns

of pulse generators.

OUT

t

TLH

t

THL

V

IN

LOW V

(tr)

(tf)

V

IN

LOW V

2.5ns

2.5ns

SG00090

1998 May 11

10

Philips Semiconductors Product specification

3.3V BTL 7-bit Futurebus+ transceiver (standard A port)

FBL2041

FBL2041I

QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm SOT379-1

1998 May 11

11

Philips Semiconductors Product specification

3.3V BTL 7-bit Futurebus+ transceiver (standard A port)

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

FBL2041

FBL2041I

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

Date of release: 05-98

Document order number: 9397 750 -03938




1998 May 11

12