Page 1
INTEGRATED CIRCUITS
FBL2033
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
Product specification 1999 Apr 15
IC23 data handbook
Philips Semiconductors
Page 2
Philips Semiconductors Product specification
I
CC
Su ly current
mA
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
FEA TURES
•8-bit transceivers
•Latched, registered or straight through in either A to B or B to A
path
•Drives heavily loaded backplanes with equivalent load
impedances down to 10Ω.
•High drive 100mA BTL Open Collector drivers on B-port
•Allows incident wave switching in heavily loaded backplane buses
•Reduced BTL voltage swing produces less noise and reduces
power consumption
•Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
QUICK REFERENCE DATA
SYMBOL PARAMETER TYPICAL UNIT
t
PLH
t
PHL
t
PLH
t
PHL
C
I
I
OB
OL
Propagation delay
AIn to Bn
Propagation delay
Bn to AOn
Output capacitance (B0 – Bn only) 6 pF
Output current (B0 – Bn only) 100 mA
Supply current
•Compatible with IEEE Futurebus+ or proprietary BTL backplanes
•Each BTL driver has a dedicated Bus GND for a signal return
•Controlled output ramp and multiple GND pins minimize ground
bounce
•Glitch-free power up/power down operation
•Low I
current
CC
•Tight output skew
•Supports live insertion
•Pins for the optional JTAG boundary scan function are provided
•High density packaging in plastic Quad Flatpack
•5V compatible I/O on A-port
3.0
3.0
5.0
5.3
AIn to Bn
outputs Low
outputs High
Bn to AOn (outputs Low) 17
Bn to AOn (outputs High) 14
9
14
FBL2033
ns
ns
mA
ORDERING INFORMATION
PACKAGE
52-pin Plastic Quad Flat Pack (PQFP) FBL2033BB SOT379-1
NOTE: Thermal mounting or forced air is recommended
PIN CONFIGURATION
AI1
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND
LOOPBACK
LOGIC GND
AO1
AI2
AO2
AI3
AO3
AI4
AO4
AO
1
2
3
4
5
6
7
8
9
10
AI
5
11
5
12
AI
6
13
14 15 16 17 18 19 20 21 22 23 24 25 26
AO6
VCC = 3.3V±10%; T
COMMERCIAL RANGE
AO0
AI0
LOGIC GND
CC
V
LCAB
SBA1
SBA0
CC
BG V
OEA
8-Bit Universal Transceiver
FBL2033
52-lead PQFP
AI7
AO7
LGOIC GND
CC
V
LCBA
SAB0
SAB1
CC
V
OEB0
BIAS V
BG GND
OEB1
BUS GND
= –40°C to +85°C
amb
B0
BUS GND
39
38
B1
37
BUS GND
B2
36
35
BUS GND
34
B3
BUS GND
33
B4
32
31
BUS GND
30
B5
29
BUS GND
B6
28
27
BUS GND
B7
SG00088
DWG
No.
1999 Apr 15 853-2156 21253
2
Page 3
Philips Semiconductors Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
DESCRIPTION
The FBL2033 is an 8-bit transceiver featuring a split input (AI) and
output (AO) bus on the TTL-level side.
The common I/O, open collector B port operates at BTL signal
levels. The logic element for data flow in each direction is controlled
by two pairs of mode select inputs (SBA0 and SBA1 for B-to-A,
SAB0 and SAB1 for A-to-B). It can be configured as a buffer, a
register, or a D-type latch.
When configured in the buffer mode, the inverse of the input data
appears at the output port. In the flip-flop mode, data is stored on
the rising edge of the appropriate clock input (LCAB or LCBA). In the
latch mode, clock pins serve as transparent-High latch enables.
Regardless of the mode, data is inverted from input to output.
Data flow in the B-to-A direction, regardless of the logic element
selected, is further controlled by the Loopback input. When the
Loopback input is High the output of the selected A-to-B logic
element (not inverted) becomes the B-to-A input.
The 3-State AO port is enabled by asserting a High level on OEA.
The B port has two output enables, OEB0 and OEB1
OEB0 is High and OEB1
OEB0 is Low or OEB1
the level of the pull-up voltage. New data can be entered in the
flip-flop and latched modes or can be retained while the associated
outputs are in 3-State (AO port) or inactive (B port).
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port ensure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V .
The B-port interfaces to “Backplane Transceiver Logic” (see the
IEEE 1194.1 BTL standard). BTL features low power consumption
is Low is the output enabled. When either
is High, the B-port is inactive and is pulled to
. Only when
FBL2033
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading by placing an internal series diode on the
drivers. BTL also provides incident wave switching, a necessity for
high performance backplanes.
Output clamps are provided on the BTL outputs to further reduce
switching noise. The “V
during a Low-to-High transition. The “V
The other clamp, the “trapped reflection” clamp, clamps out ringing
below the BTL 0.5V V
approximately 100ns after a High-to-Low transition.
To support live insertion, OEB0 is held Low during power on/off
cycles to ensure glitch- free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while V
which will reverse-bias the BTL driver series Schottky diode, and
also bias the B port output pins to a voltage between 1.62V and
2.1V. This bias function is in accordance with IEEE BTL Standard
1194.1. If live insertion is not a requirement, the BIAS V pin should
be tied to a V
The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble- shoot.
As with any high power device thermal considerations are
critical. It is recommended that airflow (300Ifpm) and/or thermal
mounting be used to ensure proper junction temperature.
CC
pin.
” clamp reduces inductive ringing effects
OH
level. This clamp remains active for
OL
is Low. The BIAS V pin is a low current input
CC
” clamp is always active.
OH
PIN DESCRIPTION
SYMBOL PIN NUMBER TYPE NAME AND FUNCTION
AI0 – AI7 50, 52, 3, 5, 8, 10, 12, 15 Input Data inputs (TTL)
AO0 – AO7 51, 2, 4, 6, 9, 11, 14, 16 Output 3-State outputs (TTL)
B0 – B7 40, 38, 36, 34, 32, 30, 28, 26 I/O Data inputs/Open Collector outputs, High current drive (BTL)
OEB0 23 Input Enables the B outputs when High
OEB1 24 Input Enables the B outputs when Low
OEA 43 Input Enables the AO outputs when High
BUS GND 39, 37, 35, 33, 31, 29, 27, 25 GND Bus ground (0V)
LOGIC GND 1, 13, 17, 49 GND Logic ground (0V)
V
CC
BIAS V 41 Power Live insertion pre-bias pin
BG V
CC
BG GND 42 GND Band Gap threshold voltage reference ground
SABn 20, 21 Input Mode select from AI to B
SBAn 45, 46 Input Mode select from B to AO
LCAB 47 Input A-to-B clock/latch enable (transparent latch when High)
LCBA 19 Input B-to-A clock/latch enable (transparent latch when High)
Loopback 7 Input Enables loopback function when High (from AIn to AOn)
18, 22, 48 Power Positive supply voltage
44 Power Band Gap threshold voltage reference
1999 Apr 15
3
Page 4
Philips Semiconductors Product specification
AIn to Bn thru mode
AIn to Bn transparent latch
AIn to Bn latch and read
AIn to Bn register
Bn to AOn thru mode
Bn to AOn transparent latch
Bn to AOn latch and read
Bn to AOn register
Disable Bn outputs
3.3V BTL 8-bit latched/registered/pass-thru
FBL2033
universal transceiver
FUNCTION TABLE
INPUTS OUTPUTS
MODE
p
Bn outputs latched and read
(preconditioned latch)
p
AOn outputs latched and read
(preconditioned latch)
p
Disable AOn outputs X X X X L X X XX XX Z X
AIn Bn* OEB0 OEB1 OEA LCAB LCBA
L — H L L X X LL XX Z H**
H — H L L X X LL XX Z L
L — H L L H X HX XX Z H**
H — H L L H X HX XX Z L
l — H L L ↓ X HX XX Z H**
h — H L L ↓ X HX XX Z L
L — H L L ↑ X LH XX Z H**
H — H L L ↑ X LH XX Z L
X — H L L L X HX XX Z
X L L H H X X XX LL H input
X H L H H X X XX LL L input
X L L H H X H XX HX H input
X H L H H X H XX HX L input
X l L H H X ↓ XX HX H input
X h L H H X ↓ XX HX L input
X L L H H X ↑ XX LH H input
X H L H H X ↑ XX LH L input
X X L H H X L XX HX
X X L X X X X XX XX X H**
X X X H X X X XX XX X H**
SAB
0
SBA
1
1
0
AOn Bn
latched
data
latched
data
X
FUNCTION SELECT TABLE
NOTES:
H = High voltage level
L = Low voltage level
h = High voltage level one set-up time prior to the High-to-Low LCXX transition
l = Low voltage level one set-up time prior to the High-to-Low LCXX transition
X = Don’t care
Z = High-impedance (OFF) state
— = Input not externally driven
↑ = Low-to-High transition
↓ = High-to-Low transition
H** = Goes to level of pull-up voltage
* = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
Bn
In Loopback mode (Loopback = High), AIn inputs are routed to the AOn outputs. The Bn
1999 Apr 15
MODE SELECTED SXX1 SXX0
Thru mode L L
Register mode L H
Latch mode H X
inputs are blocked out.
4
Page 5
Philips Semiconductors Product specification
V
In ut voltage
I
mA
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
LOGIC DIAGRAM
23
OEB0
24
OEB1
20
SAB0
21
SAB1
47
LCAB
50
AIn
LCBA
SBA0
SBA1
OEA
52,
2, 5,
8, 10,
12, 15
1 of 8 cells
19
45
46
43
D
En
D
Clk
40
36, 34,
32, 30,
FBL2033
Bn
38,
28, 26
D
AOn
2, 4, 6, 9,
11, 14, 16
Loopback
51
1 of 8 cells
7
En
D
Clk
BGGnd
BGref
42
SG00069
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.
SYMBOL
V
CC
IN
I
IN
V
OUT
OUT
T
STG
Supply voltage -0.5 to +4.6 V
p
Input current VIN 0 -50
Voltage applied to output in High output state -0.5 to +7.0 V
Current applied to output in AO0 – AO7 64, –64
Low output state/High output state B0 – B7 200
Storage temperature -65 to +150 °C
PARAMETER RATING UNIT
AI0 – AI7, OEB0, OEBn, OEAn -0.5 to +7.0 V
B0 – B7 -0.5 to +3.5
1999 Apr 15
5
Page 6
Philips Semiconductors Product specification
V
High-level in ut voltage
V
Low-level in ut voltage
I
Low-level out ut current
SYMBOL
PARAMETER
UNIT
I
(
BIASV
)
IOLOFF
Power up current
A
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
RECOMMENDED OPERATING CONDITIONS
SYMBOL
T
V
I
C
CC
IH
IL
I
IK
OH
OL
OB
amb
Supply voltage 3.0 3.3 3.6 V
p
p
Input clamp current -18 mA
High-level output current AO0 – AO7 -12 mA
p
Output capacitance on B port 6 7 pF
Operating free-air temperature range 0 +70 °C
LIVE INSERTION SPECIFICA TIONS
V
BIASV
BIASV
V
I
I
IBnPEAK
t
Bias pin voltage
Bias pin (I
DC current
Bus voltage during prebias B0 – B7 = 0V, Bias V = 3.3V 1.62 2.1 V
Bn
Fall current during prebias B0 – B7 = 2V, Bias V = 1.3 to 2.5V 1 µA
LM
Rise current during prebias B0 – B7 = 1V, Bias V = 3 to 3.6V -1 µA
HM
BIASV
) input
Peak bus current during
insertion
p
Input glitch rejection VCC = 3.3V 1.0 1.35 ns
GR
PARAMETER
Except B0–B7 2.0 V
B0 – B7 1.62 1.55
Except B0–B7 0.8 V
B0 – B7 1.47
AO0 – AO7 +12 mA
B0 – B7 100
Voltage dif ference between the Bias voltage
and VCC after the PCB is plugged in.
VCC = 0 V, Bias V = 3.6V 1.2 mA
VCC = 3.3V, Bias V = 3.6V 10 µA
VCC = 0 to 3.3V, B0 – B7 = 0 to 2.0V,
Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns
V
= 0 to 3.3V, OEB0 = 0.8V 100
CC
V
= 0 to 1.2V, OEB0 = 0 to 5V 100
CC
COMMERCIAL LIMITS
VCC = 3.3V±10%;
T
= –40 to +85°C
amb
MIN TYP MAX
LIMITS
MIN TYP MAX
– – 0.5 V
FBL2033
UNIT
10 mA
µ
1999 Apr 15
6
Page 7
Philips Semiconductors Product specification
symbol
parameter
test conditions
1
nit
I
Power-off output current
B0
B7
A
High level out ut
3
AO0
AO7
3
V
µ
I
g
µ
V
MAX, V
9V
100µA
mA
IILLow-level input current
B0
B7
V
MAX, V
75V
100µA
CCH
Su ly current (total)
mA
CCH
Su ly current (total)
mA
3.3V BTL 8-bit latched/registered/pass-thru
FBL2033
universal transceiver
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
p
I
OFF
High level output current B0 – B7 VCC = MAX, VIL = MAX, VOH = 1.9V 100 µA
OH
p
–
VCC = 0V, VIL = MAX, VOH = 1.9V 100
VCC = 0V, VIL = MAX, VOH = 1.9V@85°C 300
VCC = MIN to MAX; IOH = -100µA
V
OH
-
voltage
p
AO0 – AO7
VCC = MIN; IOH = -8mA 2.4 V
VCC = MIN; IOH = -32mA 2.0 V
V
Low-level output voltage
OL
–
VCC = MIN; IOL = 16mA 0.4 V
VCC = MIN; IOL = 32mA 0.5 V
B0 – B7 VCC = MIN, IOL = 4mA 0.5
VCC = MIN, IOL = 100mA 0.75 1.0 1.20
V
Input clamp voltage VCC = MIN, II = I
IK
= –18mA –0.85 -1.2 V
IK
Control pins VCC = 3.6V; VI = VCC or 300mV ±1.0
I
Input leakage current
I
Control/
AI0 – AI7
AI0 – AI7 VCC = 3.6V; VI = V
VCC = 0V or 3.6V; VI = 5.5V 10
CC
Note 4 VCC = 3.6V; VI = 300mV –5
=
CC
I
IH
High-level input current B0 – B7 VCC = MAX, VI = 3.5V , note 5 100
= 1.
I
VCC = MAX, VI = 3.75V, Note 5 @ –40°C 100
p
I
OZH
I
OZL
I
CCH
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
Off-state output current AO0 – AO7 VCC = MAX, VO =3V 5 µA
Off-state output current AO0 – AO7 VCC = MAX, VO = 0.5V -5 µA
pp
Supply current VCC = MAX 22 55 mA
pp
Supply current VCC = MAX 14 33 mA
–
CC
=
= 0.
I
VCC = MAX, outputs High 14 31
B→A VCC = MAX, outputs Low 17 38
VCC = MAX, outputs High 14 32
A→B VCC = MAX, outputs Low 9 18
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V
3. Due to test equipment limitations, actual test conditions are V
4. Unused pins are at V
5. For B port input voltage between 3 and 5 volt; I
is active).
= 3.3V, TA = 25°C.
CC
or GND.
CC
= 1.8V and VIL = 1.3V for the B side.
IH
will be greater than 100mA but the part will continue to function normally (clamping circuit
IH
limits
min typ2max
V
CC
–0.2
-
u
µ
V
A
1
1999 Apr 15
7
Page 8
Philips Semiconductors Product specification
3.3V BTL 8-bit latched/registered/pass-thru
FBL2033
universal transceiver
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX MIN MAX UNIT
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
SYMBOL PARAMETER TEST CONDITION
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Propagation delay,
An to Bn through latch
Propagation delay,
An to Bn transparent latch
Propagation delay,
LCAB to B
n latch
Propagation delay,
LCAB to Bn register
Propagation delay,
SABX to Bn inverting
Propagation delay,
SABX to Bn non-inverting
OEBn to Bn
Propagation delay,
An to Bn through latch
Propagation delay,
An to B
n transparent latch
Propagation delay,
LCAB to Bn latch
Propagation delay,
LCAB to Bn register
Propagation delay,
SABX to Bn inverting
Propagation delay,
SABX to Bn non-inverting
OEBn to Bn
1.2
1.2
1.3
1.8
2.0
2.3
2.1
2.0
1.2
2.3
1.8
1.8
1.5
1.6
T
amb
2.7
2.6
3.2
3.7
3.8
4.3
3.8
4.3
4.3
5.1
4.0
5.0
3.4
3.4
4.8
4.3
5.2
5.6
5.8
6.3
5.7
6.5
7.6
8.0
6.4
8.5
5.4
5.3
= +25°C, VCC = 3.3V,
RL = 16.5Ω
1.0
1.0
1.0
1.6
1.2
1.8
1.4
1.8
1.0
2.0
1.1
1.6
1.0
1.0
T
= –40 to +85°C,
amb
V
= 3.3V±10%,
CC
= 16.5Ω
R
L
5.3
4.9
6.1
6.3
7.0
7.3
6.9
7.3
9.2
8.7
8.0
9.8
6.0
7.2
MIN TYP MAX MIN MAX
1.2
1.2
1.4
1.7
2.0
2.2
2.0
2.2
1.2
1.8
1.3
1.5
1.5
1.5
2.8
2.4
3.2
3.5
3.8
4.1
3.9
4.1
4.6
4.7
4.5
4.6
3.4
3.2
4.5
4.0
5.1
5.4
5.6
6.1
5.9
6.1
8.6
7.9
8.2
8.2
6.0
7.2
1.0
1.0
1.0
1.3
1.3
1.6
1.2
1.6
1.0
1.6
1.0
1.2
1.0
1.0
5.7
4.6
6.1
5.9
6.9
7.0
7.7
7.0
10.4
8.7
10.0
9.1
6.3
7.0
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
1999 Apr 15
8
Page 9
Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITION
UNIT
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (B TO A)
T
= +25°C, VCC = 3.3V
SYMBOL PARAMETER TEST CONDITION
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PHZ
t
PZH
t
PHZ
Propagation delay,
B
n to An through mode
Propagation delay,
Bn to An transparent latch
Propagation delay,
LCAB to An latch
Propagation delay,
LCAB to An register
Propagation delay,
SABX to An inverting
Propagation delay,
SABX to An non-inverting
Propagation delay,
AIn to AOn loopback
Propagation delay,
LPBK to An non-inverting or inverting
Propagation delay,
OEA to An
Propagation delay,
OEA to An
amb
MIN TYP MAX MIN MAX
2.5
3.0
3.4
3.2
2.1
1.6
1.9
2.3
2.3
2.5
1.4
1.9
2.4
2.3
2.0
1.3
2.4
3.1
2.1
1.4
4.5
5.1
5.4
5.4
3.9
3.3
3.7
4.1
4.2
4.5
3.9
4.0
4.3
4.4
4.3
4.9
4.3
5.3
4.0
2.7
6.5
7.3
7.6
7.6
5.8
5.0
5.7
6.0
6.4
6.5
8.7
6.1
6.3
6.6
7.0
9.4
6.3
7.6
6.2
4.4
T
= –40 to +85°C,
amb
VCC = 3.3V±10%
1.6
2.6
2.2
2.7
1.3
1.2
1.1
1.8
1.3
2.0
1.0
1.5
1.6
1.6
1.4
1.5
1.9
2.5
1.7
1.0
FBL2033
UNIT
7.8
9.1
9.2
9.3
7.2
5.9
6.8
7.0
7.9
7.4
9.8
7.1
8.1
7.6
8.9
11.3
7.3
8.9
6.9
5.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1999 Apr 15
9
Page 10
Philips Semiconductors Product specification
CONDITION
CONDITION
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
AC SETUP REQUIREMENTS INDUSTRIAL AND COMMERCIAL
SYMBOL PARAMETER
ts(H)
ts(L)
th(H)
th(L)
th(H)
th(L)
th(H)
th(L)
th(H)
th(L)
tw(H)
t
(L)
w
Setup time
AIn to LCAB or Bn to LCBA
Hold time (latch mode)
AIn to LCAB
Hold time (register mode)
AIn to LCAB
Hold time (latch mode)
Bn to LCAB
Hold time (register mode)
Bn to LCAB
Pulse width, High or Low
AIn to LCAB or B
n to LCBA
TEST
LIMITS
T
= –40 to +85°C,
T
= +25°C, V
amb
= 3.3V
CL = 50pF (A side) / CD = 30pF (B side)
RL = 500Ω (A side) / RU = 9Ω (B side)
MIN MIN
3.0
3.0
6.0
5.0
1.0
1.0
1.5
1.5
1.0
1.0
3.0
3.0
CC
amb
V
= 3.3V±10%
CC
4.0
4.0
6.5
5.5
1.3
1.3
2.0
2.0
1.3
1.3
4.0
4.0
FBL2033
UNIT
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS INDUSTRIAL AND COMMERCIAL
SYMBOL PARAMETER
ts(H)
ts(L)
th(H)
th(L)
th(H)
th(L)
th(H)
th(L)
th(H)
th(L)
tw(H)
t
(L)
w
Setup time
AIn to LCAB or Bn to LCBA
Hold time (latch mode)
AIn to LCAB
Hold time (register mode)
AIn to LCAB
Hold time (latch mode)
Bn to LCAB
Hold time (register mode)
Bn to LCAB
Pulse width, High or Low
AIn to LCAB or B
n to LCBA
TEST
LIMITS
T
= –40 to +85°C,
T
= +25°C, V
amb
= 3.3V
CL = 50pF (A side) / CD = 30pF (B side)
RL = 500Ω (A side) / RU = 16.5Ω (B side)
MIN MIN
3.0
3.0
6.0
5.0
1.0
1.0
1.5
1.5
1.0
1.0
3.0
3.0
CC
amb
V
= 3.3V±10%
CC
4.0
4.0
6.5
5.5
1.3
1.3
2.0
2.0
1.3
1.3
4.0
4.0
UNIT
ns
ns
ns
ns
ns
ns
1999 Apr 15
10
Page 11
Philips Semiconductors Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
AC WAVEFORMS
Input
Output
V
M
t
PLH
Waveform 1. Propagation Delay for Data
or Output Enable to Output
AIn, Bn
AOn, Bn
V
M
tSK(o)
Waveform 3. Output to Output Skew
OEA
AOn
V
M
t
PZH
V
M
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
V
M
t
PHL
V
M
V
M
V
M
t
PHZ
V
M
VOH -0.3V
OV
FBL2033
Input
Output
V
M
t
PHL
Waveform 2. Propagation Delay for Data
or Output Enable to Output
V
AIn, Bn
LCAB, LCBA
M
t
t
s
h
V
M
t
(H)
w
Waveform 4. Setup and Hold Times,
Pulse Widths and Maximum Frequency
V
OEA
AOn
M
t
PZL
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
V
M
t
PLH
V
M
t
1/f
MAX
V
M
t
PLZ
V
M
w
tst
(L)
V
M
h
V
M
VOL +0.3V
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
SG00070
1999 Apr 15
11
Page 12
Philips Semiconductors Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
TEST CIRCUIT AND WAVEFORMS
V
CC
7.0V
NEGATIVE
PULSE
POSITIVE
PULSE
Family
FB+
A Port
DEFINITIONS:
RL= Load Resistor; see AC CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
CD= Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
RU= Pull up resistor; see AC CHARACTERISTICS for value.
PULSE
GENERATOR
V
IN
R
T
D.U.T.
V
OUT
Test Circuit for 3-State Outputs on A Port
SWITCH POSITION
TEST SWITCH
t
PLZ,
All other
PULSE
GENERATOR
t
PZL
V
IN
Test Circuit for Outputs on B Port
BIAS
V
R
closed
open
D.U.T.
T
V
CC
V
OUT
R
L
R
C
L
L
2.0V (for RU = 9 Ω)
2.1V (for RU = 16.5 Ω)
R
U
C
D
90%
10%
t
W
V
M
10%
(tf)
t
THL
t
(tr)
TLH
90%
V
M
t
W
VM = 1.55V for Bn, VM = 1.5V for all others.
10%
90%
V
M
V
Input Pulse Definitions
INPUT PULSE REQUIREMENTS
Low V
0.0V
1.0VB Port
Rep. RateAmplitude t
1MHz3.0V
1MHz2.0V
t
W
500ns
of pulse generators.
OUT
FBL2033
90%
M
10%
TLHtTHL
2.5ns
2.0ns500ns
t
TLH
t
THL
AMP (V)
LOW V
(tr)
(tf)
AMP (V)
LOW V
2.5ns
2.0ns
SG00063
1999 Apr 15
12
Page 13
Philips Semiconductors Product specification
3.3V BTL 8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm SOT379-1
FBL2033
1999 Apr 15
13
Page 14
Philips Semiconductors Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
FBL2033
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 07-98
Document order number: 9397-750–05517
yyyy mmm dd
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