Datasheet FB2040BB Datasheet (Philips)

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INTEGRATED CIRCUITS

FB2040A

8-bit Futurebus+ transceiver

Product specification IC19 Data Handbook

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1995 May 25

Page 2

Philips Semiconductors Product specification

Input voltage

FB2040A8-bit Futurebus+ transceiver

FEA TURES

•8-bit BTL transceivers

•Separate I/O on TTL A-port

•Inverting

•Drives heavily loaded backplanes with equivalent load

impedances down to 10Ω.

•High drive 100mA BTL open collector drivers on B-port

•Allows incident wave switching in heavily loaded backplane buses

•Reduced BTL voltage swing produces less noise and reduces

power consumption

•Built-in precision band-gap reference provides accurate receiver

thresholds and improved noise immunity

QUICK REFERENCE DATA

SYMBOL PARAMETER TYPICAL UNIT

PLH

PHL

PLH

PHL

Propagation delay AIn to Bn

Propagation delay Bn to AOn

Output capacitance (B0 – B7 only) 4 pF Output current (B0 – B7 only) 100 mA

Supply current

•Compatible with IEEE Futurebus+ or proprietary BTL backplanes

•Controlled output ramp and multiple GND pins minimize ground

bounce

•Each BTL driver has a dedicated Bus GND for a signal return

•Glitch-free power up/power down operation

•Low I

current

•Tight output skew

•Supports live insertion

•Pins for the optional JTAG boundary scan function are provided

•High density packaging in plastic Quad Flat Pack

Standby 4

AIn to Bn

(outputs Low or High)

Bn to AOn

(outputs Low)

Bn to AOn

(outputs High)

4.4

3.1

3.4

3.2

ORDERING INFORMATION

PACKAGES

52-pin Plastic Quad Flat Pack (QFP) FB2040BB SOT379-1

COMMERCIAL RANGE

VCC = 5V±10%; T

= 0°C to +70°C

amb

DRAWING

NUMBER

ABSOLUTE MAXIMUM RATINGS

Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.

SYMBOL

OUT

amb

STG

Supply voltage -0.5 to +7.0 V

Input current -18 to +5.0 mA Voltage applied to output in High output state -0.5 to +V

Current applied to output in Low output state

Operating free-air temperature range -40 to ++85 °C Storage temperature -65 to +150 °C

PARAMETER RATING UNIT

AI0 – AI7, OEB0, OEB1, OEA -1.2 to +7.0

B0 – B7 -1.2 to +5.5

A0 – A7 48 B0 – B7 200

1995 May 25 853-1801 15279

Page 3

Philips Semiconductors Product specification

FB2040A8-bit Futurebus+ transceiver

PIN CONFIGURATION

LOGIC V

AI0

AO1

AO0

52 51 50 49 48 47 46 45 44 43 42 41 40

LOGIC GND

AI1

AI2

AO2

AO3

AI3

AI4

AO4

AO5

1 2 3 4 5 6 7

9 10 11 12 13

14 15 16 17 18 19 20 21 22 23 24 25 26

AI5

8-Bit Transceiver

52-lead PQFP

AO6

BG V

LOGIC GND

DESCRIPTION

The FB2040A is an 8-bit bidirectional BTL transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The FB2040A is an inverting transceiver.

The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V .

The B-port interfaces to “Backplane Transceiver Logic” (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes.

The A-port operates at TTL levels with separate I/O. The 3-state A-port drivers are enabled when OEA goes High after an extra 6ns delay which is built in to provide a break-before-make function. When OEA goes Low, A-port drivers become High impedance without any extra delay. During power on/of f cycles, the A-port drivers are held in a High impedance state when V

The B-port has two output enables, OEB0 and OEB1 is High and OEB1

is Low the output is enabled. When OEB0 is Low

is below 2.5V.

. When OEB0

TMS (option)

OEB0

OEB1

AO7

TDO (option)

or if OEB1

TCK (option)

BUS V

TDI (option)

AI7

B0/B0

BUS GND

39 38 37 36 35 34 33

32 31 30 29 28 27

BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND

SG00076

is High, the B-port is inactive and is at the level of the

OEA

BIAS V

FB2040A

AI6

BG GND

backplane signal. To support live insertion, OEB0 is held Low during power on/off

cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while V BIAS V pin should be tied to a V

is Low. If live insertion is not a requirement, the

pin.

The LOGIC GND and BUS GND pins are isolated in the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package.

Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble-shoot.

The LOGIC V

and BUS VCC pins are also isolated internally to

minimize noise and may be externally decoupled separately or simply tied together.

JTAG boundary scan pins are provided with signals TMS, TCK, TDI and TDO. TMS and TCK are no-connects (no bond wires) and TDI and TDO are shorted together internally. Boundary scan functionality is not implemented at this time.

1995 May 25

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Philips Semiconductors Product specification

MODE

AIn to Bn

Disable Bn out uts

Bn to AOn

FB2040A8-bit Futurebus+ transceiver

PIN DESCRIPTION

SYMBOL PIN NUMBER TYPE NAME AND FUNCTION

AI0 – AI7 51, 2, 3, 8, 9, 14, 18, 24 Input Data inputs (TTL)

AO0 – AO7 50, 52, 4, 6, 10, 12, 16, 20 Output 3-state outputs (TTL)

B0 – B7

OEB0 46 Input Enables the B outputs when High OEB1 45 Input Enables the B outputs when Low

OEA 47 Input Enables the A outputs when High

BUS GND 41, 39, 37, 35, 33, 31, 29, 27 GND Bus ground (0V)

LOGIC GND 1, 5, 7, 11, 13, 15 GND Logic ground (0V)

BUS V

LOGIC V

BG V

BG GND 19 GND Band Gap threshold voltage reference ground

BIAS V 48 Power Live insertion pre-bias pin

TMS 42 Input Test Mode Select (optional, if not implemented then no-connect) TCK 44 Input Test Clock (optional, if not implemented then no-connect)

TDI 22 Input Test Data In (optional, if not implemented then shorted to TDO)

TDO 21 Output Test Data Out (optional, if not implemented then shorted to TDI)

NC 25 NC No Connect

40, 38, 36, 34,

32, 30, 28, 26

23, 43 Power Positive supply voltage

49 Power Positive supply voltage 17 Power Band Gap threshold voltage reference

I/O Data inputs/Open Collector outputs. High current drive (BTL)

FUNCTION TABLE

INPUTS OUTPUTS

AIn Bn* OEB0 OEB1 OEA AOn Bn*

L — H L L Z H**

H — H L L Z L

L — H L H L H**

H — H L H H L

Disable AOn outputs — X X X L Z X

H** = Goes to level of pull-up voltage B* = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.

X X L X X X H** X X X H X X H** X L L X H H Input X H X H H L Input X L X H H H Input X H L X H L Input

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Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

High-level in ut voltage

Low-level in ut voltage

Low-level out ut current

FB2040A8-bit Futurebus+ transceiver

RECOMMENDED OPERATING CONDITIONS

LIMITS

MIN NOM MAX

amb

Supply voltage 4.5 5.0 5.5 V

Except B0–B7 2.0 B0 – B7 1.62 1.55 Except B0–B7 0.8

B0 – B7 1.47 Input clamp current -18 mA High-level output current AO0 – AO7 -3 mA

AO0 – AO7 24

B0 – B7 100 Output capacitance on B port 5 pF Operating free-air temperature range 0 +70 °C

1995 May 25

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Philips Semiconductors Product specification

FB2040A8-bit Futurebus+ transceiver

LOGIC DIAGRAM FOR FB2040

OEB0

OEB1

OEA

AI0

AO0

AI1

AO1

AI2

AO2

TTL

Levels

AO3

AO4

AO5

AO6

AO7

TMS TCK

TDI

TDO

AI3

AI4

AI5

AI6

AI7

42 44

(Future JTAG Boundary Scan option)

22 21

BTL

Levels

NC = 25 LOGIC V LOGIC GND = 1, 5, 7, 11, 13, 15 BUS V BUS GND = 27, 29, 31, 33, 35, 37, 39, 41

BIAS V = 48 BG V BG GND = 19

=49

= 23, 43

=17

1995 May 25

SG00077

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Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

IIHHigh level in ut current

µA µ

IILLow level in ut current

µA

FB2040A8-bit Futurebus+ transceiver

DC ELECTRICAL CHARACTERISTICS

Over recommended operating free-air temperature range unless otherwise noted.

LIMITS

MIN TYP2MAX

OFF

OZH

OZL

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.

2. All typical values are at V

3. Due to test equipment limitations, actual test conditions are V

4. Not more than one output should be shorted at a time. For testing I techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I

High level output current B0 – B7 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA Power-off output current B0 – B7 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA High-level output voltage AO0 – AO73VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA 2.5 2.85 V

AO0 – AO73VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA 0.33 0.5

Low-level output voltage

Input clamp voltage VCC = MIN, II = I

Input current at maximum

input voltage

–

OEB0, OEB1, OEA, AI0–AI7

OEB0, OEB1,

High-level input current

OEA, AI0–AI7

VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA .75 1.0 1.10 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA 1.15

VCC = MAX, VI = GND or 5.5V ±50 µA

VCC = MAX, VI = 2.7V 20

B0 – B7 VCC = MAX, VI = 2.1V 100

Low-level input current

OEB0, OEB1, OEA, AI0–AI7

VCC = MAX, VI = 0.5V -20

B0 – B7 VCC = MAX, VI = 0.75V -100 Off-state output current AO0 – AO7 VCC = MAX, VO = 2.7V 50 µA Off-state output current AO0 – AO7 VCC = MAX, VO = 0.5V -50 µA Short-circuit output

current

Supply current (total)

= 5V, TA = 25°C.

AO0 – AO7

only

(standby) VCC = MAX 19 30

CCZ

AIn to

CCB,

Bn to

CCA,

AOn

Bn to

CCA,

AOn

should be performed last.

VCC = MAX, VO = 0.0V -30 -150 mA

VCC = MAX, outputs Low or High 40 60

VCC = MAX, outputs Low 22 35

VCC = MAX, outputs High 19 35

= 1.8V and VIL = 1.3V for the B side.

, the use of high-speed test apparatus and/or sample-and-hold

-1.2 V

1995 May 25

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Philips Semiconductors Product specification

FB2040A8-bit Futurebus+ transceiver

AC ELECTRICAL CHARACTERISTICS

A PORT LIMITS

= 0 to 70°C,

= +25°C, VCC = 5V,

SYMBOL PARAMETER TEST CONDITION

amb

CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

PLH

PHL

PZH

PZL

PHZ

PLZ

TLH

THL

tSK(o)

Propagation delay, Bn to AOn

Output enable time, OEA to AOn

Output disable time, OEA to AOn

Transition time, AOn Port (10% to 90% or 90% to 10%)

Output skew between receivers in same package

Waveform 1, 2

Waveform 4, 5

Test Circuit and

Waveforms

1.8

1.6

1.0

1.5

3.4

3.2

3.3

2.2

2.4

5.0

4.9

5.0

4.8

5.4

3.5

Waveform 3 0.4 1.0 1.0 ns

B PORT LIMITS

SYMBOL PARAMETER

PLH

PHL

PLH

PHL

PLH

PHL

TLH

THL

tSK(o)

Propagation delay, AIn to Bn

Enable/disable time, OEB0 to Bn

Enable/disable time, OEB1 to Bn

Transition time, Bn Port (1.3V to 1.8V)

Output skew between drivers in same package

TEST CONDITION

Waveform 1, 2

Waveform 2

Waveform 1

Test Circuit and

Waveforms

Waveform 3 0.3 1.0 1.0 ns

= +25°C, VCC = 5V,

amb

CD = 30pF, RU = 9Ω

2.9

1.6

2.9

1.9

3.0

1.7

1.0

0.5

4.4

3.3

4.7

3.5

5.3

3.2

1.4

1.1

5.0

4.8

5.9

5.1

6.3

4.8

3.0

SYMBOL PARAMETER TEST CONDITION RU = 16.5Ω RU = 16.5Ω UNIT

PLH

PHL

PLH

PHL

PLH

PHL

TLH

THL

tSK(o)

Propagation delay, AIn to Bn

Enable/disable time, OEB0 to Bn

Enable/disable time, OEB1 to Bn

Transition time, Bn Port (1.3V to 1.8V)

Output skew between drivers in same package

Waveform 1, 2

Waveform 2

Waveform 1

Test Circuit and

Waveforms

3.0

1.7

3.0

2.0

3.1

1.8

1.0

0.5

4.5

3.3

4.8

3.5

5.4

3.3

1.5

1.1

6.4

4.8

6.0

5.2

6.4

4.9

3.0

Waveform 3 0.3 1.0 1.0 ns

NOTES:

actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or

1.  t

HL. Skew times are valid only under same test conditions (temperature, V

, loading, etc.).

amb

VCC = 5V±10%,

= 50pF, RL = 500Ω

1.6

1.5

1.2

1.3

1.0

= 0 to 70°C,

amb

VCC = 5V±10%,

= 30pF, RU = 9Ω

2.3

1.5

2.6

1.8

2.7

1.5

1.0

0.5

2.3

1.6

2.7

1.9

2.8

1.6

1.0

0.5

5.6

5.3

5.5

5.0

5.9

4.5

5.5

5.1

7.8

5.7

8.0

5.7

3.0

6.9

5.1

7.9

5.7

8.1

5.7

3.0

UNIT

1995 May 25

Page 9

Philips Semiconductors Product specification

FB2040A8-bit Futurebus+ transceiver

AC WAVEFORMS

AIn, Bn

OEB1

AOn, Bn

PLH

PHL

Waveform 1. Propagation Delay for Data

or Output Enable to Output

AIn, Bn

AOn, Bn

Waveform 3. Output Skews

OEA

AOn

PZH

PHZ

VOH -0.3V

Waveform 4. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

NOTE: V

= 1.55V for Bn, V

tSK(o)

AIn, Bn

OEB0

AOn, Bn

PHL

PLH

Waveform 2. Propagation Delay for Data

or Output Enable to Output

OEA

AOn

PZL

PLZ

Waveform 5. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

= 1.5V for all others.

VOL +0.3V

SG00078

1995 May 25

Page 10

Philips Semiconductors Product specification

FB2040A8-bit Futurebus+ transceiver

TEST CIRCUIT AND WAVEFORMS

BIAS

PULSE

GENERATOR

D.U.T.

OUT

Test Circuit for 3-State Outputs on A Port

SWITCH POSITION

TEST SWITCH

PULSE

GENERATOR

PLZ,

PZL

All other

BIAS

D.U.T.

closed

open

OUT

2.0V (for RU = 9 Ω)

2.1V (for RU = 16.5 Ω)

7.0V NEGATIVE PULSE

POSITIVE PULSE

Family

FB+

A Port

90%

10%

(tf)

THL

(tr)

TLH

90%

VM = 1.55V for Bn, VM = 1.5V for all others.

10%

90%

Input Pulse Definitions

INPUT PULSE REQUIREMENTS

Low V

0.0V

1.0VB Port

Rep. RateAmplitude t

1MHz3.0V 1MHz2.0V

500ns

2.5ns

2.5ns500ns

TLH

THL

LOW V

(tr)

(tf)

LOW V

90%

10%

TLHtTHL

2.5ns

Test Circuit for Outputs on B Port

DEFINITIONS:

RL= Load Resistor; see AC CHARACTERISTICS for value. CL= Load capacitance includes jig and probe capacitance; see AC

CHARACTERISTICS for value.

= Termination resistance should be equal to Z

CD= Load capacitance includes jig and probe capacitance; see AC

of pulse generators.

OUT

CHARACTERISTICS for value.

RU= Pull up resistor; see AC CHARACTERISTICS for value.

SG00059

1995 May 25

Page 11

Philips Semiconductors Product specification

FB2040A8-bit Futurebus+ transceiver

QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm SOT379-1

1995 May 25

Page 12

Philips Semiconductors Product specification

FB2040A8-bit Futurebus+ transceiver

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 08-98 Document order number:

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1995 May 25