Datasheet FB2033BB Datasheet (Philips)

INTEGRATED CIRCUITS

FB2033

8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

Product specification IC19 Data Handbook

 

1995 May 25

Philips Semiconductors Product specification

I

S

t

A

8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

FEA TURES

•8-bit transceivers

•Latched, registered or straight through in either A to B or B to A

path

•Drives heavily loaded backplanes with equivalent load

impedances down to 10Ω.

•High drive 100mA BTL Open Collector drivers on B-port

•Allows incident wave switching in heavily loaded backplane buses

•Reduced BTL voltage swing produces less noise and reduces

power consumption

QUICK REFERENCE DATA

SYMBOL PARAMETER TYPICAL UNIT

t

PLH

t

PHL

t

PLH

t

PHL

C

I

OB

OL

CC

Propagation delay AIn to Bn

Propagation delay Bn to AOn

Output capacitance (B0 – Bn only) 6 pF Output current (B0 – Bn only) 100 mA

AIn to Bn

upply curren

(outputs Low or High) Bn to AOn (outputs Low) 45 Bn to AOn (outputs High) 22

FB2033

•Built-in precision band-gap reference provides accurate receiver

thresholds and improved noise immunity

•Compatible with IEEE Futurebus+ or proprietary BTL backplanes

•Each BTL driver has a dedicated Bus GND for a signal return

•Controlled output ramp and multiple GND pins minimize ground

bounce

•Glitch-free power up/power down operation

•Low I

•Tight output skew

•Supports live insertion

current

CC

3.0

4.3

4.1

24

ns

m

ORDERING INFORMATION

PACKAGES

52-pin Plastic Quad Flat Pack (QFP) FB2033BB SOT379-1

NOTE: Thermal mounting or forced air is recommended

PIN CONFIGURATION

52 51 50 49 48 47 46 45 44 43 42 41 40

LOGIC GND

LOOPBACK

LOGIC GND

AO1

AI2

AO2

AI3

AO3

AI4

AO4

AI5

AO5

AI6

1 2 3 4 5 6 7

8

9 10 11 12 13

14 15 16 17 18 19 20 21 22 23 24 25 26

COMMERCIAL RANGE

VCC = 5V±10%; T

AO0

LOGIC GND

AI0

LCAB

SBA1

AI1

CC

V

8-Bit Universal Transceiver

FB2033

52-lead PQFP

AO7

LGOIC GND

CC

V

SAB0

LCBA

AO6

AI7

SBA0

SAB1

CC

BG V

CC

V

= 0°C to +70°C

amb

OEA

BIAS V

BG GND

OEB0

OEB1

BUS GND

B0

B7

39 38 37 36 35 34 33

32 31 30 29 28 27

DRAWING

NUMBER

BUS GND B1 BUS GND B2 BUS GND B3

BUS GND B4 BUS GND B5 BUS GND

B6 BUS GND

SG00068

1995 May 25 853-1717 15279

2

Philips Semiconductors Product specification

8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

DESCRIPTION

The FB2033 is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level side.

The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two pairs of mode select inputs (SBA0 and SBA1 for B-to-A, SAB0 and SAB1 for A-to-B). It can be configured as a buffer, a register, or a D-type latch.

When configured in the buffer mode, the inverse of the input data appears at the output port. In the flip-flop mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-High latch enables. Regardless of the mode, data is inverted from input to output.

Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the Loopback input. When the Loopback input is High the output of the selected A-to-B logic element (not inverted) becomes the B-to-A input.

The 3-State AO port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1 OEB0 is High and OEB1 OEB0 is Low or OEB1 the level of the pull-up voltage. New data can be entered in the flip-flop and latched modes or can be retained while the associated outputs are in 3-State (AO port) or inactive (B port).

The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port ensure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V .

The B-port interfaces to “Backplane Transceiver Logic” (see the IEEE 1194.1 BTL standard). BTL features low power consumption

is Low is the output enabled. When either

is High, the B-port is inactive and is pulled to

. Only when

FB2033

by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes.

Output clamps are provided on the BTL outputs to further reduce switching noise. The “V during a Low-to-High transition. The “V The other clamp, the “trapped reflection” clamp, clamps out ringing below the BTL 0.5V V approximately 100ns after a High-to-Low transition.

To support live insertion, OEB0 is held Low during power on/off cycles to ensure glitch- free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while V which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and

2.1V. This bias function is in accordance with IEEE BTL Standard

1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a V

The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package.

Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble- shoot.

As with any high power device thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature.

CC

pin.

” clamp reduces inductive ringing effects

OH

level. This clamp remains active for

OL

is Low. The BIAS V pin is a low current input

” clamp is always active.

OH

PIN DESCRIPTION

SYMBOL PIN NUMBER TYPE NAME AND FUNCTION

AI0 – AI7 50, 52, 3, 5, 8, 10, 12, 15 Input Data inputs (TTL)

AO0 – AO7 51, 2, 4, 6, 9, 11, 14, 16 Output 3-State outputs (TTL)

B0 – B7 40, 38, 36, 34, 32, 30, 28, 26 I/O Data inputs/Open Collector outputs, High current drive (BTL)

OEB0 23 Input Enables the B outputs when High OEB1 24 Input Enables the B outputs when Low

OEA 43 Input Enables the AO outputs when High

BUS GND 39, 37, 35, 33, 31, 29, 27, 25 GND Bus ground (0V)

LOGIC GND 1, 13, 17, 49 GND Logic ground (0V)

V

CC

BIAS V 41 Power Live insertion pre-bias pin

BG V

CC

BG GND 42 GND Band Gap threshold voltage reference ground

SABn 20, 21 Input Mode select from AI to B SBAn 45, 46 Input Mode select from B to AO LCAB 47 Input A-to-B clock/latch enable (transparent latch when High) LCBA 19 Input B-to-A clock/latch enable (transparent latch when High)

Loopback 7 Input Enables loopback function when High (from AIn to AOn)

18, 22, 48 Power Positive supply voltage

44 Power Band Gap threshold voltage reference

1995 May 25

3

Philips Semiconductors Product specification

AIn to Bn thru mode

AIn to Bn transparent latch

AIn to Bn latch and read

AIn to Bn register

Bn to AOn thru mode

Bn to AOn transparent latch

Bn to AOn latch and read

Bn to AOn register

Disable Bn outputs

8-bit latched/registered/pass-thru

FB2033

Futurebus+ universal interface transceiver

FUNCTION TABLE

INPUTS OUTPUTS

MODE

p

Bn outputs latched and read (preconditioned latch)

p

AOn outputs latched and read (preconditioned latch)

p

Disable AOn outputs X X X X L X X XX XX Z X

AIn Bn* OEB0 OEB1 OEA LCAB LCBA

L — H L L X X LL XX Z H**

H — H L L X X LL XX Z L

L — H L L H X HX XX Z H**

H — H L L H X HX XX Z L

l — H L L ↓ X HX XX Z H** h — H L L ↓ X HX XX Z L L — H L L ↑ X LH XX Z H**

H — H L L ↑ X LH XX Z L X — H L L L X HX XX Z X L L H H X X XX LL H input

X H L H H X X XX LL L input X L L H H X H XX HX H input X H L H H X H XX HX L input X l L H H X ↓ XX HX H input X h L H H X ↓ XX HX L input X L L H H X ↑ XX LH H input X H L H H X ↑ XX LH L input

X X L H H X L XX HX X X L X X X X XX XX X H**

X X X H X X X XX XX X H**

SAB

0

SBA

1

0

AOn Bn

latched

data

latched

data

X

FUNCTION SELECT TABLE

NOTES:

H = High voltage level L = Low voltage level h = High voltage level one set-up time prior to the High-to-Low LCXX transition l = Low voltage level one set-up time prior to the High-to-Low LCXX transition X = Don’t care Z = High-impedance (OFF) state — = Input not externally driven

↑ = Low-to-High transition ↓ = High-to-Low transition

H** = Goes to level of pull-up voltage

* = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.

Bn NOTE: In Loopback mode (Loopback = High), AIn inputs are routed to the AOn outputs. The Bn

1995 May 25

MODE SELECTED SXX1 SXX0

Thru mode L L Register mode L H Latch mode H X

inputs are blocked out.

4

Philips Semiconductors Product specification

8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

LOGIC DIAGRAM

23

OEB0

24

OEB1

20

SAB0

21

SAB1

47

LCAB

50

AIn

LCBA

SBA0 SBA1

OEA

52, 2, 5, 8, 10, 12, 15

1 of 8 cells

19

45 46

43

D En

D Clk

40

36, 34, 32, 30,

FB2033

Bn

38,

28, 26

AOn

2, 4, 6, 9, 11, 14, 16

Loopback

51

7

1 of 8 cells

D

En

D

Clk

BGGnd

BGref

42

SG00069

1995 May 25

5

Philips Semiconductors Product specification

V

Input voltage

V

I

Current applied to output in Low output state

mA

SYMBOL

PARAMETER

UNIT

V

High-level input voltage

V

Low-level input voltage

V

I

Input clamp current

mA

I

Low-level output current

mA

8-bit latched/registered/pass-thru

FB2033

Futurebus+ universal interface transceiver

ABSOLUTE MAXIMUM RATINGS

Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.

SYMBOL

V

T

V

I

OUT

STG

CC

IN

Supply voltage -0.5 to +7.0 V

p

Input current -40 to +5.0 mA Voltage applied to output in High output state -0.5 to +V

pp

p

Storage temperature -65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

T

V

I

C

CC

IH

IL

IK

OH

OL

I

IA

OB

amb

Supply voltage 4.5 5.0 5.5 V

p

High-level output current AO0 – AOn -3 mA

p

Off device input current Output capacitance of B port 6 7 pF

Operating free-air temperature range 0 +70 °C

PARAMETER RATING UNIT

All inputs except B0 – Bn -1.2 to +7.0 B0 – Bn -1.2 to +3.5

CC

p

AO0 – AOn 48 B0 – Bn 200

LIMITS

MIN NOM MAX

Except B0 – Bn 2.0 B0 – Bn 1.62 1.55 Except B0 – Bn 0.8 B0 – Bn 1.47 Except B0 – Bn -40 B0 – Bn -50

AO0 – AOn 24 B0 – Bn 100 Except B0 – Bn,

V

= 0 to 5.5V, VCC = 0V

I

100 µA

V

1995 May 25

6

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITIONS

1

UNIT

B0

Bn

B0

Bn

µ

µA

B0

Bn

µ

IILLow level in ut current

µA

8-bit latched/registered/pass-thru

FB2033

Futurebus+ universal interface transceiver

DC ELECTRICAL CHARACTERISTICS

Over recommended operating free-air temperature range unless otherwise noted.

LIMITS

MIN TYP2MAX

I

OFF

V

I

OZH

I

OZL

I

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.

4. Due to test equipment limitations, actual test conditions are V

5. For B port input voltage between 3 and 5 volts I

6. B0

High level output current B0 – Bn VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA

OH

Power-off output current B0 – Bn VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V 100 µA High-level output voltage AO0 – AOn 4VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA 2.5 2.85 V

OH

AO0 – AOn 4VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA 0.5

Low-level output voltage

OL

Input clamp voltage

IK

Input current at maximum

I

input voltage

High-level input current

IH

Low-level input current

–

Except B0–Bn

–

Except B0–Bn

–

Except B0–Bn

VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA .75 1.0 1.15 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA 0.5

VCC = MIN, II = I VCC = MIN, II = I

IK

6

IK

0.3

VCC = MIN, II = -18mA -1.2 VCC = MAX, VI = 0.0V or 5.5V ±50 µA

VCC = MAX, VI = 2.7V, Bn = AIn = 0V 20 VCC = MAX, VI = 1.9V 100

VCC = MAX, VI = 3.5V

5

100 mA

VCC = MAX, VI = 0.5V -20

B0 – Bn VCC = MAX, VI = 0.75V -100 Off-state output current AO0 – AOn VCC = MAX, VO = 2.7V 50 µA Off-state output current AO0 – AOn VCC = MAX, VO = 0.5V -50 µA

OS

Short-circuit output

3

current

AO0 – AOn

only

VCC = MAX, VO = 0.0V -45 -150 mA

AIn to Bn VCC = MAX, outputs Low or High 24 50 Supply current (total)

CC

Bn to AOn VCC = MAX, outputs Low 45 75

Bn to AOn VCC = MAX, outputs High 22 44

= 5V, T

CC

– B7 clamps remain active for a minimum of 80ns following a High-to-Low transition.

amb

= 25°C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

= 1.8V and VIL = 1.3V for the B side.

will be greater than 100µA, but the parts will continue to function normally.

IH

V

-0.5 V

A

mA

1995 May 25

7

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

I

Bias pin DC current

IOLOFF

Power up current

A

8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

LIVE INSERTION SPECIFICA TIONS

V

BIASV

V

I I

HM

IBnPEAK

t

GR

Bias pin voltage VCC = 0 to 5.25V, Bn = 0 to 2.0V 4.5 5.5 V

VCC = 0 to 4.75V, Bn = 0 to 2.0V,

p

Bias V = 4.5 to 5.5V VCC = 4.5 to 5.5V, Bn = 0 to 2.0V,

Bias V = 4.5 to 5.5V

Bus voltage during pre-bias B0 – B8 = 0V, Bias V = 5.0V 1.62 2.1 V

Bn

Fall current during pre-bias B0 – B8 = 2V, Bias V = 4.5 to 5.5V 1 µA

LM

Rise current during pre-bias B0 – B8 = 1V, Bias V = 4.5 to 5.5V -1 µA Peak bus current during

insertion

p

VCC = 0 to 5.25V, B0 – B8 = 0 to 2.0V, Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns

V

= 0 to 5.25V, OEB0 = 0.8V 100

CC

V

= 0 to 2.2V, OEB0 = 0 to 5V 100

CC

Input glitch rejection VCC = 5.0V 1.0 1.35 ns

FB2033

LIMITS

MIN NOM MAX

1 mA

10 µA

10 mA

µ

AC ELECTRICAL CHARACTERISTICS

A PORT LIMITS

T

= 0 to 70°C,

SYMBOL PARAMETER

TEST

CONDITION

T

= +25°C, VCC = 5V,

amb

CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

TLH

t

THL

tSK(o) Output to output skew, A port tSK(p)

Maximum clock frequency Waveform 4 100 150 100 MHz Propagation delay (thru mode)

Bn to AOn Propagation delay (transparent latch)

Bn to AOn Propagation delay

LCBA to AOn Propagation delay

SBAn to AOn Propagation delay (Loopback mode)

AIn to AOn Propagation delay (Loopback mode)

Loopback to AOn Output enable time from High or Low

OEA to AOn Output disable time to High or Low

OEA to AOn Output transition time, AOn Port

10% to 90%, 90% to 10%

1

Pulse skew 2  t

– t

PLH



MAX

PHL

Waveform 1, 2

Waveform 5, 6

Test Circuit and

Waveforms

Waveform 3 0.5 1.0 1.5 ns Waveform 2 0.3 1.0 1.5 ns

2.2

2.0

1.5

2.4

2.0

2.2

1.4

2.0

1.2

1.0

2.6

1.0

4.3

4.1

4.5

4.4

3.8

4.3

2.9

3.1

3.8

3.9

3.4

3.2

3.1

4.0

3.5

3.3

6.0

6.5

5.5

6.0

5.0

5.5

6.0

5.0

5.5

5.1

5.5

5.0

4.6

NOTES:

1. Bn

to AOn propagation delays are extended for 5 nanoseconds following B port excursions above 3.1 volts.

actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL.

2.  t

PN

Skew times are valid only under same test conditions (temperature, V

(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

3. t

SK

duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

, loading, etc.).

CC

amb

VCC = 5V±10%,

CL = 50pF, RL = 500Ω

2.0

1.8

1.0

2.0

1.8

1.7

1.0

2.8

2.3

1.0

2.4

1.7

2.0

7.0

7.5

6.0

6.5

6.0

6.5

7.0

6.0

6.5

5.5

5.8

5.6

5.2

5.0

UNIT

ns

1995 May 25

8

Philips Semiconductors Product specification

8-bit latched/registered/pass-thru

FB2033

Futurebus+ universal interface transceiver

AC ELECTRICAL CHARACTERISTICS (Continued)

B PORT LIMITS

T

= 0 to 70°C,

SYMBOL PARAMETER

TEST

CONDITION

T

= +25°C, VCC = 5V,

amb

CD = 30pF, RU = 9Ω

MIN TYP MAX MIN MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

∆V/∆t tSK(o) Output to output skew, B port tSK(p)

Propagation delay (thru mode) AIn to Bn

Propagation delay (transparent latch) AIn to Bn

Propagation delay LCAB to Bn

Propagation delay SABn to Bn

Enable/disable time OEB0 or OEB1 to Bn

Output transition rate, Bn Port 20% to 80%, 80% to 20%

1

Pulse skew 2  t

– t

PLH



MAX

PHL

Waveform 1, 2

1.2

1.0

1.4

1.0

2.7

2.2

1.8

1.0

1.4

1.0

2.9

3.1

3.3

4.4

5.1

3.6

3.3

3.0

3.1

4.3

4.4

4.5

4.8

5.7

6.6

5.0

4.9

4.5

5.0

Test Circuit and

Waveforms

Waveform 3 0.8 1.5 2.0 ns Waveform 2 0.3 1.5 ns

SYMBOL PARAMETER TEST CONDITION RU = 16.5Ω RU = 16.5Ω UNIT

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

∆V/∆t tSK(o) Output to output skew, B port tSK(p)

Propagation delay (thru mode) AIn to Bn

Propagation delay (transparent latch) AIn to Bn

Propagation delay LCAB to Bn

Propagation delay SABn to Bn

Enable/disable time OEB0 or OEB1 to Bn

Output transition rate, Bn Port 20% to 80%, 80% to 20%

1

– t

PLH

2



MAX

Pulse skew  t

PHL

Waveform 1, 2

1.2

1.0

1.4

1.0

2.7

2.2

1.8

1.0

1.4

1.0

3.0

3.2

3.4

4.5

5.2

3.7

3.4

3.1

3.2

4.4

4.5

4.6

4.9

5.8

6.7

5.1

5.0

4.6

5.1

Test Circuit and

Waveforms

Waveform 3 0.5 1.0 1.5 ns Waveform 2 0.3 1.0 1.5 ns

NOTES:

actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or

1.  t

PN

HL. Skew times are valid only under same test conditions (temperature, V

(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

2. t

SK

duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

, loading, etc.).

CC

amb

VCC = 5V±10%,

CD = 30pF, RU = 9Ω

1.0

2.4

2.0

1.4

1.0

4.8

4.6

5.1

6.4

7.1

5.7

5.2

5.0

5.6

0.4 1.2 V/ns

1.0

2.4

2.0

1.4

1.0

4.9

4.7

5.2

6.5

7.2

5.8

5.3

5.1

5.7

0.2 0.6 V/ns

UNIT

ns

1995 May 25

9

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST

UNIT

8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

AC SETUP REQUIREMENTS

TEST

CONDITION

ts(H) ts(L)

th(H) th(L)

tw(H)

tw(L)

SYMBOL PARAMETER

ts(H) ts(L)

th(H) th(L)

tw(H)

tw(L)

Setup time AIn to LCAB or Bn to LCBA

Hold time AIn to LCAB or Bn to LCBA

Pulse width, High or Low LCAB or LCBA

Setup time AIn to LCAB or Bn to LCBA

Hold time AIn to LCAB or Bn to LCBA

Pulse width, High or Low LCAB or LCBA

Waveform 4

TEST

CONDITION

Waveform 4

FB2033

LIMITS

T

= 0 to 70°C,

T

= +25°C, VCC = 5V

amb

CL = 50pF (A side) / CD = 30pF (B side)

RL = 500Ω (A side) / RU = 9Ω (B side)

MIN TYP MAX MIN MAX

3.0

1.0

3.0

CL = 50pF (A side) / CD = 30pF (B side)

RL = 500Ω (A side) / RU = 16.5Ω (B side)

3.0

1.0

3.0

amb

VCC = 5V±10%

4.0

1.3

4.0

1.3

4.0

ns

UNIT

ns

AC WAVEFORMS

Input

Output

V

M

t

PLH

Waveform 1. Propagation Delay for Data

or Output Enable to Output

AIn, Bn

AOn, Bn

V

M

tSK(o)

Waveform 3. Output to Output Skew

OEA

AOn

V

M

t

PZH

V

M

Waveform 5. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

V

M

t

PHL

V

M

V

M

V

M

t

PHZ

V

M

VOH -0.3V

OV

Input

Output

V

M

t

PHL

V

M

t

PLH

V

M

V

M

Waveform 2. Propagation Delay for Data

or Output Enable to Output

V

AIn, Bn

LCAB, LCBA

M

t

s

h

V

M

t

(H)

w

1/f

MAX

tst

h

t

(L)

w

V

M

Waveform 4. Setup and Hold Times,

Pulse Widths and Maximum Frequency

OEA

AOn

V

M

t

PZL

V

M

t

PLZ

V

M

VOL +0.3V

Waveform 6. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

1995 May 25

NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.

SG00070

10

Philips Semiconductors Product specification

8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

TEST CIRCUIT AND WAVEFORMS

V

CC

7.0V NEGATIVE PULSE

POSITIVE PULSE

Family

FB+

A Port

DEFINITIONS:

RL= Load Resistor; see AC CHARACTERISTICS for value. CL= Load capacitance includes jig and probe capacitance; see AC

R

= Termination resistance should be equal to Z

T

CD= Load capacitance includes jig and probe capacitance; see AC RU= Pull up resistor; see AC CHARACTERISTICS for value.

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

Test Circuit for 3-State Outputs on A Port

SWITCH POSITION

TEST SWITCH

t

PLZ,

All other

PULSE

GENERATOR

t

PZL

V

IN

Test Circuit for Outputs on B Port

BIAS

V

R

T

closed

open

V

CC

D.U.T.

V

OUT

R

L

R

C

L

2.0V (for RU = 9 Ω)

2.1V (for RU = 16.5 Ω)

R

U

C

D

90%

V

M

10%

(tf)

t

THL

t

(tr)

TLH

90%

V

10%

M

VM = 1.55V for Bn, VM = 1.5V for all others.

Input Pulse Definitions

INPUT PULSE REQUIREMENTS

Low V

0.0V

1.0VB Port

CHARACTERISTICS for value.

t

W

V

M

10%

90%

V

M

t

W

Rep. RateAmplitude t

1MHz3.0V

t

W

500ns

1MHz2.0V

of pulse generators.

OUT

FB2033

90%

t

TLH

t

THL

10%

TLHtTHL

2.5ns

2.0ns500ns

2.5ns

2.0ns

AMP (V)

LOW V

(tr)

(tf)

AMP (V)

LOW V

SG00063

1995 May 25

11

Philips Semiconductors Product specification

8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm SOT379-1

FB2033

1995 May 25

12

Philips Semiconductors Product specification

8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

NOTES

FB2033

1995 May 25

13

Philips Semiconductors Product specification

8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

FB2033

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 08-98 Document order number:

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1995 May 25

14