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EMIF04-10006F1
®
January 2003 - Ed: 1
IEC 61000-4-2 level 4:
15kV (air discharge)
8 kV (contact discharge)
MIL STD 883E - Method 3015-6 Class 3
COMPLIES WITHTHE FOLLOWING STANDARDS :
Flip-Chip package
®
I3
O3
D1
D2
D3
Gnd Gnd Gnd
D4
I2
O2
I4
O4
I1
O1
987 654 321
A
B
C
PIN CONFIGURATION (ball side)
■ EMI symmetrical (I/O) low-pass filter
■ High efficiency in EMI filtering
■ Very lowPCB space consuming:
2.92mm x1.29mm
■
Very thin package: 0.65 mm
■
High efficiency in ESD suppression
(IEC61000-4-2 level 4)
■
High reliability offered by monolithic integration
■
High reducing of parasitic elements through
integration and wafer level packaging.
BENEFITS
4 LINES EMI FILTER
AND ESD PROTECTION
IPAD
TM
Where EMI filtering in ESD sensitive equipment is required:
■
Mobile phones and communication systems
■
Computers, printers and MCU Boards
MAIN PRODUCT CHARACTERISTICS
The EMIF04-10006F1 is a highly integrated devices
designed to suppress EMI/RFI noise in all systems
subjected to electromagnetic interferences. The
EMIF04 flip-chip packagingmeans the package size
is equal to the die size.
This filter includes an ESD protection circuitry which
preventsthe device from destruction whensubjected
to ESD surges up 15kV. This device includes four
EMIF filters and 4 separated ESD diodes.
DESCRIPTION
TM : IPAD is a trademark of STMicroelectronics.
Input 1
Input 2
Input 3
Output 1
Output 2
Output 3
GND
Input 4
D1
D3
Output 4
D2
D 4
Filtering cells: Ri/o = 100
Cline = 60pF
Ω
BASIC CELL CONFIGURATION
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Symbol Parameter and test conditions Value Unit
P
R
DC power per resistance
0.1 W
P
T
Total DC power per package
0.6 W
T
j
Maximum junction temperature
125 °C
T
op
Operating temperature range
-40 to + 85 °C
T
stg
Storage temperature range
125 °C
ABSOLUTE RATINGS (limiting values)
Symbol Parameter
V
BR
Breakdown voltage
I
RM
Leakage current @ V
RM
V
RM
Stand-off voltage
V
CL
Clamping voltage
R
d
Dynamic impedance
I
PP
Peak pulse current
R
I/O
Series resistance between Input
and Output
C
line
Input capacitance per line
ELECTRICAL CHARACTERISTICS (T
amb
=25°C)
I
V
I
F
VF
IRM
IR
IPP
VRMVBR
VCL
Symbol Test conditions Min. Typ. Max. Unit
V
BR
IR=1mA
5.5 7 9 V
I
RM
VRM= 3.3 V per line
500 nA
R
I/O
I=10mA
80 100 120 Ω
C
line
VR=2.5V,F=1MHz, 30 mV (on filter cells)
50 60 70 pF
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1M 3M 10M 30M 100M 300M 1G 3G
-50
-37.5
-25
-12.5
00
Aplac 7.62 User: ST Microelectronics
dB
1M 3M 10M 30M 100M 300M 1G 3G
-50
-37.5
-25
-12.5
00
Aplac 7.62 User: ST Microelectronics
dB
f/Hz
i3-o3-load
Simulation
Fig. 1: S21 (dB) attenuation measurements and
Aplac simulation.
Aplac 7.62 User: ST Microelectronics
100k
1M
10M 100M 1G
00
-25
-50
-75
-100
Aplac 7.62 User: ST Microelectronics
dBdB
i3_o2.s2p
f/Hz
Fig. 2: Analog crosstalk measurements.
Fig. 3: Digital crosstalk measurements. Fig. 4: ESD response to IEC61000-4-2 (+15kV air
discharge)on oneinput V(in)and oneoutputV(out).
Fig. 5: ESD response to IEC61000-4-2 (-15kV air
discharge)on oneinput V(in)and oneoutputV(out).
0
10
20
30
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V (V)
R
C(pF)
F=1MHz
V
osc
=30mV
RMS
Tj=25°C
Fig. 6: Line capacitanceversus applied voltagefor
filter.
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EMIF04-10006F1 model Ground return for each GND bump
Oi* = Output of each filter cell
Ii* = Input of each filter cell
Oi*
Cz=41pF@0V
Cz=41pF@0V
sub
Rs=100LbumpRbump
Rsub
Cbump
Ii*
Rsub
Lbump Rbump
Cbump
Di*
Cz=41pF@0V
Cz=41pF@0V
sub
LbumpRbump
Rsub
Cbump
Dj*
Rsub
Lbump Rbump
Cbump
With Dj* = D1 & D3
And Di* = D2 & D4
sub
Lbump
Rbump
sub
Rsub
Lgnd
Rgnd
CgndCgndCgnd
Aplac model
aplacvar Rs
100
aplacvar Cz
41 pF
aplacvar Lbump
50 pH
aplacvar Rbump
20 m
aplacvar Cbump
1.2 pF
aplacvar Rsub
100 m
aplacvar Rgnd
100 m
aplacvar Lgnd
100 pH
aplacvar Cgnd
0.15 pF
Aplac parameters
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EMIF yy xxx zz F 1-
EMI Filter
Number of lines
x: resistance value ( ) z:capacitance value / 10 (pF)
or
application (3 letters) and version (2 digits)
Ω
FLIP CHIP
Pitch = 500µm
Bump = 315µm
ORDER CODE
2.92mm ± 50µm
1.29mm ± 50µm
435µm ± 50
315µm ± 50
501µm ± 50
500µm ± 50
250µm ± 50
650µm ± 65
PACKAGE MECHANICAL DATA
545
545
400
100
230
x
y
x
wxw
Dot, ST logo
xxx = marking
yww = datecode
(y = year
ww = week)
All dimensions in µm
MARKING
Copper pad Diameter :
250µm recommended , 300µm max
Solder stencil opening : 330µm
Solder mask opening recommendation :
340µm min for 300µm copper pad diameter
FOOT PRINT RECOMMENDATIONS
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Informationfurnishedisbelievedtobe accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of
useofsuch information nor for any infringement of patents or other rights of third parties which may resultfrom its use. No license isgranted by
implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics - Printed in Italy - All rights reserved.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany
Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore
Spain - Sweden - Switzerland - United Kingdom - United States.
http://www.st.com
Note: More packing informations are available in the application note AN1235: ''Flip-Chip: Package description and
recommandations for use''
Dot identifying Pin A1 location
User direction of unreeling
All dimensions in mm
4 +/- 0.1
8 +/- 0.3
4 +/- 0.1
1.75 +/- 0.1 3.5 +/- 0.1
Ø 1.5 +/- 0.1
0.73 +/- 0.05
ST
xxx
yww
ST
xxx
yww
ST
xxx
yww
FLIP-CHIP TAPE AND REEL SPECIFICATION
Ordering code Marking Package Weight Base qty Delivery mode
EMIF04-10006F1 FST Flip-Chip 5.4 mg 5000 Tape & reel
OTHER INFORMATION
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