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IPAD™
Main product characteristics
Where EMI filtering in ESD sensitive equipment is
required:
■ Mobile phones and communication systems
■ Computers and printers and MCU Boards
Description
The EMIF02-SPK01C2 is a highly integrated
device designed to suppress EMI/RFI noise in all
systems subjected to electromagnetic
interference. The Flip-Chip packaging means the
package size is equal to the die size.
This filter includes ESD protection circuitry, which
prevents damage to the application when it is
subjected to ESD surges up to 15 kV.
EMIF02-SPK01C2
2 line EMI filter and ESD protection
Coated Flip-Chip package
(about 20 times real size)
Pin configuration (Bump side)
Benefits
■ EMI symmetrical (I/O) low-pass filter
■ High efficiency EMI filter (-33 dB @ 900 MHz)
■ Very low PCB space consumption:
1.07 mm x 1.47 mm
■ Very thin package: 0.695 mm
■ Coating resin on back side and lead free
package
■ High efficiency in ESD suppression
■ High reliability offered by monolithic integration
■ High reduction of parasitic elements through
integration and wafer level packaging.
132
I1
I2
GND
O2
O1
A
B
C
Complies with following standards:
IEC 61000-4-2
level 4 input pins 15 kV (air discharge)
8 kV (contact discharge
level 1 output pins 2 kV (air discharge)
2 kV (contact discharge
MIL STD 883G - Method 3015-7 Class 3
January 2007 Rev 1 1/7
www.st.com
Page 2
Characteristics EMIF02-SPK01C2
1 Characteristics
Figure 1. Basic cell configuration
Low-pass Filter
Input
Output
Ri/o = 10
Ω
Cline = 200 pF
GND GND GND
Table 1. Absolute ratings (limiting values)
Symbol Parameter Value Unit
T
T
op
T
stg
Table 2. Electrical characteristics (T
Maximum junction temperature 125 °C
j
Operating temperature range -40 to +85 °C
Storage temperature range -55 to +150 °C
= 25° C)
amb
Symbol Parameters
V
I
V
V
Breakdown voltage
BR
Leakage current @ V
RM
Stand-off voltage
RM
Clamping voltage
CL
R
Dynamic impedance
d
RM
VCL
VRMVBR
I
IR
IRM
I
PP
IRM
IR
VBRVRM
VCL
V
I
Peak pulse current
PP
R
C
Series resistance between input and output
I/O
Input capacitance per line
line
Symbol Test conditions Min Typ Max Unit
V
BR
I
RM
R
I/O
C
line
IR = 1 mA 6 8 V
VRM = 3 V per line 500 nA
Tolerance ±20% 10 Ω
VR = 0 V 200 pF
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IPP
Page 3
EMIF02-SPK01C2 Characteristics
Figure 2. S21 (dB) attenuation measurement Figure 3. Analog crosstalk measurement
dB
0.00
-
-5.00
-
-10.00
-
-15.00
-
-20.00
-
-25.00
-
-30.00
-35.00
-40.00
100.0k 1.0M 10.0M 100.0M 1.0G
1.0M
F (Hz)
Figure 4. ESD response to IEC 61000-4-2
(+15 kV air discharge) on one
input V
and one output V
in
out
Figure 5. ESD response to IEC 61000-4-2
dB
0.00
-10.00
-
-20.00
-
-30.00
-
-40.00
-
-50.00
-
-60.00
-
100.0k 1.0M 10.0M 100.0M 1.0G
F (Hz)
(- 15 kV air discharge) on one
input V
and one output V
in
out
Figure 6. Line capacitance versus applied
voltage
C(pF)
250
F=1MHz
V
=30mV
osc
200
150
100
50
V (V)
0
012345
R
Tj=25°C
RMS
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Page 4
Characteristics EMIF02-SPK01C2
Figure 7. Aplac model
IN1
IN2 OUT2
Rbump Lbump Lbump Rbump
model = D1 model = D2
model = D1
Rbump Lbump Lbump RbumpRspk Lspk
Rspk Lspk
model = D3
model = D2
EMIF02-SPK01C2 model
Figure 8. Aplac parameters
Model D1
CJO=Cdiode1
BV=7
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.7
VJ=0.6
TT=50n
Model D3
CJO=Cdiode3
BV=7
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.12
VJ=0.6
TT=50n
Model D2
CJO=Cdiode2
BV=7
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.3
VJ=0.6
TT=50n
OUT1
GND
Cgnd
aplacvar Ls 1nH
aplacvar Rs 150m
aplacvar Rspk 10
aplacvar Lspk 10p
aplacvar Cdiode1 234pF
aplacvar Cdiode2 3.5ppF
aplacvar Cdiode3 1nF
aplacvar Lbump 50pH
aplacvar Rbump 10m
aplacvar Rsub 0.5m
aplacvar Lsub 10pH
aplacvar Rgnd 1m
aplacvar Lgnd 50pH
aplacvar Cgnd 0.15pF
GND
Lsub
Rsub
Rbump
Lbump
Lgnd
Rgnd
Ground return
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Page 5
EMIF02-SPK01C2 Ordering information scheme
5
2 Ordering information scheme
EMIF yy - xxx zz Cx
EMI Filter
Number of lines
Information
3 letters = application
2 digits = version
Package
C = Coated Flip-Chip
x = 2: Leadfree Pitch = 500 µm, Bump = 315 µm
3 Package information
Figure 9. Flip-Chip Dimensions
500 µm ± 10
250 µm ± 10
00 µm ± 15
1.07 mm ± 50 µm
315 µm ± 50
1.47 mm ± 50 µm
695 µm ± 50
Figure 10. Marking Figure 11. Footprint recommendation
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year ww = week)
E
xyxwz
w
Solder mask opening recommendation:
340 µm min for 315 µm copper pad diameter
Copper pad Diameter:
250µm recommended, 300 µm max
Solder stencil opening: 330 µm
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Page 6
Ordering information EMIF02-SPK01C2
Figure 12. Flip-Chip tape and reel specification
Dot identifying Pin A1 location
4 ± 0.1
Ø 1.5 ± 0.1
1.75 ± 0.1
8 ± 0.3
0.73 ± 0.05
All dimensions in mm
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available
at: www.st.com.
4 Ordering information
Ordering code Marking Package Weight Base qty Delivery mode
E E E
ST
xxz
yww
ST
xxz
yww
4 ± 0.1
User direction of unreeling
ST
xxz
yww
3.5 ± 0.1
EMIF02-SPK01C2 FX Flip-Chip 2.3 mg 5000 7” Tape and reel
5 Revision history
Date Revision Changes
26-Jan-2006 1 Initial release.
6/7
Page 7
EMIF02-SPK01C2
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