Page 1
EL4585C
Horizontal Genlock, 8 F
EL4585C March 1996 Rev C
SC
Features
# 36 MHz, general purpose PLL
# 8F
timing. (Use the EL4584
SC
for4F
SC
)
# Compatible with EL4583C Sync
Separator
# VCXO, Xtal, or LC tank
oscillator
k
#
2nS jitter (VCXO)
# User-controlled PLL capture and
lock
# Compatible with NTSC and PAL
TV formats
# 8 pre-programmed popular TV
scan rate clock divisors
# Single 5V, low current operation
Applications
# Pixel Clock regeneration
# Video compression engine
(MPEG) clock generator
# Video Capture or digitization
# PIP (Picture In Picture) timing
generator
# Text or Graphics overlay timing
Ordering Information
Part No. Temp. Range Package Outline
EL4585CNb40§Cto
EL4585CS
For 3Fsc and 4Fsc clock frequency operation,
see EL4584 datasheet.
a
85§C 16-Pin DIP MDP0031
b
40§Ctoa85§C 16-Lead SO MDP0027
Demo Board
A demo PCB is available for this
product. Request ‘‘EL4584/5 Demo
Board’’.
General Description
The EL4585C is a PLL (Phase Lock Loop) sub system, designed
for video applications, but also suitable for general purpose use
up to 36 MHz. In a video application this device generates a
TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan rate, and phase locked to it.
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog composite
video signal with the EL4583 Sync Separator. An input signal
to ‘‘coast’’ is provided for applications where periodic disturbances are present in the reference video timing such as VTR
head switching. The Lock detector output indicates correct lock.
The divider ratio is four ratios for NTSC and four similar ratios
for the PAL video timing standards, by external selection of
three control pins. These four ratios have been selected for common video applications including 8 F
,6FSC, 27 MHz (CCIR
SC
601 format) and square picture elements used in some workstation graphics. To generate 4 F
,3FSC, 13.5 MHz (CCIR 601
SC
format) etc., use the EL4584, which does not have the additional divide by 2 stage of the EL4585.
For applications where these frequencies are inappropriate or
for general purpose PLL applications the internal divider can be
by passed and an external divider chain used.
FREQUENCIES and DIVISORS
Function 6Fsc CCIR 601 Square 8Fsc
Divisor* 1702 1728 1888 2270
Ý
PAL Fosc (MHz) 26.602 27.0 29.5 35.468
Divisor* 1364 1716 1560 1820
NTSC Fosc (MHz) 21.476 27.0 24.546 28.636
CCIR 601 divisors yield 1440 pixels in the active portion of each line for NTSC and PAL.
Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL.
6Fsc frequencies do not yield integer divisors.
*Divisor does not include
d
2 block.
Connection Diagram
EL4585 SO, P-DIP Packages
4585– 17
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
©
1995 Elantec, Inc.
Ý
4585C
Page 2
EL4585C
Horizontal Genlock, 8 F
SC
Absolute Maximum Ratings
Supply 7V
V
CC
Storage Temperature
b
65§Ctoa150§C
Lead Temperature 260
Pin Voltages
Operating Ambient Temperature Range
Important Note:
All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually
performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test
equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore T
Test Level Test Procedure
I 100% production tested and QA sample tested per QA test plan QCX0002.
II 100% production tested at T
III QA sample tested per QA test plan QCX0002.
IV Parameter is guaranteed (but not tested) by Design and Characterization Data.
V Parameter is typical value at T
T
MAX
and T
b
0.5V to V
b
A
per QA test plan QCX0002.
MIN
DC Electrical Characteristics
Parameter Conditions Temp Min Typ Max
I
DD
V
Input Low Voltage 25§C 1.5 I V
IL
e
V
5V (Note 1) 25§C24ImA
DD
e
(T
25§C)
A
C
§
a
0.5V
CC
40§Ctoa85§C
e
25§C and QA sample tested at T
e
25§C for information purposes only.
A
e
(V
DD
5V, T
e
A
Operating Junction Temp 125
Power Dissipation 400mW
Oscillator Frequency 36MHz
e
e
T
J
C
e
25§C,
A
25§C unless otherwise noted)
Test
Level
TA.
C
§
Units
VIHInput High Voltage 25§C 3.5 I V
IILInput Low Current All inputs except COAST, V
IIHInput High Current All inputs except COAST, V
IILInput Low Current COAST pin, V
IIHInput High Current COAST pin, V
VOLOutput Low Voltage Lock Det, I
VOHOutput High Voltage Lock Det, I
VOLOutput Low Voltage CLK, I
VOHOutput High Voltage CLK, I
VOLOutput Low Voltage OSC Out, I
VOHOutput High Voltage OSC Out, I
IOLOutput Low Current Filter Out, V
IOHOutput High Current Filter Out, V
IOL/IOHCurrent Ratio Filter Out, V
I
Filter Out Coast Mode, V
LEAK
e
1.5V 25§C
in
e
3.5V 25§C 60 100 I mA
in
e
1.6mA 25§C 0.4 I V
OL
eb
1.6mA 25§C 2.4 I V
OH
e
3.2mA 25§C 0.4 I V
OL
eb
3.2mA 25§C 2.4 I V
OH
e
200mA25
OL
eb
200mA25
OH
e
2.5V 25§C 200 300 I mA
OUT
e
2.5V 25§C
OUT
e
2.5V 25§C 1.05 1.0 0.95 I
OUT
l
V
DD
OUT
e
1.5V 25§C
in
e
3.5V 25§C 100 I nA
in
l
0V 25§C
b
100 I nA
b
C 0.4 I V
§
C 2.4 I V
§
b
100
100
b
60 I mA
b
b
300
g
200 I mA
1 100 I nA
Note 1: All inputs to 0V, COAST floating.
TD is 3.5in
2
Page 3
EL4585C
Horizontal Genlock, 8 F
e
AC Electrical Characteristics
Parameter Conditions Temp Min Typ Max
VCO Gain@20 MHz Test circuit 1 25§C 15.5 V dB
H-sync S/N Ratio V
Jitter VCXO Oscillator 25§C1 Vns
Jitter LC Oscillator (Typ) 25§C10 Vns
Note 2: Noisy video signal input to EL4583C, H-sync input to EL4585C. Test for positive signal lock.
e
5V (Note 2) 25§C35 V dB
DD
(V
DD
Pin Description
Pin No. Pin Name Function
16, 1, 2 Prog A,B,C Digital inputs to selectdN value for internal counter. See table below for values.
3 Osc/VCO Out Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit.
4V
5 Osc/VCO In Input from external VCO.
6V
7 Charge Pump Connect to loop filter. If the H-sync phase is leading or H-sync frequencylCLKd2N, current is
8 Div Select Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin,
9 Coast Tri-state logic input. Low(k(/3*VCC)enormal mode, Hi Z(or (/3 to )/3*VCC)efast lock mode,
10 H-sync In Horizontal sync pulse (CMOS level) input.
11 VDD(D) Positive supply for digital, I/O circuits.
12 Lock Det Lock Detect output. Low level when PLL is locked. Pulses high when out of lock.
13 Ext Div External Divide input when DIV SEL is low, internald2N output when DIV SEL is high.
14 VSS(D) Ground for digital, I/O circuits.
15 CLK Out Buffered output of the VCO.
(A) Analog positive supply for oscillator, PLL circuits.
DD
(A) Analog ground for oscillator, PLL circuits.
SS
Out
pumped into the filter capacitor to increase VCO frequency. If H-sync phase is lagging or frequency
k
CLKd2N, current is pumped out of the filter capacitor to decrease VCO frequency. During coast
mode or when locked, charge pump goes to a high impedance state.
outputting CLK
externaldN.
l
High(
d
2N. When low, the internal divider is disabled and EXT DIV is an input from an
)/3*VCC)ecoast mode.
Table 5. VCO Divisors
Prog A Prog B Prog C Div Value
Pin 16 Pin 1 Pin 2 N
0 0 0 1702
0 0 1 1728
0 1 0 1888
0 1 1 2270
1 0 0 1364
1 0 1 1716
1 1 0 1560
1 1 1 1820
e
5V, T
25§C unless otherwise noted)
A
Test
Level
SC
Units
TD is 3.5in TD is 3.5in
3
Page 4
EL4585C
Horizontal Genlock, 8 F
Timing Diagrams
PLL Locked Condition (Phase Errore0)
SC
Out of Lock Condition
4585– 2
T
i
e
i
E
T
H
e
T
H-sync period
H
e
phase error period
T
i
c
360
§
Typical Performance Curves
4585– 3
Test Circuit 1
4585– 5
4
Page 5
EL4585C
Horizontal Genlock, 8 F
SC
Typical Performance Curves
Idd vs Fosc
Typical Varactor
Ð Contd.
4585– 4
OSC Gain vs Fosc
OSC Gain@20 MHz vs Temp
Charge Pump Duty Cycle Vs i
4585– 6
E
4585– 9
4585– 7
EL4585 Block Diagram
4585– 8
4585– 1
5
Page 6
EL4585C
Horizontal Genlock, 8 F
SC
Description Of Operation
The horizontal sync signal (CMOS level, falling
leading edge) is input to H-SYNC input (pin 10).
This signal is delayed about 110nS, the falling
edge of which becomes the reference to which the
clock output will be locked. (See timing diagrams.) The clock is generated by the signal on
pin 5, OSC in. There are 2 general types of VCO
that can be used with the EL4585C, LC and crystal controlled. Additionally, each type can be either built up using discrete components, including a varactor as the frequency controlling element, or complete, self contained modules can be
purchased with everything inside a metal can.
These modules are very forgiving of PCB layout,
but cost more than discrete solutions. The VCO
or VCXO is used to regulate the clock. An LC
tank resonator has greater ‘‘pull’’ than a crystal
controlled circuit, but will also be more likely to
drift over time, and thus will generate more jitter. The ‘‘pullability’’ of the circuit refers to the
ability to pull the frequency of oscillation away
from its center frequency by modulating the voltage on the control pin of the VCO module or varactor, and is a function of the slope and range of
the capacitance-voltage curve of the varactor or
VCO module used. The VCO signal is sent to the
CLK out pin, divided by two, then sent to the
divide by N counter. The divisor N is determined
by the state of pins 1, 2, and 16 and is described
in table 5 above. The divided signal is sent, along
with the delayed H-sync input, to the phase/frequency detector, which compares the two signals
for phase and frequency differences. Any phase
difference is converted to a current at the charge
pump output, (pin 7). A VCO with a positive frequency deviation with control voltage must be
used. Varactors have negative capacitance slope
with voltage, resulting in positive frequency deviation with increasing control voltage for the oscillators in figures 10 and 11 below.
VCO
The VCO should be tuned so that its frequency of
oscillation is very close to the required clock output frequency when the voltage on the varactor
is 2.5 volts. VCXO and VCO modules are already
tuned to the desired frequency, so this step is not
necessary if using one of these units. The output
range of the charge pump output (pin 7) is 0 to
5 volts, and it can source or sink a maximum of
about 300mA, so all frequency control must be
accomplished with variable capacitance from the
varactor within this range. Crystal oscillators are
more stable than LC oscillators, which translates
into lower jitter, but LC oscillators can be pulled
from their mid-point values further, resulting in
a greater capture and locking range. If the incoming horizontal sync signal is known to be very
stable, then a crystal oscillator circuit can be
used. If the H-sync signal experiences frequency
variations of greater than about 300ppm, an LC
oscillator should be considered, as crystal oscillators are very difficult to pull this far. When Hsync input frequency is greater than CLK fre-
d
quency
current into the filter capacitor, increasing the
voltage across the varactor, thus tending to increase VCO frequency. Conversely, charge pump
output pulls current from the filter capacitor
when H-sync frequency is less than CLK
forcing the VCO frequency lower.
2N, charge pump output (pin 7) sources
d
2N,
Loop Filter
The loop filter controls how fast the VCO will
respond to a change in phase comparator output
stimulus. Its components should be chosen so
that fast lock can be achieved, yet with a minimum of VCO ‘‘hunting’’, preferably in one to two
oscillations of charge pump output, assuming the
VCO frequency starts within capture range. If
the filter is under-damped, the VCO will over and
under-shoot the desired operating point many
times before a stable lock takes place. It is possible to under-damp the filter so much that the
loop itself oscillates, and VCO lock is never
achieved. If the filter is over-damped, the VCO
response time will be excessive and many cycles
will be required for a lock condition. Over-damping is also characterized by an easily unlocked
system because the filter can’t respond fast
enough to perturbations in VCO frequency. A severely over damped system will seem to endlessly
oscillate, like a very large mass at the end of a
long pendulum. Due to parasitic effects of PCB
traces and component variables, it will take some
trial and error experimentation to determine the
best values to use for any given situation. Use the
component tables as a starting point, but be
aware that deviations from these values are not
out of the ordinary.
6
Page 7
EL4585C
Horizontal Genlock, 8 F
SC
Description Of Operation
Ð Contd.
External Divide
DIV SEL (pin 8) controls the use of the internal
divider. When high, the internal divider is enabled and EXT DIV (pin 13) outputs the CLK
out divided by 2N. This is the signal to which the
horizontal sync input will lock. When divide select is low, the internal divider output is disabled,
and external divide becomes an input from an external divider, so that a divisor other than one of
the 8 pre-programmed internal divisors can be
used.
Normal Mode
Normal mode is enabled by pulling COAST (pin
9) low (below (/3*Vcc). If H-SYNC and CLK
have any phase or frequency difference, an error
signal is generated and sent to the charge pump.
The charge pump will either force current into or
out of the filter capacitor in an attempt to modulate the VCO frequency. Modulation will continue until the phase and frequency of CLK
exactly match the H-sync input. When the phase
and frequency match (with some offset in phase
that is a function of the VCO characteristics), the
error signal goes to zero, lock detect no longer
pulses high, and the charge pump enters a high
impedance state. The clock is now locked to the
H-sync input. As long as phase and frequency
differences remain small, the PLL can adjust the
VCO to remain locked and lock detect remains
low.
d
d
2N
2N
Fast Lock Mode
Fast Lock mode is enabled by either allowing
coast to float, or pulling it to mid supply (between (/3 and )/3*Vcc). In this mode, lock is
achieved much faster than in normal mode, but
the clock divisor is modified on the fly to achieve
this. If the phase detector detects an error of
enough magnitude, the clock is either inhibited
or reset to attempt a ‘‘fast lock’’ of the signals.
Forcing the clock to be synchronized to the
H-sync input this way allows a lock in approximately 2 H-cycles, but the clock spacing will not
be regular during this time. Once the near lock
condition is attained, charge pump output should
be very close to its lock-on value, and placing the
device into normal mode should result in a normal lock very quickly. Fast lock mode is intended
to be used where H-sync becomes irregular, until
a stable signal is again obtained.
Coast Mode
Coast mode is enabled by pulling COAST (pin 9)
high (above )/3*Vcc). In coast mode the internal
phase detector is disabled and filter out remains
in high impedance mode to keep filter out voltage and VCO frequency as constant a possible.
VCO frequency will drift as charge leaks from the
filter capacitor, and the voltage changes the VCO
operating point. Coast mode is intended to be
used when noise or signal degradation result in
loss of horizontal sync for many cycles. The
phase detector will not attempt to adjust to the
resultant loss of signal so that when horizontal
sync returns, sync lock can be re-established
quickly. However, if much VCO drift has occurred, it may take as long to re-lock as when
restarting.
Lock Detect
Lock detect (pin 12) will go low when lock is established. Any DC current path from charge
pump out will skew EXT DIV relative to HSYNC in, tending to offset or add to the 110nS
internal delay, depending on which way the extra
current is flowing. This offset is called static
phase error, and is always present in any PLL
system. If, when the part stabilizes in a locked
mode, lock detect is not low, adding or subtracting from the loop filter series resistor R
change this static phase error to allow LDET to
go low while in lock. The goal is to put the rising
edge of EXT DIV in sync with the falling edge of
H-SYNC
creasing R
ing R
tive when EXT DIV lags H-SYNC.) The resistance needed will depend on VCO design or VCXO
module selection.
a
110nS. (See timing diagrams.) In-
decreases phase error, while decreas-
2
increases phase error. (Phase error is posi-
2
will
2
7
Page 8
EL4585C
Horizontal Genlock, 8 F
SC
Applications Information
Choosing External Components
1. To choose LC VCO components, first pick the
desired operating frequency. For our example
we will use 28.636MHz, with an H-sync frequency of 15.734kHz.
2. Choose a reasonable inductor value (1-5mH
works well). We choose 3.3mH.
3. Calculate C
e
F
OSC
e
C
T
4q2F2L
4. From the varactor data sheet find C
the desired lock voltage. C
SMV1204-12 for example.
5. C
should be about 10CV, so we choose
2
e
C
220pF for our example.
2
6. Calculate C
e
C
T
(C1C2)a(C1CV)a(C2C
then
needed to produce F
T
1
2q0LC
1
T
e
4q2(28.636e6)2(3.3eb6)
. Since
1
C1C2C
V
.
OSC
1
V
V
e
9.4pF
@
V
e
23pF for our
,
)
2.5V,
Typical LC VCO
4585– 10
LC VCO Component Values (Approximate)
Frequency L1 C1 C2
(MHz) (mH) (pF) (pF)
26.602 3.3 22 220
27.0 3.3 21 220
29.5 2.7 22 220
35.468 2.2 16 220
21.476 4.7 26 220
24.546 3.9 22 220
28.636 3.3 17 220
Note: Use shielded inductors for optimum performance.
Typical Xtal VCO
C2CTC
e
C
1
(C2Cv)b(C2CT)b(CTCV)
For our example, C
V
e
17pF. (A trim cap may be
1
.
used for fine tuning.) Examples for each frequency using the internal divider follow.
4585– 11
8
Page 9
EL4585C
Horizontal Genlock, 8 F
Typical Application
Horizontal genlock provides clock for an analog to digital converter, digitizing analog video.
SC
Xtal VCO Component Values (Approximate)
Frequency R1 C1 C2
(MHz) (kX) (pF) (mF)
26.602 300 15 .001
27.0 300 15 .001
29.5 300 15 .001
35.468 300 15 .001
21.476 300 15 .001
24.546 300 15 .001
28.636 300 15 .001
The above oscillators are arranged as Colpitts oscillators, and the structure is redrawn here to emphasize the split capacitance used in a Colpitts
oscillator. It should be noted that this oscillator
configuration is just one of literally hundreds
possible, and the configuration shown here does
not necessarily represent the best solution for all
applications. Crystal manufacturers are very informative sources on the design and use of oscillators in a wide variety of applications, and the
reader is encouraged to become familiar with
them.
Colpitts Oscillator
4585– 18
4585– 12
C1is to adjust the center frequency, C2DC isolates the control from the oscillator, and V1 is the
primary control device. C
than C
so that V1has maximum modulation
V
should be much larger
2
capability. The frequency of oscillation is given
by:
1
e
F
2q0LC
T
C1C2C
e
C
T
(C1C2)a(C1CV)a(C2CV)
V
9
Page 10
EL4585C
Horizontal Genlock, 8 F
Choosing Loop Filter
Components
The PLL, VCO, and loop filter can be described
as:
Where:
e
K
phase detector gain in A/rad
d
e
F(s)
loop filter impedance in V/A
e
K
N
low)
VCO gain in rad/s/V
VCO
e
Total internal or external divisor (see 3 be-
SC
4585– 13
e
transfer function C
verse bias control voltage, and C
pacitance. Since F(V
best to build the VCO and measure K
F(VC), where VCis the re-
v
) is nonlinear, it is probably
C
is varactor ca-
V
VCO
about
2.5V. The results of one such measurement are
shown below. The slope of the curve is determined by linear regression techniques and equals
K
. For our example, K
VCO
F
vs VC,LCVCO
OSC
e
9.06 Mrad/s/V.
VCO
It can be shown that for the loop filter shown
below:
KdK
e
C
3
Where 0
VCO
2
N0
n
e
loop filter bandwidth, and geloop
n
,C
C
3
e
,R
4
10
2Ng0
KdK
n
VCO
e
3
filter damping factor.
e
1. K
300mA/2qrade4.77e-5A/rad for the
d
EL4585C.
2. The loop bandwidth should be about H-sync
frequency/20, and the damping ratio should be
1 for optimum performance. For our example,
e
0
15.734kHz/20e787 Hz&5000 rad/S.
n
e
3. N
N
4. K
910x2e1820 from table 1.
e
F
F
VCO
VCO
Hsync
28.636M
e
15.73426k
e
1820e910x2
represents how much the VCO frequency changes for each volt applied at the control
pin. It is assumed (but probably isn’t) linear
about the lock point (2.5V). Its value depends
on the VCO configuration and the varactor
5. Now we can solve for C3,C4, and R3.
KdK
e
C
3
N0
C
3
e
e
10
2Ng0
KdK
e
C
4
R
3
We choose R
6. Notice R
sign. R
2
VCO
(4.77eb5)(9.06e6)
e
2
n
(1820)(5000)
e
0.01mF
2
0.001mF
(2)(1820)(1)(5000)
n
e
VCO
(4.77eb5)(9.06e6)
e
43kX for convenience.
3
has little effect on the loop filter de-
2
e
42.1kX
should be large, around 100k, and can
be adjusted to compensate for any static phase
error T
slow loop response. If R
at lock, but if made too large, will
i
is made smaller, T
2
(see timing diagrams) increases, and if R2in-
4585– 14
i
10
Page 11
EL4585C
Horizontal Genlock, 8 F
SC
creases, Tidecreases. For LDET to be low at
lock,
k
T
50nS. C4is used mainly to attenuate
l
l
i
high frequency noise from the charge pump. The
effect these components have on time to lock is
illustrated below.
Lock Time
Let TeR3C3. As T increases, damping increases,
but so does lock time. Decreasing T decreases
damping and speeds up loop response, but increases overshoot and thus increases the number
of hunting oscillations before lock. Critical damp-
e
ing (g
decreased damping also decreases loop stability,
it is sometimes desirable to design slightly overdamped (g
stability.
1) occurs at minimum lock time. Because
l
1), trading lock time for increased
Typical Loop Filter
LC Loop Filter Components (Approximate)
Frequency R2 R3 C3 C4
(MHz) (kX)(kX)(mF) (mF)
26.602 100 39 0.01 0.001
27.0 100 39 0.01 0.001
29.5 100 43 0.01 0.001
35.468 100 51 0.01 0.001
21.476 100 30 0.01 0.001
24.546 100 36 0.01 0.001
28.636 100 43 0.01 0.001
4585– 16
Xtal Loop Filter Components (Approximate)
Frequency R2 R3 C3 C4
(MHz) (kX)(MX) (pF) (pF)
26.602 100 4.3 68 6.8
27.0 100 4.3 68 6.8
29.5 100 4.3 68 6.8
35.468 100 4.3 68 6.8
21.476 100 4.3 68 6.8
24.546 100 4.3 68 6.8
28.636 100 4.3 68 6.8
PCB Layout Considerations
It is highly recommended that power and ground
planes be used in layout. The oscillator and filter
sections constitute a feedback loop and thus care
must be taken to avoid any feedback signal influencing the oscillator except at the control input.
The entire oscillator/filter section should be surrounded by copper ground to prevent unwanted
influences from nearby signals. Use separate
paths for analog and digital supplies, keeping the
analog (oscillator section) as short and free from
spurious signals as possible. Careful attention
must be paid to correct bypassing. Keep lead
lengths short and place bypass caps as close to
the supply pins as possible. If laying out a PCB
to use discrete components for the VCO section,
care must be taken to avoid parasitic capacitance
at the OSC pins 3 and 5, and FILTER out (pin
7). Remove ground and power plane copper
above and below these traces to avoid making a
capacitive connection to them. It is also recommended to enclose the oscillator section within a
shielded cage to reduce external influences on the
VCO, as they tend to be very sensitive to ‘‘hand
waving’’ influences, the LC variety being more
sensitive than crystal controlled oscillators. In
general, the higher the operating frequency, the
more important these considerations are. Self
contained VCXO or VCO modules are already
mounted in a shielding cage and therefore do not
require as much consideration in layout. Many
crystal manufacturers publish informative literature regarding use and layout of oscillators which
should be helpful.
11
Page 12
EL4585C
Horizontal Genlock, 8 F
SC
EL4585/4 Demo Board
4585– 19
12
Page 13
EL4585C
Horizontal Genlock, 8 F
SC
EL4585/4 Demo Board
The VCO and loop filter section of the EL4583/4/5 Demo Board can be implemented in the following
configurations:
Ð Contd.
(1) VCXO
4585– 20
(2) XTAL
(3) LC Tank
13
4585– 21
4585– 22
Page 14
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14
Page 15
BLANK
15
Page 16
EL4585C
Horizontal Genlock, 8 F
EL4585CMarch 1996 Rev C
Component Sources
SC
Inductors
# Dale Electronics
E. Highway 50
PO Box 180
Yankton, SD 57078-0180
(605) 665-9301
Crystals, VCXO, VCO Modules
# Connor-Winfield
2111 Comprehensive Drive
Aurora, IL 60606
(708) 851-4722
# Piezo Systems
100 K Street
PO Box 619
Carlisle, PA 17013
(717) 249-2151
# Reeves-Hoffman
400 West North Street
Carlisle, PA 17013
(717) 243-5929
# SaRonix
151 Laura Lane
Palo Alto, CA 94043
(415) 856-6900
# Standard Crystal
9940 Baldwin Place
El Monte, CA 91731
(818) 443-2121
Varactors
# Alpha Industries
20 Sylvan Road
Woburn, MA 01801
(617) 935-5150
# Motorola Semiconductor Products
2100 E. Elliot
Tempe, AZ 85284
(602) 244-6900
Note: These sources are provided for information
purposes only. No endorsement of these companies is implied by this listing.
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes
in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any
circuits described herein and makes no representations that they are free from patent infringement.
WARNING Ð Life Support Policy
Elantec, Inc. products are not authorized for and should not be
used within Life Support Systems without the specific written
consent of Elantec, Inc. Life Support systems are equipment in-
Elantec, Inc.
1996 Tarob Court
Milpitas, CA 95035
Telephone: (408) 945-1323
(800) 333-6314
Fax: (408) 945-9305
European Office: 44-71-482-4596
tended to support or sustain life and whose failure to perform
when properly used in accordance with instructions provided can
be reasonably expected to result in significant personal injury or
death. Users contemplating application of Elantec, Inc. products
in Life Support Systems are requested to contact Elantec, Inc.
factory headquarters to establish suitable terms & conditions for
these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages.
Printed in U.S.A.16
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