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EL4331C
Triple 2:1 Mux-Amp AV = 1
EL4331C
Features
•3 ns A-B switching
• 300 MHz bandwidth
• Power down mode
• TTL/CMOS compatible controls
• Fixed gain of 1
• 400V/µs slew rate
Applications
• RGB multiplexing
• Picture-in-picture
•Cable driving
• HDTV processing
• Switched gain amplifiers
• ADC input multiplexer
Ordering Information
Part No. Temp. Range Package Outline#
EL4331CS -45°C to +85 °C 16-Lead SOIC MDP0027
General Description
The EL4331C is a trip le , ve ry hi gh sp eed , 2 :1 Mu ltip le x ing Am pl ifie r.
It is intended primarily for component vid eo multiple xing, and is es pecially suited for pixel switching. The amplifiers have their gain set to
1, internally. All three amplifiers are switched simultaneously from
their A to B inputs by the TTL/CMOS compatible, common A/B control pin.
The EL4331C has a power down mode, in which the total supply current drops to less than 1 mA. In this mode, each output will appear as
a high impedance.
The EL4331C runs fro m st an dard ±5V s uppl ie s, an d is a vai lable in the
narrow 16-pin small outline package.
© 1995 Elantec, Inc.
Connection Diagrams
October 6, 1999
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EL4331C
Triple 2:1 Mux-Amp AV = 1
EL4331C
Absolute Maximum Ratings (T
VCC to V
EE
to Any GND 12V
V
CC
to Any GND 12V
V
EE
Continuous Output Current 45 mA
Any Input (except P
Input VCC-7V to VCC+0.3V
P
D
)V
D
= 25 °C)
A
-0.3V to VCC+0.3V
EE
14V
Input Current, Any Input 5 mA
Power Dissipation See curves
Operating Temperature -45°C to +85°C
Leading Temperature during Soldering 300°C
Junction Temperature 170°C
Storage Temperature -60°C to +150°C
Important Note:
All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during
production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test equipment, specifically the LTX77
Series system. Unless otherwise noted, all tests are pulsed tests, therefor T
= TC = TA.
J
Test Level Test Procedure
I 100% production tested and QA sample tested per QA test plan QCX0002.
II 100% production tested at T
= 25°C and QA sample tested at TA = 25°C, T
A
MAX
and T
per QA test plan QCX0002.
MIN
III QA sample tested per QA test plan QCX0002.
IV Parameter is guaranteed (but not tested) by Design and Characterization Data.
V Parameter is typical value at T
= 25°C for information purposes only.
A
DC Electrical Characteristics
VCC = +5V, VEE = -5V, Ambient Temperature =25°C, RL = 500Ω, PD = 5V
Parameter Description Min Typ Max
V
OS
dV
OS
I
B
dI
B
AV
OL
Input Referred Offset Voltage -12 30 II mV
Input A to Input B Offset Voltage
[1]
18II mV
Input Bias Current -7 -30 II µA
Input A to Input B Bias Current
[1]
0.5 4.0 II µA
Open Loop Gain (from Gain Error Calculation) 54 VdB
PSRR Power Supply Rejection Ratio 60 70
_500 Output Voltage Swing into 500Ω Load ±2.7 ±3.2 II V
V
OUT
V
_150 Output Voltage Swing into 150Ω Load +3/-2.7 VV
OUT
I
OUT
X
TALK
V
IH
V
IL
I
IL_AB
I
IH_AB
I
IL_PD
I
IH_PD
I
S
I
S(PD)
Current Output, Measured with 75Ω load Crosstalk from Non-Selected Input (at DC) -70 -85 II dB Input Logic High Level (A/B and PD) 2.0 II V Input Logic Low Level (A/B and PD) 0.8 II V Logic Low Input Current (VIN = 0.8V), A/B Pin -1 -20 -100 II µA Logic High Input Current (VIN = 2.0V), A/B Pin -5 0 5 II µA Logic Low Input Current (VIN = 0.8V), PD Pin -10 0 10 II µA Logic High Input Current (VIN = 5.0V), PD Pin 0.5 1.0 1.6 II mA Total Supply Current 38 48 60 II mA Powered Down Supply Current 0.01 1.0 II mA
[2]
30 40 II mA
1. Any channel’s A-input to its B-input.
2. There is no short circuit protection on any output.
Test Level Units
II dB
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EL4331C
Triple 2:1 Mux-Amp AV = 1
AC Electrical Characteristics
VCC = +5V, VEE = -0.5V, Ambient Temperature = 25°C, RL = 150Ω and CL = 5 pF
Parameter Description Min Typ Max Test Level Units
BW -3 dB Bandwidth
SR Slew Rate (4V Square Wav e, Measured 25%–75%) 400 V V/µs T
S
T
AB
OS Overshoot, V
-10M Input to Input Isolation at 10 MHz 53 V dB
I
SO-AB
I
-100M Input to Input Isolation at 100 MHz 33 V dB
SO-AB
I
-10M Channel to Channel Isolation at 10 MHz 56 V dB
SO-CH
I
SO-CH-CH
Pkg Peaking with Nominal Load 0 V dB
T
ON_PD
T
OFF_PD
-3 dB BW with 250Ω and 10 pF Load
Settling Time to 0.1% of Final Value 13 V ns
Time to Switch Inputs 3 V ns
= 4V
OUT
pk-pk
-100M Channel to Channel Isolation at 100 MHz 33 V dB
Power Down Turn-On T ime 150 V ns
Power Down Turn-Off Time 1 V µs
300
400
8V%
V
V
EL4331C
MHz
MHz
3
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EL4331C
Triple 2:1 Mux-Amp AV = 1
EL4331C
Typical Performance Curves
3 dB Bandwidth Small Signal Transmit Response Large Signal Transient Response
Switching from Ground to An
Uncorrelated Sine Wave and Back
Switching Glitch, 0V to 0V with 2 ns AB edges Switching Glitch, 0V to 0V with 10 ns AB Edges
Switching a Family of DC Levels to Ground and Back
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EL4331C
Triple 2:1 Mux-Amp AV = 1
EL4331C
Switching a Family of DC Levels to a Sine Wave and BackV
Output Response In and Out of
Power Down with a Family of DC Inputs
Output Power Down Turn-On ResponseOutput Power Down Turn-Off Response
Frequency Response with
150Ω and 5 pF Load
Frequency Response with
240Ω and 5 pF Load
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EL4331C
Triple 2:1 Mux-Amp AV = 1
EL4331C
Frequency Response with 150Ω and
Various Values of Capacitive Load
A-Input to B-Input Isolation Channel to Channel Isolation
Frequency Response with 240Ω and
Various Values of Capacitive Load
Supply Current
vs Power Down Voltage
-3 dB BW vs Supply Voltage
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Triple 2:1 Mux-Amp AV = 1
Slew Rate vs Supply Voltage Slew Rate vs Temperature
EL4331C
EL4331C
Total Harmonic Distortion
Output Voltage Swing vs
Supply Voltage
Voltage Noise Spectral Density
Maximum Power Dissipation
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EL4331C
Triple 2:1 Mux-Amp AV = 1
EL4331C
Applications Information
Pin Descriptions
A1, A2, A3 “A” inputs to amplifiers 1, 2 and 3 respectively
B1, B2, B3 “B” inputs to amplifiers 1, 2 and 3 respectively
GND1, GND2,
GND3
OUT1, OUT2,
OUT3
V
CC
V
EE
A/B Common input select pin, a logic high selects the “A”
PD A logic low puts the part into its power do wn mode. Note
These are the individual ground pins for each channel.
Amplifier outputs. Note there is no short circuit
protection.
Positive power supply. Typically +5V.
Negative power supply, typically -5V.
inputs, logic low selects the “B” inputs. If left to float,
this pin will float high and the “A” channels will be
selected.
that when this pin is at a logic high (+5V), it will sink
typically 1 mA. When pulled low, it will source a few
µA, typically < 25 µA. This pin should not be left
floating.
Circuit Operation
Each multiplexing amplifier has two input stages. The
multiplexing amplifiers switch from their “A” inputs to
their “B” inputs un de r c on tr ol o f t he c o m mo n A/B select
pin. The switch ing ha s a m a ke bef o r e bre a k ac tio n. Each
amplifier is internally c onn ected fo r un ity g a in, allo win g
larger switching matrixes to be built up. Note however,
that each amplifier likes to see a load of 250Ω or less;
load resistances higher than this, can lead to excessive
peaking. Load capacitance should be kept down below
40 pF, and 40 pF requires a load resistance of ð 150Ω to
keep the output from excessi ve peaki ng. High er capaci tive loads can best be driven using a series resistor to
isolate the amplifier from the reactive load.
The ground pins are used as a reference for the logic
controls. Both A/B and PD are referenced to ground.
The supplies do not have t o be symmetrical around
ground, but the logic inputs are referred to the ground
pins, and the logic sw ing must not exc eed the + V supp ly.
Due to the fact that all three channels share common
control pins, th e three ground s have to be at the same
potential. One third of the 1 mA that PD will sink (at
5V) will be seen at each ground pin. Also, the individual
grounds are internally connected to their channel compensation capacitor in an effort to keep crosstalk low.
A/B Switching
Referring to the photographs showing the 0V–0V
switching glitches, it will be noted that slower edges on
the A/B control pin result in switching glitches of somewhat less total energy. The switching action is a makebefore-break, so the two inputs essentially get mixed at
the output for a few nanoseconds. Note that the two
inputs are buffered, so there is no component of one
input injected into the other input. The input impedance
does not depend on whether an input has been sel ected.
Power Down
Referring to the photographs of the power down function and Figure 4, it will be noted t hat there is a
considerable glitch in the output as the part powers
down. It will also be noted that the power down time is
considerably longer than power up, 1 µs compared to
150 ns. In power down mode, the whole amplifier, its
reference and bias lines are all powered down. At the
same time, the output stage has bee n configu red so that
the powered down output appears as a high impedance.
This allows circuits such as the multiplexer show n in
application #4 to be realized, although the price is the
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significant o utput dis tur bance as on e p art turns on be fore
the other has fully turned off.
EL4331C
EL4331C
Triple 2:1 Mux-Amp AV = 1
Figure 1. Two RGB Sources Multiplexed to One RGB Output
Single Supply Operation
Due to the fact that video signals often have negative
sync levels and i nvariably require ground to be with in
the signal swing, runni ng the EL4331 on a single supply
rail compromises many aspects of its performance. It is
difficult to generate a solid, clean, pseudo ground a few
volts away from groun d witho ut us ing mor e power, and
components th an simply providin g a negative pow er
rail. A signal ground has to be capable of handling all the
return currents from all the inpu ts, as well a s the ou tputs,
from DC to frequencies in excess of 400 MHz. While
this is by no means impossible, a negative rail can be
generated from a standard +5V rail for a co uple of dollars and a square inch, or less, of board space. However,
a pseudo ground can be derived with for example an
LM336, to give an “AC ground” 2.5V above 0V. The
logic inputs will need some form of level shifting to
ensure that the logic “1” and “0” specifications can be
met. The pseu do ground must be well by passed to the
real ground; note that the pseudo ground will have to
sink/source all the current that flows in the internal compensation capacitors during slewing. This can easily be
several milliamps in a few nanoseconds. If the pseudo
ground “moves” because one channel is forcing current
into the derived ground, cross-talk into th e other two
channels will become very sig ni ficant.
Application Circuit #1
Figure 1 shows a very high speed RGB (or YUV) multiplexer. Two video sourc es can be displayed on one
monitor with the only stipulation that the video sources
have to be synchronous. An e xampl e is a pi ctu re-i n-picture, or “window” is generated with one video source
(e.g. RGB TV) in a window, and a computer application
around it. Multiplexing synchronous RGB signals has
the advantage that the video signals do not have to be
digitized, and an image stored in RAM prior to being
displayed.
When the monitor is switched off, or goes into its
power-saving blank ed mode, the EL43 31 can b e powered down to further save power. The input impedance
does not chang e appreci ably b etween po wered up and
down modes, although the bias current does drop to near
zero.
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EL4331C
Triple 2:1 Mux-Amp AV = 1
EL4331C
A demonstration board with this circuit on it is available
from Elantec.
Figure 2. A Bandwidth-Selectable Filter
Application Circuit #2
Figure 2 shows a ci rcuit th at has ei ther a very wi de bandwidth, or an 11 MHz low pass response. The EL4331’s
“A” inputs are connected to the one frequency determining set of components, while the “B” inputs are
connected direct ly. The A/B se lect pin th erefore selec ts
the desired bandwidth. This would allow appropriate filtering to clean up noisy low bandwidth video signals
when displaying them on a high quality wide bandwidth
monitor.
Application Circuit #3
Figure 3 shows one of the three channels of a component
video, 8:1 multiplexer. The A/B select pins naturally
allow binary coded addressing—allowing simple microprocessor or state machine control. Note that each
amplifier output is loaded, to keep the amplifier outputs
damped.
Photograph A 1 shows a stai rcase g enera ted by ha ving all
the inputs (sig0 through sig7) connected to a resistive
divider chain, and the select bits were driven by a binary
counter. Photograph A2 shows the glitch between steps
4 and 5; this is the worst glitch since all three banks of
EL4331s are switching together. The magnitude of this
glitch is affected by the timing skew of the select lines,
the physical length of the tra ces, and the difference in
amplitude of the two signals. This particu lar circuit was
bread-board ed usin g EL4331s on their ad apter boar ds
(available from Elantec for those who can not breadboard with SOICs), and the binary counter was an
'LS163.
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Applications Information
High Speed 8-to-1 Multiplexer
Note: No supply bypass cap acitors show n and onl y one
of three channels shown.
Channel Selection Table
BIT2BIT1BIT0OUTPUT
000SIG0
001SIG1
010SIG2
011SIG3
100SIG4
101SIG5
110SIG6
111SIG7
Figure 3. A High Speed, 8:1 C omponent Video
Multiplexer
Photograph A3 shows the same circuit, with the counter
running at 25 MHz. This turn s out to be c lose to the limit
of the TTL counter used in the breadboard, rather than
the limit of the EL4331. Here the different glitches are
easily recognizable—a small glit ch for one of th e 4 in put
EL4331s A/B switching, somewhat larger glit che s when
two banks switch together, and the biggest glitch when
all three banks switch. Photograp h A4 shows the big
glitch in detail. A good PCB and equal length and
matched traces would clean up these glitches.
433129
A1
433130
A2
433131
A3
433132
A4
8-to-1 Multiplexer using Power Down
Note: No supply bypass capacitors shown. Only one of
three channels show n.
EL4331C
EL4331C
Triple 2:1 Mux-Amp AV = 1
Channel Select ion Table
BIT2BIT1BIT0OUTPUT
000SIG0
001SIG1
010SIG2
011SIG3
100SIG4
101SIG5
110SIG6
111SIG7
Figure 4. A Simple 8:1 Component Video Multiplexer
Figure 4 shows one of the three channels of a component
video, 8:1 mul tiplexer. In this example, the power down
capability is used to save on EL4331s, but as can be
seen, the control part does become more complicated.
Using the power down mode for multiplexing does, of
course, slow down the speed with which one can select a
given input channel. Ho weve r, i f in pu t c h ann el sel ectio n
can be done during a blanking period, the couple of
microseconds that it takes to power down one
chip may be no problem. Note that some external logic
is needed in this application, both to select the appropriate amplifier, and also to force a break-before-make
action by pulling the T_OFF line low. All this logic
would best be incorporated inside a PAL or gate array,
and is shown in gate form just to illustra te th e idea . Note
that the BIT0 line would have the 3 ns response time,
since it is switching the muxamps directly.
Photograph B 1 s hows a sta irc ase gen erate d b y ha vi ng a ll
the inputs (sig0 through sig7) connected to a resistive
divider chain, and then the select bits and the PD pins
were driven by a binary counter and a 2-line to 1 of 4
decoder. Photograph B2 shows the glitch between steps
4 and 5; this glitch is caused by the fa ct that the ampli fier
that has just been powered up momentarily fights the
amplifier that has been powered down, but is not yet off.
As seen in the photograph, this causes a glitch of about
200 ns duration. However, when the A/B select pin
changes inputs, the glitches are mu ch smaller, as sho wn
in photograph B3. Photograph B4 sho w s the +2.5V to
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EL4331C
Triple 2:1 Mux-Amp AV = 1
EL4331C
-2.5V transition. This is another PD caused glitch, similar to the step 4 to step 5 glitch, but with a much
increased magnitude—which causes significantly more
fighting between the output stages.
Despite the glitches, if the PD switching can be done
during signal blanking, and only A/B switching is used
during the picture, this simple multiplexer has significant parts savings and power savings when compared to
the high performance multiplexer in the previous application note.
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EL4331C
Triple 2:1 Mux-Amp AV = 1
EL4331C
General Disclaimer
Specifications contained in this data sheet are in effect as of the publicat ion date shown. Elantec, Inc. re serves the r ight to make changes in th e circuitry or specifications cont ained herein at a ny time without notice. Elante c, Inc. assumes no res ponsibili ty for t he us e of any circuits described
herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intend ed to sup-
Elantec, Inc.
1996 Tarob Court
Milpitas, CA 95035
Telephone: (408) 945-1323
(800) 333-6314
Fax: (408) 945-9305
European Office: 44-71-482-4596
port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users contemplating applicatio n of Elantec, In c. Products in Li fe Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elantec, Inc. ’s warranty is limited to replacement of defective
components and does not cov er injury to per sons or prop erty or
other consequential damages.
October 6, 1999
13
Printed in U.S.A.
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