Datasheet EL4102CU Datasheet (ELANT)

C

EL4102C - Preliminary

500MHz Video Front End: 4-1 MUX, VGA & DC-Restore

EL4102C - Preliminary

Features

• 4:1 multiplexer with monitor out

• 18dB variable gain amplifier

• DC-restore amplifier

• Digital control serial interface

• ±5V operation

• 500MHz bandwidth

Applications

• HDTV/DTV Analog Inputs

• Video Projectors

• Computer Monitors

•Set Top Boxes

• Security Video

• Broadcast Video Equipment

Ordering Information

Part No. Package Tape & Reel Outline #

EL4102CU 24-Pin QSOP MDP0040

General Description

The EL4102C VFE (Vi deo Front End) is de signed to perform all of the
input processing functions in an analog video system as well as provide
analog input processing for digital video systems. The EL4102C VFE
contains a 4:1 MUX input, a DC-restore amplifier and a variable gain
amplifier. The MUX input can be used to select which input to use. In a
digital system, the DC-restore and variable gain amplifiers allow the
input signal to be positioned and scaled to give optimum A-to-D con­versions results. In an analog system these perform the brightnes s and
contrast operations. A buffered output of the MUX selection is also
available for use as a monitor output.

With a 500MHz bandwi dth and only 50mA supply cur rent, the
EL4102C is ideal for use in portable and fixed projectors, as well as
HDTV, DTV and other high performance vid e o ap plications.

A 3-wire digital interface enables full control of the input selection, as
well as 0 to -18dB of gain and blanking operations.

The EL4102C is availabl e in t he QSOP24 pac kage a nd is spec ified for
operation over the -40°C to +85°C temperature ran ge.

onnection Diagram

SAMPLE PULSE

V

I/P0

V

I/P1

V

I/P2

V

I/P3

+5V

1

HOLD

2

GNDL2

3

IN0

4

VS1+

5

IN1

6

0V

GNDI

7

IN2

8

-5V

VS-

9

IN3

CAP

DCREF

DCFDBK

VFDBK

VOUT

VS2+

VS-

MOUT

MFDBK

24

23

DCV

22

21

20

19

+5V

18

-5V

17

16

C

H

0.33nF

R

GV

R

FV

Video Out
RL=150Ω

Monitor Out

R

RL=150Ω

FM

R

GM

August 30, 2001

10

ENB

SDI

SCLK

Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request . W e recommend checking the revision level befo re finalization of your design documentation.

© 2001 Elantec Semiconductor, Inc.

ENB

11

SDI

12

SCLK

GNDL

PDWN

SDO

15

14

PDWN

13

DATAOUT

EL4102C - Preliminary

500MHz Video Front End: 4-1 MUX, VGA & DC-Restore

Absolute Maximum Ratings (T

Values beyond absolute maximum ratings can cause the device to be pre­maturely damaged. Absolute maximum ratings are stress ratings only
and functional device operation is not implied.

Supply Voltage (V

EL4102C - Preliminary

Input Voltage V

to VS-) 11V

S+

= 25°C)

A

- - 0.3V, VS+ +0.3V

S

Storage Temperature Range -65°C to +150°C
Ambient operating Temperature -40°C to +85°C
Operating Junction Temperature 125°C
Power Dissipation See Curves

Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the

specified temperature and are pulsed tests, therefore: T

= TC = TA.

J

Electrical Characteristics

VS1+ = VS2+ = 5V, VS1- = VS2- = -5V, RFV = RFG = 750, RGV = RGM = O.C., AV = 1, RLV = RLM = 150Ω, CLV = CLM = 3p, CH = 0.33n, GAIN = 1.

Parameter Description Conditions Min Typ Max Unit

Supply

I

+ Positive Supply Current 1 35 mA

S1

I

- Negative Supply Current VIN = 0, IL = 0 45 mA

S

I

+ Positive Supply Current 2 VIN = 0, IL = 0 141520mA

S2

I

+ Positive Supply Current 1 in Standby Standby 3.8 5 7.3 mA

S1S

I

- Negative Supply Current in Standby Standby 0.57 1 1.3 mA

SS

I

+ Positive Supply Current 2 in Standby Standby -10 - 10 µ A

S2S

V

+, VS2+ Positive Supply Voltage 4.5 5.0 5.5 V

S1

V

- Negative Supply Voltage -4.5 -5.0 -5.5 V

S

Input

Ib Input Bias Current V
Ibo Input Bias Current Drift with Temp. V
V

IH

V

IL

V

IP

V

IN

I

IDL

I

IDH

I

IL

I

IH

Input High Voltage 2V Input Low Voltage 0.8 V Input V oltage Swing, Pos. Saturated Input, Att. code = 01010 3.35 3.5 V Input V oltage Swing, Neg. Saturated Input, Att. code = 01010 -3.5 -3.39 V Low Input Current for SCLK and ENB VIN = 0V 50 85 150 µA High Input Current for SCLK and ENB VIN =5V 0 0.1 10 µ A Low Input Current for SDI, PDWN, HOLD VIN = 0V 15 48 75 µA

High Input Current for SDI, PDWN, HOLD VIN =5V 0 0.1 10 µ A
tsh Sample and Hold Delay Time 15 ns
tsu Data Set Up Time TBD 10 TBD ns
th Data Hold Time TBD 10 TBD ns
fclk Serial Clock Rate TBD 5 MHz
tsue Enable Set Up Time TBD 10 ns
the Enable Hold Time TBD 10 ns
tpd Clock to Data Output Delay C

Output

V

OSM

V

OS

T

CVOS

V

+ Output Voltage Swing, Pos. Attenuator = 0dB, Monitor & Video Outputs 3.44 3.5 V

O

V

- Output Voltage Swing, Neg. Attenuator = 0dB, Monitor & Video Outputs -3.5 -3.43 V

O

V

SDO

V

SDO

Output Offset Voltage - Monitor VIN = 0V -400 30 420 mV

DC-restore Offset Voltage auto-zero on, DC

Output Offset Voltage Drift - Video auto-zero on 15 µV/°C

high Serial Data Output High IL = +1mA 4.7 V low Serial Data Output Low IL = -1mA 0.25 V

= 0V -22.4 -2.2 6.1 µA

IN

= 0V TBD nA/°C

IN

= 10pF TBD 21 ns

L

= 0 -5 - 5 mV

REF

2

EL4102C - Preliminary

500MHz Video Front End: 4-1 MUX, VGA & DC-Restore

Electrical Characteristics

VS1+ = VS2+ = 5V, VS1- = VS2- = -5V, RFV = RFG = 750, RGV = RGM = O.C., AV = 1, RLV = RLM = 150Ω, CLV = CLM = 3p, CH = 0.33n, GAIN = 1.

Parameter Description Conditions Min Typ Max Unit

I

SC

AC Performance

SR Slew Rate - Video Out (20%-80%) V
SRM Slew Rate - Monitor Out (20%-80%) V
OS Output Overshoot, Video V
OSM Output Overshoot, Monitor V
ts Settling Time to 1%, Video Hold Mode TBD ns
tsm Settling Time to 1%, Monitor TBD ns
V

REF

tsd DC-restore - Settling Time to 1% Sample Mode On 1.2 µS
V

OHS

V

OSB

I

CCL

I

DC

BW 3dB Bandwidth, Video Out Attenuator = 00000 TBD MHz
BWM 3dB Bandwidth, Monitor Out TBD MHz

0.1BW ±0.1dB Flat Bandwidth, Video Out Attenuator = 00000 TBD MHz

0.1BWM ±0.1dB Flat Bandwidth, Monitor Out TBD MHz
Vp Peaking, Video TBD dB
Vpm Peaking, Monitor TBD dB
dP Diff. Phase @3.58MHz, Video TBD °
dG Diff. Gain @3.58MHz, Video TBD %
dPM Diff. Phase @3.58MHz, Monitor TBD °
dPG Diff. Gain @3.58MHz, Monitor TBD %
e

n

e

nm

1. Total unwanted output normalized by wanted (or expected) output; add -10dB to get channel-to-channel isolation

Output Short Circuit Current RL = 10Ω, Source or Sink 65 100 mA

= 4V

OUT

P-P

= 4V

OUT

P-P

= 1V

OUT

P-P

= 1V

OUT

P-P

DC-restore Reference Voltage Range VIN = -2V to +2V -2 - 2 V

DC-restore - Video Output Hold Step S - H Transition -1.1 mV DC-restore - Offset vs. Black Level Sample Mode On -1 -0.6 1 mV/V DC-restore - Charge Current Limit, I DC-restore - Droop Current, I

Noise Voltage at Input for V
Noise Voltage at Input for M

[1]

Crosstalk Crosstalk Attenuator Range - 18.2 - dB Attenuator Step Size 31 Steps - 0.58 - dB Relative Attenuation Error Between any 2 levels 0 - ±0.2 dB

@10MHz 3 channel hostile -45 dB

[1]

@100MHz 3 channel hostile -20 dB

CAP

CAP

OUT

OUT

Sample Mode On 260 µ A
Hold Mode On -30 - 30 nA

1000 2100 4500 V/µS 1250 2100 3900 V/µS

TBD %
TBD %

TBD nV/√Hz
TBD nV/√Hz

EL4102C - Preliminary

3

EL4102C - Preliminary

500MHz Video Front End: 4-1 MUX, VGA & DC-Restore

Serial Programming Truth Table

Inputs (X = Don’t Care)

Standby

MSB LSB

EL4102C - Preliminary

B7 B6 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 X X 0dB = 1.000 0 0 0 0 0 1 X X -0.6dB = 0.94 0 0 0 0 1 0 X X -1.2dB = 0.88 0 0 0 0 1 1 X X -1.7dB = 0.82 0 0 0 1 0 0 X X -2.3dB = 0.77 000101XX -2.9dB = 0.7 0 0 0 1 1 0 X X -3.5dB = 0.67 0 0 0 1 1 1 X X -4.1dB = 0.63 0 0 1 0 0 0 X X -4.6dB = 0.59 0 0 1 0 0 1 X X -5.2dB = 0.55 0 0 1 0 1 0 X X -5.8dB = 0.51 001011XX -6.4B = 0.48 0 0 1 1 0 0 X X -7.0dB = 0.45 0 0 1 1 0 1 X X -7.5dB = 0.42 0 0 1 1 1 0 X X -8.1dB = 0.39 0 0 1 1 1 1 X X -8.7dB = 0.37 0 1 0 0 0 0 X X -9.3dB = 0.34 0 1 0 0 0 1 X X -9.9dB = 0.32 0 1 0 0 1 0 X X -10.5dB = 0.30 0 1 0 0 1 1 X X -11.0dB = 0.28 0 1 0 1 0 0 X X -11.6dB = 0.26 0 1 0 1 0 1 X X -12.2dB = 0.25 0 1 0 1 1 0 X X -12.8dB = 0.23 0 1 0 1 1 1 X X -13.4dB = 0.22 0 1 1 0 0 0 X X -13.9dB = 0.20 0 1 1 0 0 1 X X -14.5dB = 0.19 0 1 1 0 1 0 X X -15.1dB = 0.18 0 1 1 0 1 1 X X -15.7dB = 0.17 0 1 1 1 0 0 X X -15.3dB = 0.15 0 1 1 1 0 1 X X -16.8dB = 0.14 0 1 1 1 1 0 X X -17.4dB = 0.13 0 1 1 1 1 1 X X -18.0dB = 0.12 0XXXXX1 1 IN3 Selected 0XXXXX1 0 IN2 Selected 0XXXXX0 1 IN1 Selected 0XXXXX0 0 IN0 Selected 1 X X X X X X X Standby Mode - Powered Down 1 1 1 1 1 1 1 1 Wake-up Condition (-18.0dB,

Attenuation

Input Selection

Attenuation

IN3, Powered Down)

4

Control Bits Logic Table

Bit Function

B7 Standby - Power Down
B6 Gain Bit 4
B5 Gain Bit 3
B4 Gain Bit 2
B3 Gain Bit 1
B2 Gain Bit 0
B1 Input Select Bit 1
B0 Input Select Bit 0

Serial Timing Diagram

ENB

t

t

HE

SE

EL4102C - Preliminary

500MHz Video Front End: 4-1 MUX, VGA & DC-Restore

Tt

r

t

t

f

t

HE

SE

EL4102C - Preliminary

SCLK

SDI

t

SD

t

HD

B7 B6 B5 B4-B2 B1 B0

MSB LSB

Load MSB first, LSB last

Serial Timing Parameters

Parameter Example Description

T ≥100 ns Clock Period

t

r/tf

t

HE

t

SE

t

HD

t

SD

t

w

t

w

0.05 x T Clock Rise/Fall Time

≥40ns ENB Hold Time
≥40ns ENB Setup Time
≥40ns Data Hold Time
≥40ns Data Setup Time

0.50 x T Clock Pulse Width

t

5

EL4102C - Preliminary

500MHz Video Front End: 4-1 MUX, VGA & DC-Restore

Pin Descriptions

Pin Number Pin Name Pin Type Pin Description

1 HOLD Lo gic Input Hold pulse for DC-restore function

EL4102C - Preliminary

2 GNDL2 Logic Ground Logic ground for “hold” buffer 3 IN0 High Frequency Signal Video input #0 4V 5 IN1 High Frequency Signal Video input #1 6 GNDI Analog Signal Intermediate reference for attenuation function 7 IN2 High Frequency Signal Video input #2 8V 0 IN3 High Frequency Signal Video input #3

10 ENB

11 SDI Logic Input Serial input data stream 12 SCLK Logic Input Serial data stream clock 13 SDO Logic Output Serial output data stream for connection to cascaded chip 14 P 15 GNDL Logic Ground Logic ground for logic buffers 16 M 17 M 18 V 19 V 20 V 21 V 22 DC 23 DC 24 CAP Analog Signal Sample storage capacitor for DC-restore circuit

+ Power Positive power pin for quiet supply currents

S1

- Power Negative power pin

S

Logic Input Enable (negative true) input for loading serial data stream

DWN

FDBK

OUT

- Power Negative power pin

S

+ Power Positive power pin for heavy, pulsatile supply currents

S2

OUT

FDBK

FDBK

REF

Logic Input Power down input to put chip in low current standby mode

High Frequency Signal Monitor amplifier feedback
High Frequency Signal Monitor amplifier output

High Frequency Signal Video amplifier output
High Frequency Signal Video amplifier feedback

Analog Signal Input to sample circuit Analog Signal Reference DC voltage representing black level

6

Block Diagram (Gain of 1)

Input Video

Input Video

Input Video

IN0

IN1

IN2

EL4102C - Preliminary

EL4102C - Preliminary

500MHz Video Front End: 4-1 MUX, VGA & DC-Restore

+

V

S

M

FDBK

­+

X

M

OUT

+

V

-

OUT

750

V

FDBK

DC

FDBK

+

-

DC

REF

750

Input Video

IN3

ENB

SDI

SCLK

GNDL GNDI GNDL2 VS-P

7

DWN

HOLD

CAP

SD0

C

H

EL4102C - Preliminary

500MHz Video Front End: 4-1 MUX, VGA & DC-Restore

Applications Information

Using the Serial Data Output Connection for a
Multi-chip Design

EL4102C - Preliminary

In a system design that uses three chips, (i.e. RGB,
YUV, YPrPb systems) the control signal may be "daisy
chained" through the three chips. This gives an advan­tage in that the control wil l be updated simult aneously
on the three channels.

Figure xx shows the control signal waveforms when
using this configur ation. Note, that the last data bit
clocked into the three chips occurs on the last positive
clock edge that is within the enabled period . This will be
D0 in the first chip, D8 and D16 on the second two
chips. The rising edge of /ENB will then simultaneously

The serial data out (SDO) of chip one is con nected to th e
serial data in (SDI) of chip two, similarly, chip two SDO
is connected to SDI on chip three. The clock (SCLK)
and enable (/ENB) signals are connected in parallel to all
three chips. See figure yy for suggested interconnect of
the control signals.

transfer the data internally to th e chip. Typicall y the data
for each chip is held as an image in the micro-co ntro ller
system; the load operati on would prepare the up date
information as a 24-bit word ready for shifting into the
three chips.

8

EL4102C - Preliminary

500MHz Video Front End: 4-1 MUX, VGA & DC-Restore

EL4102C - Preliminary

General Disclaimer

Specifications contained in this data sheet are in effect as of the publicat ion date shown. Elantec, Inc. re serves the r ight to make changes in th e cir­cuitry or specifications cont ained herein at a ny time without notice. Elantec , Inc. assumes no res ponsibili ty for t he us e of an y circuits descr ibed
herein and makes no representations that they are free from patent infringement.

WARNING - Life Support Policy

Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intend ed to sup-

Elantec Semiconductor, Inc.

675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: [phone]

(888) ELANTEC
Fax: [phone]
European Office: 44-118-977-6020
Japan Technical Center: 81-45-682-5820

port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users con­templating applicatio n of Elantec, Inc. P roducts in Li fe Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elan­tec, Inc.’s warranty is limited to replacement of defective
components and does not cov er injury to persons or prop erty or
other consequential damages.

August 30, 2001

9

Printed in U.S.A.