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®
DSD1700
©
1999 Burr-Brown Corporation PDS-1555A Printed in U.S.A. December, 1999
Direct Stream Digital™ (DSD™)
TM
Audio
DIGITAL-TO-ANALOG CONVERTER
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
DESCRIPTION
The DSD1700 is a unique digital-to-analog converter
designed for DSD audio applications. The DSD1700
consists of a single-channel, 8-tap analog FIR filter
constructed using a double differential circuit architecture, ensuring excellent dynamic performance and
high power- supply noise rejection. The DSD1700
also includes the necessary logic required to interface
directly to a DSD decoder IC.
The overall features and performance of the DSD1700
make it an ideal choice for high-performance Super
Audio CD players and DSD studio applications.
FEATURES
● DIRECT TRANSFER OF DSD DATA
STREAM TO ANALOG OUTPUT SIGNAL
● DUAL DIFFERENTIAL ANALOG FIR FILTER
● DIRECT, CMOS LOGIC INTERFACE TO
DSDTM DECODER IC
Data Clock: 2.8224 MHz (64 • 44.1kHz)
System Clock: 11.2896 MHz (256 • 44.1kHz)
● EXCELLENT DYNAMIC PERFORMANCE
THD+N: 0.001% (typ)
Dynamic Range: 110dB (typ)
SNR: 110dB (typ)
Frequency Response (–3dB): 100kHz
● SINGLE +5V SUPPLY OPERATION
● SMALL 28-LEAD SSOP PACKAGE
APPLICATIONS
● SUPER AUDIO CD (SACD™) PLAYERS
● PROFESSIONAL DSD PROCESSORS
● PROFESSIONAL DSD CONSOLES
For most current data sheet and other product
information, visit www.burr-brown.com
DSD I/F
PHASE
DATA
RST
DCK
SCK
V
DD
DGND
V
CC
AGND
Duty
Generator
Duty
Generator
Shift Register
(HOT)
Analog FIR
(HOT/P)
Analog FIR
(HOT/N)
Analog FIR
(COLD/N)
Analog FIR
(COLD/P)
Shift Register
(COLD)
V
DD
Timing
Generator
Power
Supply
V
DD
I
OUT
HP
I
OUT
HN
I
OUT
CP
I
OUT
CN
DSD1700
All trademarks are property of their respective owners.
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DSD1700
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
SPECIFICATIONS
All specifications TA = +25°C, VDD = VCC = 5.0V, fS = 44.1kHz, data clock = 64fS, system clock = 256fS, unless otherwise specified. (Although the sampling frequency
of Direct Stream Digital is 2.8224MHz, for convenience, in this specification sheet, it is described that the sampling frequency (f
S
) is 44.1kHz and the 2.8224MHz
clock is 64f
S
).
DSD1700E
PARAMETER CONDITIONS MIN TYP MAX UNITS
INPUT CLOCK
Data Clock Frequency (DCK) 64f
S
2.8224 MHz
System Clock Frequency (SCK) 256f
S
11.2896 MHz
SCK AC REQUIREMENT
(1)
Input Clock Duty Cycle 50 %
DIGITAL INPUT
High Level Input Voltage V
IH
0.7V
DD
V
Low Level Input Voltage V
IL
0.3V
DD
V
High Level Input Current I
IH
±10 µA
Low Level Input Current I
IL
(2)
±10 µA
I
IL
(3)
–120 µA
ANALOG OUTPUT
(5)
Full-Scale Voltage 4.1V
CC
Vp-p
Gain Error ±4 ±10 % of FSR
Offset Error ±0.1 ±1 % of FSR
Output Impedance
(4)
2kΩ
DYNAMIC PERFORMANCE
(5)
THD+N, V
OUT
= 0dB with 30kHz GIC Filter 0.001 %
Dynamic Range with 30kHz GIC Filter 110 dB
Signal-to-Noise Ratio with 30kHz GIC Filter 110 dB
Frequency Response, –3dB 100 kHz
POWER SUPPLY REQUIREMENTS
Voltage Range V
CC
, V
DD
4.5 5 5.5 VDC
Supply Current I
CC+IDD
VCC = VDD = 5.0V 5.5 8.0 mA
Power Dissipation V
CC
= VDD = 5.0V 27.5 40 mW
TEMPERATURE RANGE
Operating –25 +85 °C
Storage –55 +125 °C
Thermal Resistance θ
JA
28-Pin SSOP 100 °C/W
NOTES: (1) See description of system clock in the Functional Description section of this data sheet. (2) Pins 26, 27, 28: DATA. DCK. SCK. (3) Pins 3, 4: RST, PHASE
(with internal pull-up). (4) Pins 13, 14, 15, 16: I
OUT
HN, I
OUT
CP, I
OUT
CN, I
OUT
HP. (5) Measure DSD signal modulated f
SIG
= 1kHz with 50% scaling factor through
standard differential to single-ended converter (see Figure 10) using Audio Precision System II in rms mode with 20kHz LPF and 400Hz HPF.
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DSD1700
PIN CONFIGURATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
Supply Voltage
(2)
.............................................................................. +6.5V
Supply Voltage Differences
(3)
........................................................... ±0.1V
Ground Voltage Differences
(4)
.......................................................... ±0.1V
Digital Input Voltage ................................................... –0.3V to V
DD
+0.3V
Input Current (any pins except supplies) ....................................... ±10mA
Operating Temperature .................................................... –25°C to +85°C
Storage Temperature .....................................................–55°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 5s) ................................................. +260°C
Package Temperature (IR reflow, peak, 10s) ............................... +235°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. (2) V
CC
, VDD. (3) Among VCC, VDD. (4) Among AGND, DGND.
ABSOLUTE MAXIMUM RATINGS
(1)
Top View SSOP
PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER
(1)
MEDIA
DSD1700E 28-Lead SSOP 324 0°C to +70°C DSD1700E DSD1700E Rails
"""""DSD1700E/2K Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “DSD1700E/2K” will get a single 2000-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
DGND
V
DD
RST
PHASE
AGND
V
CC
AGND
V
CC
V
CC
AGND
V
CC
AGND
I
OUT
HN
I
OUT
CP
SCK
DCK
DATA
AGND
V
CC
AGND
V
CC
V
CC
AGND
V
CC
AGND
AGND
I
OUT
HP
I
OUT
CN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DSD1700
PIN NAME I/O DESCRIPTION
1 DGND — Digital Ground
2V
DD
— Digital Power Supply: +5V
3 RST IN Reset Control Input, Active LOW
(1)
4 PHASE IN Select data phase
(LOW = Normal; HIGH = Invert)
5 AGND — Analog Ground
6V
CC
— Analog Power Supply: +5V
7 AGND — Analog Ground
8V
CC
— Analog Power Supply: +5V
9V
CC
— Analog Power Supply: +5V
10 AGND — Analog Ground
11 V
CC
— Analog Power Supply: +5V
12 AGND — Analog Ground
13 I
OUT
HN OUT Analog Output from DAC (Hot Negative)
14 I
OUT
CP OUT Analog Output from DAC (Cold Positive)
15 I
OUT
CN OUT Analog Output from DAC (Cold Negative)
16 I
OUT
HP OUT Analog Output from DAC (Hot Positive)
17 AGND — Analog Ground
18 AGND — Analog Ground
19 V
CC
— Analog Power Supply: +5V
20 AGND — Analog Ground
21 V
CC
— Analog Power Supply: +5V
22 V
CC
— Analog Power Supply: +5V
23 AGND — Analog Ground
24 V
CC
— Analog Power Supply: +5V
25 AGND — Analog Ground
26 DATA IN Direct Stream Digital Data Input
27 DCK IN Data Clock Input
28 SCK IN System Clock Input
NOTE: (1) With internal pull-up resistor
PIN ASSIGNMENTS
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DSD1700
GENERAL INFORMATION
The DSD1700 is designed solely for use in DSD and SACD
applications. It is not compatible with standard CD audio
transports, or DVD/MPEG-2 decoders. Burr-Brown manufacturers a wide array of products for these applications.
Please refer to our audio brochure and product data sheets,
available from our web site (www.burr-brown.com) and
local sales offices.
FUNCTIONAL DESCRIPTION
The concept of Direct Stream Digital (DSD) conversion is
simple. An analog audio input is digitized by a 1-bit, 64x
oversampled delta-sigma modulator. The 1-bit data stream is
then stored and may be transferred to a SACD disc at a later
time. For playback, the 1-bit, 64x oversampled data is then
presented to the DSD1700 directly by a DSD decoder IC.
The DSD1700 then low-pass filters the oversampled data to
reconstruct the original analog audio waveform. The recording and playback functions are illustrated in Figures 1 and 2
respectively.
To perform the digital-to-analog conversion, the DSD1700
includes both the decoder interface logic and an analog FIR
filter. The following paragraphs provide a summary of these
functions.
FIGURE 1. DSD Recording.
FIGURE 2. DSD Playback.
DECODER INTERFACE
The decoder interface consists of several CMOS logic inputs. The system clock input, SCK (pin 28), operates at
11.2896MHz (256 • 44.1kHz). The data bit clock, DCK
(pin 27), operates at 2.8244 MHz (64 • 44.1kHz) and is the
64x oversampled data clock. The 1-bit, 64x oversampled
data stream is input at DATA (pin 26). DATA and DCK are
synchronized to the SCK falling edge.
The DSD1700 generates HOT and COLD data internally for
use with the double differential analog FIR filter. The
PHASE input (pin 4) is used to determine the polarity of the
HOT and COLD data (normal or inverted). The PHASE
input is synchronized to the rising edge of SCK.
The RST input (pin 3) is used for system reset purposes.
RST should be High for normal operation, and Low for reset
operation. When RST is held Low, the current outputs of the
analog FIR filter are set to the bipolar zero (BPZ) level. The
RST signal is synchronized to the rising edge of SCK.
TIMING
Figures 3 though 6 show the timing diagrams for the
DSD1700 interface signals. Figure 3 shows the system clock
(SCK) timing requirements. Figure 4 shows the general
timing for the data input. Figures 5 and 6 show the detailed
timing for the DSD data and control data inputs.
LOGIC
DSD
Input
(64f
S
, 1-Bit)
Analog
Output
Low-Pass
Filter
Interface
Logic
FIGURE 3. System Clock Timing.
FIGURE 4. Input Signal Timing.
t
SCKH
t
SCKL
1/256 f
S
V
IH
V
IL
High
Low
System Clock
VIH = 0.7V
DD
VIL = 0.3V
DD
∫
Q
Analog
Input
DSD
Output
(64f
S
, 1-Bit)
Loop Filter
(Noise Shaping
and Integration)
1-Bit
Quantizer
+
–
DATA
SCK (256f
S
)
DCK (64f
S
)
RST
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
SCKH
System Clock Pulse Width High 10 ns
t
SCKL
System Clock Pulse Width Low 10 ns
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®
DSD1700
DCK
SCK
DATA
t
DCH
t
DAH
t
DAS
t
DCS
t
SCWH
t
SCWL
t
SCY
PHASE
SCK
RST
t
PH
t
RH
t
RS
t
PS
t
SCWL
t
SCWH
t
SCY
FIGURE 5. DSD Data Input Timing.
FIGURE 6. Control Data Input Timing.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
SCWH
SCK Pulse Width High 10 ns
t
SCWL
SCK Pulse Width Low 10 ns
t
SCY
SCK Pulse Cycle Time 1/(256fS)sec
t
DCS
DCK Setup Time 15 ns
t
DCH
DCK Hold Time 5 ns
t
DAS
DATA Setup Time 15 ns
t
DAH
DATA Hold Time 5 ns
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
SCWH
SCK Pulse Width High 10 ns
t
SCWL
SCK Pulse Width Low 10 ns
t
SCY
SCK Pulse Cycle Time 1/(256fS) sec
t
PS
PHASE Setup Time 15 ns
t
PH
PHASE Hold Time 5 ns
t
RS
RST Setup Time 15 ns
t
RH
RST Hold Time 5 ns
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DSD1700
D0
R0
D1
R1
D2
R2
D3
R3
D4
R4
D5
R5
D6
R6
D7
R7
I
OUT
FIGURE 7. Analog FIR Filter Structure.
FIGURE 8. Analog FIR Filter Frequency Response.
FREQUENCY RESPONSE
(DC – 1.4112MHz)
Frequency (Hz)
Gain (dB)
705,600 1,411,2000
0
–50
–100
FREQUENCY RESPONSE
(DC – 11.2896MHz)
Frequency (Hz)
Gain (dB)
5,644,800 11,289,6000
0
–50
–100
ANALOG FIR FILTER
The low-pass filter function for the DSD1700 is constructed
by using four 8-tap, analog FIR filters with current outputs.
The four filters include one each for HOT and COLD
positive, and one each for HOT and COLD negative. This is
referred to as a double differential architecture. These filters
use resistors to set the filter coefficients, as shown in
Figure 7. Prior to the analog FIR filters, the duty cycle of the
DSD input signal is set to 75% by the DSD1700’s duty
generators.
Plots of the analog FIR filter response is shown in Figure 8.
The stop-band attenuation of the filters dictates that additional low-pass filtering is required at the output of the
external current-to-voltage converter circuit (see Figure 10).
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®
DSD1700
FIGURE 9. Basic Connection Diagram.
DGND
V
DD
RST
PHASE
AGND
V
CC
AGND
V
CC
V
CC
AGND
V
CC
AGND
I
OUT
HN
I
OUT
CP
SCK
DCK
DATA
AGND
V
CC
AGND
V
CC
V
CC
AGND
V
CC
AGND
AGND
I
OUT
HP
I
OUT
CN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DSD1700
Direct
Stream
Digital
™
Data
System Clock
System Reset
C
1
C
6
C
7
C
8
C
9
C
1
C
3
C
4
C
5
Phase Control
+5V
NOTE: C
1
= 0.1µF ceramic and 1-100µF. C2 - C9 = 0.1µF ceramic each and 1-100µF chemical.
Analog
Ground
=
FIGURE 10. Recommended I/V Conversion Circuit.
APPLICATIONS INFORMATION
TYPICAL CONNECTIONS
Figure 9 shows the basic connection diagram for the
DSD1700. A significant number of power supply bypass
capacitors are required, and Burr-Brown recommends the
indicated values for optimal performance.
CURRENT-TO-VOLTAGE (I/V)
CONVERTER CIRCUIT
The DSD1700 is a current output device, and requires an
I/V conversion circuit to transform the double-differential
outputs into a usable voltage output. The circuit in Figure 10
is recommended for this purpose. Op amps are OPA134 or
equivalent.
+18V
–18V
OPA134
6
1
4
3
2
7
0.1µF
0.1µF
0.1µF
100pF
0.1µF
4.7kΩ
Analog
Out
220pF
4.7kΩ
+18V
+5V
–18V
OPA134
6
1
4
3
2
7
4.7kΩ
+18V
–18V
OPA134
6
1
4
3
2
7
4.7kΩ
4.7kΩ
8.2 kΩ
8.2 kΩ
100pF
1kΩ
1kΩ
1kΩ
1kΩ
470pF
470pF
220pF
I
OUT
CN
I
OUT
HP
I
OUT
HN
I
OUT
CP
4.7kΩ
Analog
Ground
=
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DSD1700
FIGURE 11. Recommended PCB Layout Technique.
DSD1700
V
CC
V
DD
DGND
Return Path for Digital Signals
Analog
Ground
Digital
Ground
AGND
Output
Circuits
DIGITAL SECTION ANALOG SECTION
DSD
™
Decoder
and
Control Logic
Digital Power
+V
D
DGND
Analog Power
+5VA +V
S
AGND –V
S
PRINTED CIRCUIT BOARD LAYOUT
A typical PCB floor plan for the DSD1700 is shown in
Figure 11. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a
split in the plane. The DSD1700 should be oriented with the
digital I/O pins facing the ground plane split/cut, allowing
for direct connection to the DSD decoder and control signals
originating from the digital section of the board.
Separate power supplies are recommended for the digital
and analog sections of the board. This prevents the switching
noise present on the digital supply from contaminating the
analog power supply and degrading the dynamic performance of the DSD1700.
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