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GENERAL DESCRIPTION
The DS1337 serial real-time clock is a low-power
clock/calendar with two programmable time-of-day
alarms and a programmable square-wave output.
Address and data are transferred serially via a 2-wire,
bidirectional bus. The clock/calendar provides
seconds, minutes, hours, day, date, month, and year
information. The date at the end of the month is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator.
APPLICATIONS
Handhelds (GPS, POS Terminal, MP3 Player)
Consumer Electronics (Set-Top Box, VCR/Digital
Recording)
Office Equipment (Fax/Printer, Copier)
Medical (Glucometer, Medicine Dispenser)
Telecommunications (Router, Switcher, Server)
Other (Utility Meter, Vending Machine, Thermostat,
Modem)
TYPICAL OPERATING CIRCUIT
DS1337
Serial Real-Time Clock
FEATURES
§ Real-Time Clock (RTC) Counts Seconds,
Minutes, Hours, Day, Date, Month, and Year
with Leap-Year Compensation Valid Up to 2100
§ Two-Wire Serial Interface
§ Two Time-of-Day Alarms
§ Oscillator Stop Flag
§ Programmable Square-Wave Output
– Defaults to 32kHz on Power-Up
§ Available in 8-Pin DIP, SO, or mSOP
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS1337 -40°C to +85°C 8 DIP (300mil) DS1337
DS1337S -40°C to +85°C 8 SO (150mil) DS1337
DS1337U -40°C to +85°C
8 mSOP
PIN CONFIGURATIONS
TOP VIEW
X1
X2
GND
DS1337
X1
X2
INT
GND
DIP
DS1337
SO, mSOP
VCC
SQW/INTB
SCL
SDA
VCC
SCL
SDA
TOP
MARK
1337
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
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REV: 012003
.
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DS1337
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperature Range -40°C to +85°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature Range See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +85°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC 1.8 4.0 V
Oscillator Voltage V
Logic 1 VIH
Logic 0 VIL
1.3 4.0 V
OSC
SCL, SDA 0.7 VCC VCC + 0.3
INTA, SQW/INTB
-0.3 0.3 V
5.5
CC
V
V
DC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V to 4.0V, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Leakage ILI
I/O Leakage ILO
Logic 0 Output (VOL = 0.4V) IOL (Note 2) 3 mA
Active Supply Current I
Standby Current I
CCA
CCS
(Note 1) 1
(Note 2) 1
(Note 3) 150
(Notes 4, 5) 2
mA
mA
mA
mA
DC ELECTRICAL CHARACTERISTICS
(VCC = 1.3V to 1.8V, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Timekeeping Current
(Oscillator Enabled)
Data Retention Current
(Oscillator Disabled)
I
(Notes 4, 6, 7) 600 nA
OSC
I
(Note 4) 50 nA
DDR
CRYSTAL SPECIFICATIONS*
PARAMETER SYMBOL MIN TYP MAX UNITS
Nominal Frequency FO 32.768 kHz
Series Resistance ESR 45 kΩ
Load Capacitance CL 6 pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations
for Dallas Real-Time Clocks for additional specifications.
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AC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V to 4.0V, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DS1337
SCL Clock Frequency f
Bus Free Time Between a
STOP and START Condition
Hold Time (Repeated)
START Condition (Note 8)
t
LOW Period of SCL Clock t
HIGH Period of SCL Clock t
Setup Time for a Repeated
START Condition
t
Data Hold Time (Notes 9, 10) t
Data Setup Time (Note 11) t
Rise Time of Both SDA and
SCL Signals (Note 12)
Fall Time of Both SDA and
SCL Signals (Note 12)
Condition
t
Capacitive Load for Each Bus
Line
SCL
Standard mode 100
kHz
Fast mode 100 400
Fast mode 1.3
t
BUF
Standard mode 4.7
Fast mode 0.6
HD:STA
LOW
HIGH
Standard mode 4.0
Fast mode 1.3
Standard mode 4.7
Fast mode 0.6
Standard mode 4.0
Fast mode 0.6
SU:STA
HD:DAT
SU:DAT
Standard mode 4.7
Fast mode 0 0.9
Standard mode 0
Fast mode 100
Standard mode 250
Fast mode 20 + 0.1CB 300
t
R
Standard mode 1000
Fast mode 20 + 0.1CB 300
t
F
SU:STO
C
B
Standard mode 300
Fast mode 0.6 Setup Time for STOP
Standard mode 4.0
(Note 12) 400 pF
ms
ms
ms
ms
ms
ms
ns
ns
ns
ms
I/O Capacitance C
Note 1: SCL only.
Note 2: SDA, INTA, and SQW/INTB.
Note 3: I
Note 4: Specified with 2-wire bus inactive, V
Note 5: SQW enabled.
Note 6: Specified with the SQW function disabled by setting INTCN = 1.
Note 7: Using recommended crystal on X1 and X2.
Note 8: After this period, the first clock pulse is generated.
Note 9: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
Note 10: The maximum t
Note 11: A fast-mode device can be used in a standard-mode system, but the requirement t
Note 12: C
—SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = V
CCA
bridge the undefined region of the falling edge of SCL.
HD:DAT
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
released.
—total capacitance of one bus line in pF.
B
has only to be met if the device does not stretch the LOW period (t
10 pF
I/O
= 0.0V, VIH = V
IL
CC.
CC.
R max + tSU:DAT
) of the SCL signal.
LOW
³ to 250ns must then be met. This is
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is
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of the SCL signal) in order to
IHMIN
Page 4
TYPICAL OPERATING CHARACTERISTICS
(VCC = 3.3V, TA = +25∞ C, unless otherwise noted.)
I
VS. V
500
(SQUARE-WAVE OFF)
450
400
SUPPLY CURRENT (nA)
350
300
1.3
OSC
CC
DS1337 toc01
4.84.33.83.32.31.8
V
(V)
BAT
850
800
750
700
650
600
550
500
SUPPLY CURRENT (nA)
450
400
350
I
VS. V
OSC
CC
(SQUARE-WAVE ON)
V
(V)
BAT
DS1337
DS1337 toc02
4.84.33.83.32.31.81.3
I
OSC
(SQUARE-WAVE OFF)
475
450
425
400
SUPPLY CURRENT (nA)
375
350
-40
VS. TEMPERATURE
VCC = 3.0V
TEMPERATURE ( C)
32767.75
32767.70
32767.65
275
DS1337 toc03
806040200-20
250
225
200
175
150
125
SUPPLY CURRENT (mA)
100
75
50
1.8 5.3
OSCILLATOR FREQUENCY vs. V
VCC = 0V
I
CCA
(SQUARE-WAVE ON)
VCC (V)
CC
DS1337 toc05
vs. V
CC
DS1337 toc04
4.84.33.3 3.82.82.3
32767.60
FREQUENCY (Hz)
32767.55
32767.50
32767.45
1.3 4.8
V
BACKUP
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4.33.83.32.82.31.8
(V)
Page 5
PIN DESCRIPTION
PIN NAME DESCRIPTION
These signals are connections for a standard 32.768kHz quartz crystal. The internal
1 X1
2 X2
3
4 GND DC power is provided to the device on these pins.
5 SDA
6 SCL Serial Clock Input. SCL is used to synchronize data movement on the serial interface.
INTA
oscillator circuitry is designed for operation with a crystal having a specified load
capacitance (C
considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-
Time Clocks. An external 32.768kHz oscillator can also drive the DS1337. In this
configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is
floated.
Interrupt Output. When enabled, INTA is asserted low when the time/day/date matches
the values set in the alarm registers. This pin is an open-drain output and requires an
external pullup resistor.
Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The
SDA pin is open-drain output and requires an external pullup resistor.
) of 6pF. For more information about crystal selection and crystal layout
L
DS1337
7
8 VCC DC power is provided to the device on these pins.
SQW/
INTB
Square-Wave/Interrupt Output. Programmable square-wave or interrupt output signal. It
is an open-drain output and requires an external pullup resistor.
Figure 1. Recommended Layout for Crystal
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Figure 2. Timing Diagram
DS1337
OPERATION
The block diagram in Figure 3 shows the main elements of the DS1337. As shown, communications to
and from the DS1337 occur serially over a 2-wire, bidirectional bus. The DS1337 operates as a slave
device on the serial bus. Access is obtained by implementing a START condition and providing a device
identification code, followed by data. Subsequent registers can be accessed sequentially until a STOP
condition is executed.
Figure 3. Block Diagram
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DS1337
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Crystal frequency drift caused by temperature shifts creates additional error. External circuit
noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application Note 58:
Crystal Considerations with Dallas Real-Time Clocks for detailed information.
ADDRESS MAP
The address map for the registers of the DS1337 is shown in Table 1. During a multibyte access, when
the address pointer reaches the end of the register space (0Fh) it wraps around to location 00h. On a 2wire START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a
second set of registers. The time information is read from these secondary registers, while the clock may
continue to run. This eliminates the need to re-read the registers in case of an update of the main registers
during a read.
Table 1. Timekeeper Registers
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE
00H 0 10 Seconds Seconds Seconds 00-59
01H 0 10 Minutes Minutes Minutes 00-59
AM/PM
02H 0 12/24
03H 0 0 0 0 0 Day Day 1-7
04H 0 0 10 Date Date Date 00-31
05H Century 0 0 10 Mo Month
06H 10 Year Year Year 00-99
07H A1M1 10 Seconds Seconds
08H A1M2 10 Minutes Minutes
09H A1M3 12/24
0AH A1M4 DY/DT
0BH A2M2 10 Minutes Minutes
0CH A2M3 12/24
0DH A2M4 DY/DT
0EH
0FH OSF 0 0 0 0 0 A2F A1F Status
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied or VCC falls below the V
EOSC
0 0 RS2 RS1 INTCN A2IE A1IE Control
10hr
AM/PM
10hr
10 DATE
AM/PM
10hr
10hr Hour Hours
Month/
Century
Alarm 1
Seconds
Alarm 1
Minutes
10hr Hour
10hr Hour
10 Date
Day
Date
Day
Date
Alarm 1
Hours
Alarm 1
Day
Alarm 1
Date
Alarm 2
Minutes
Alarm 2
Hours
Alarm 2
Day
Alarm 2
Date
OSC
1-12
+AM/PM
00-23
01-12 +
Century
00-59
00-59
1-12 +
AM/PM
00-23
1-7
1-31
00-59
1-12 +
AM/PM
00-23
1-7
1-31
.
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DS1337
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. The RTC
registers are illustrated in Table 1. The time and calendar are set or initialized by writing the appropriate
register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD)
format.
The day-of-week register increments at midnight. Values that correspond to the day of week are userdefined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time
and date entries result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors
when the internal registers update. When reading the time and date registers, the user buffers are
synchronized to the internal registers on any start or stop and when the register pointer rolls over to zero.
The countdown chain is reset whenever the seconds register is written. Write transfers occur on the
acknowledge pulse from the device. To avoid rollover issues, once the countdown chain is reset, the
remaining time and date registers must be written within 1 second. The 1Hz square-wave output, if
enable, transitions high 500ms after the seconds data transfer, provided the oscillator is already running.
The DS1337 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23
hours). The century bit (bit 7 of the month register) is toggled when the years register overflows from
99–00.
ALARMS
The DS1337 contains two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h–0Ah.
Alarm 2 can be set by writing to registers 0Bh–0Dh. The alarms can be programmed (by the INTCN bit
of the control register) to operate in two different modes—each alarm can drive its own separate interrupt
output or both alarms can drive a common interrupt output. Bit 7 of each of the time-of-day/date alarm
registers are mask bits (Table 2). When all of the mask bits for each alarm are logic 0, an alarm only
occurs when the values in the timekeeping registers 00h–06h match the values stored in the time-ofday/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day,
or date. Table 2 shows the possible settings. Configurations not listed in the table result in illogical
operation.
The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0–5
of that register reflects the day of the week or the date of the month. If DY/DT is written to logic 0, the
alarm is the result of a match with date of the month. If DY/DT is written to logic 1, the alarm is the
result of a match with day of the week.
When the RTC register values match alarm register settings, the corresponding alarm flag (A1F or A2F)
bit is set to logic 1. If the corresponding alarm interrupt enable (A1IE or A2IE) is also set to logic 1, the
alarm condition activates one of the interrupt output (INTA or SQW/INTB) signals. The match is tested
on the once-per-second update of the time and date registers.
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DS1337
Table 2. Alarm Mask Bits
ALARM 1 REGISTER MASK BITS
DY/DT
A1M4 A1M3 A1M2 A1M1
X 1 1 1 1 Alarm once per second
X 1 1 1 0 Alarm when seconds match
X 1 1 0 0 Alarm when minutes and seconds match
X 1 0 0 0 Alarm when hours, minutes, and seconds match
0 0 0 0 0
1 0 0 0 0 Alarm when day, hours, minutes, and seconds match
ALARM 2 REGISTER MASK BITS
DY/DT
A2M4 A2M3 A2M2
X 1 1 1 Alarm once per minute (00 seconds of every minute)
X 1 1 0 Alarm when minutes match
X 1 0 0 Alarm when hours and minutes match
0 0 0 0 Alarm when date, hours, and minutes match
1 0 0 0 Alarm when day, hours, and minutes match
(BIT 7)
(BIT 7)
ALARM RATE
Alarm when date, hours, minutes, and seconds
match
ALARM RATE
SPECIAL PURPOSE REGISTERS
The DS1337 has two additional registers (control and status) that control the RTC, alarms, and squarewave output.
Control Register (0Eh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EOSC
0 0 RS2 RS1 INTCN A2IE A1IE
EOSC, Enable Oscillator. This bit when set to logic 0 starts the oscillator. When this bit is set to logic 1, the
oscillator is stopped. This bit is enabled (logic 0) when power is first applied.
RS2 and RS1, Rate Select. These bits control the frequency of the square-wave output when the square wave has
been enabled. Table 3 shows the square-wave frequencies that can be selected with the RS bits. These bits are both
set to logic 1 (32kHz) when power is first applied.
Table 3. Square-Wave Output Frequency
RS2 RS1
0 0 1Hz
0 1 4.096kHz
1 0 8.192kHz
1 1 32.768kHz
INTCN, Interrupt Control. This bit controls the relationship between the two alarms and the interrupt output
pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers l
activates the INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the
SQUARE-WAVE OUTPUT
FREQUENCY
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DS1337
alarm 2 registers activates the SQW/INTB pin (provided that the alarm is enabled). When the INTCN bit is set to
logic 0, a match between the timekeeping registers and either alarm 1 or alarm 2 registers activates the INTA pin
(provided that the alarms are enabled). In this configuration, a square wave is output on the SQW/INTB pin. This
bit is set to logic 0 when power is first applied.
A1IE, Alarm 1 Interrupt Enable. When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status
register to assert
INTA . When the A1IE bit is set to logic 0, the A1F bit does not initiate the INTA signal. The
A1IE bit is disabled (logic 0) when power is first applied.
A2IE, Alarm 2 Interrupt Enable. When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status
register to assert INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1). When the A2IE bit is set to
logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first
applied.
Status Register (0Fh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OSF 0 0 0 0 0 A2F A1F
OSF, Oscillator Stop Flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for
some period of time and may be used to judge the validity of the clock and calendar data. This bit is set to logic 1
anytime that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on V
is insufficient to support oscillation.
CC
3) The EOSC bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0.
A1F, Alarm 1 Flag. A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the
A1IE bit is also logic 1, the INTA pin goes low. A1F is cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
A2F, Alarm 2 Flag. A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. This
flag can be used to generate an interrupt on either INTA or SQW/INTB depending on the status of the INTCN bit
in the control register. If the INTCN bit is set to logic 0 and A2F is at logic 1 (and A2IE bit is also logic 1), the
INTA pin goes low. If the INTCN bit is set to logic 1 and A2F is logic 1 (and A2IE bit is also logic 1), the
SQW/INTB pin goes low. A2F is cleared when written to logic 0. This bit can only be written to logic 0.
Attempting to write to logic 1 leaves the value unchanged.
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DS1337
2-WIRE SERIAL DATA BUS
The DS1337 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls
the message is called a master. The devices that are controlled by the master are referred to as slaves. A
master device that generates the serial clock (SCL), controls the bus access, and generates the START
and STOP conditions must control the bus. The DS1337 operates as a slave on the 2-wire bus. Within the
bus specifications a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum
clock rate) are defined. The DS1337 works in both modes. Connections to the bus are made through the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 4):
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is
HIGH, defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions are not limited, and are
determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
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DS1337
Figure 4. Data Transfer On 2-Wire Serial Bus
Depending upon the state of the R/W bit, two types of data transfer are possible:
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte. Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte
(the slave address). The slave then returns an acknowledge bit, followed by the slave transmitting a
number of data bytes. The master returns an acknowledge bit after all received bytes other than the
last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device
generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with
a STOP condition or with a repeated START condition. Since a repeated START condition is also the
beginning of the next serial transfer, the bus is not released. Data is transferred with the most
significant bit (MSB) first.
The DS1337 can operate in the following two modes:
1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL.
After each byte is received an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction bit (Figure 5). The slave address byte is
the first byte received after the master generates the START condition. The slave address byte
contains the 7-bit DS1337 address, which is 1101000, followed by the direction bit (R/W), which, for
a write, is 0. After receiving and decoding the slave address byte the device outputs an acknowledge
on the SDA line. After the DS1337 acknowledges the slave address + write bit, the master transmits a
word address to the DS1337. This sets the register pointer on the DS1337. The master may then
transmit 0 or more bytes of data, with the DS1337 acknowledging each byte received. The master
generates a STOP condition to terminate the data write.
2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction bit indicates that the transfer direction is
reversed. Serial data is transmitted on SDA by the DS1337 while the serial clock is input on SCL.
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START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 6).
The slave address byte is the first byte received after the master generates a START condition. The
slave address byte contains the 7-bit DS1337 address, which is 1101000, followed by the direction bit
(R/W), which, for a read, is 1. After receiving and decoding the slave address byte the device outputs
an acknowledge on the SDA line. The DS1337 then begins to transmit data starting with the register
address pointed to by the register pointer. If the register pointer is not written to before the initiation
of a read mode the first address that is read is the last one stored in the register pointer. The DS1337
must receive a “not acknowledge” to end a read.
Figure 5. Data Write: Slave Receiver Mode
Figure 6. Data Read: Slave Transmitter Mode
DS1337
CHIP INFORMATION
Transistor Count: 10,950
Process: CMOS
PACKAGE INFORMATION
For the latest package outline information, go to www.maxim-ic.com/dallaspackinfo.
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