Page 1
DS1330W
3.3V 256K Nonvolatile SRAM
with Battery Monitor
DS1330W
PRELIMINARY
022598 1/11
FEATURES
• 10 years minimum data retention in the absence of
external power
• Data is automatically protected during power loss
• Power supply monitor resets processor when V
CC
power loss occurs and holds processor in reset during
V
CC
ramp–up
• Battery monitor checks remaining capacity daily
• Read and write access times as fast as 150 ns
• Unlimited write cycle endurance
• Typical standby current 50 µA
• Upgrade for 32K x 8 SRAM, EEPROM or Flash
• Lithium battery is electrically disconnected to retain
freshness until power is applied for the first time
• Optional industrial temperature range of –40°C to
+85°C, designated IND
• New PowerCap Module (PCM) package
– Directly surface–mountable module
– Replaceable snap–on PowerCap provides lith-
ium backup battery
– Standardized pinout for all nonvolatile SRAM
products
– Detachment feature on PowerCap allows easy
removal using a regular screwdriver
PIN ASSIGNMENT
BW
OE
CE
WE
RST
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
34
33
32
31
30
29
28
27
26
25
24
23
22
14
15
16
17
21
20
19
18
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC
NC
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
34–PIN POWERCAP MODULE (PCM)
GND V
BAT
(USES DS9034PC POWERCAP)
PIN DESCRIPTION
A0–A14 – Address Inputs
DQ0–DQ7 – Data In/Data Out
CE – Chip Enable
WE – Write Enable
OE – Output Enable
RST
– Reset Output
BW – Battery Warning Output
V
CC
– Power (+3.3 Volts)
GND – Ground
NC – No Connect
DESCRIPTION
The DS1330W 3.3V 256K Nonvolatile SRAM is a
262,144–bit, fully static, nonvolatile SRAM organized
as 32,768 words by eight bits. Each NV SRAM has a
self–contained lithium energy source and control circuitry which constantly monitors V
CC
for an out–of–tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent
data corruption. Additionally, the DS1330W has dedicated circuitry for monitoring the status of VCC and the
status of the internal lithium battery. DS1330W devices
in the PowerCap Module package are directly surface
mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. The devices can be used in place of 32K x 8 SRAM,
EEPROM or Flash components.
Page 2
DS1330W
022598 2/11
READ MODE
The DS1330W executes a read cycle whenever WE
(Write Enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique
address specified by the 15 address inputs (A
0
– A14)
defines which of the 32,768 bytes of data is to be
accessed. Valid data will be available to the eight data
output drivers within t
ACC
(Access Time) after the last
address input signal is stable, providing that CE and OE
(Output Enable) access times are also satisfied. If OE
and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or
OE) and the limiting parameter is either tCO for CE or t
OE
for OE rather than address access.
WRITE MODE
The DS1330W excutes a write cycle whenever the WE
and CE signals are in the active (low) state after address
inputs are stable. The later occurring falling edge of CE
or WE will determine the start of the write cycle. The
write cycle is terminated by the earlier rising edge of CE
or WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (t
WR
) before another cycle can
be initiated. The OE
control signal should be kept inactive (high) during write cycles to avoid bus contention.
However, if the output drivers are enabled (CE
and OE
active) then WE will disable the outputs in t
ODW
from its
falling edge.
DATA RETENTION MODE
The DS1330W provides full functional capability for V
CC
greater than 3.0 volts and write protects by 2.8 volts.
Data is maintained in the absence of V
CC
without any
additional support circuitry . The nonvolatile static RAMs
constantly monitor VCC. Should the supply voltage
decay, the NV SRAMs automatically write protect themselves, all inputs become “don’t care,” and all outputs
become high impedance. As V
CC
falls below approximately 2.5 volts, the power switching circuit connects
the lithium energy source to RAM to retain data. During
power–up, when VCC rises above approximately
2.5 volts, the power switching circuit connects external
VCC to the RAM and disconnects the lithium energy
source. Normal RAM operation can resume after V
CC
exceeds 3.0 volts.
SYSTEM POWER MONITORING
The DS1330W has the ability to monitor the external
VCC power supply. When an out–of–tolerance power
supply condition is detected, the NV SRAM warns a processor–based system of impending power failure by
asserting RST
. On power up, RST is held active for 200
ms nominal to prevent system operation during power–on transients and to allow t
REC
to elapse. RST has
an open–drain output driver.
BATTERY MONITORING
The DS1330W automatically performs periodic battery
voltage monitoring on a 24 hour time interval. Such
monitoring begins within t
REC
after VCC rises above V
TP
and is suspended when power failure occurs.
After each 24 hour period has elapsed, the battery is
connected to an internal 1 MΩ test resistor for one
second. During this one second, if battery voltage falls
below the battery voltage trip point (2.6V), the battery
warning output BW
is asserted. Once asserted, BW
remains active until the module is replaced. The battery
is still retested after each VCC power–up, however, even
if BW is active. If the battery voltage is found to be higher
than 2.6V during such testing, BW is de–asserted and
regular 24–hour testing resumes. BW has an open–
drain output driver.
FRESHNESS SEAL
Each DS1330W is shipped from Dallas Semiconductor
with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a
level greater than VTP, the lithium energy source is
enabled for battery backup operation.
PACKAGES
The 34–pin PowerCap Module integrates SRAM
memory and nonvolatile control into a module base
along with contacts for connection to the lithium battery
in the DS9034PC PowerCap. The PowerCap Module
package design allows a DS1330W device to be surface mounted without subjecting its lithium backup battery to destructive high–temperature reflow soldering.
After a DS1330W module base is reflow soldered, a
DS9034PC is snapped on top of the base to form a complete Nonvolatile SRAM module. The DS9034PC is
keyed to prevent improper attachment. DS1330W module bases and DS9034PC PowerCaps are ordered separately and shipped in separate containers. See the
DS9034PC data sheet for further information.
Page 3
DS1330W
022598 3/11
ABSOLUTE MAXIMUM RATINGS*
Voltage On Any Pin Relative To Ground –0.3V to +4.6V
Operating Temperature 0
°C to 70°C, –40°C to +85°C for IND parts
Storage Temperature –40
°C to +70°C, –40°C to +85°C for IND parts
Soldering T emperature 260
°C For 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Power Supply Voltage V
CC
3.0 3.3 3.6 V
Logic 1 V
IH
2.2 V
CC
V
Logic 0 V
IL
0.0 0.4 V
DC ELECTRICAL CHARACTERISTICS (tA: See Note 10) (VCC=3.3V ±0.3V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current I
IL
–1.0 +1.0 µA
I/O Leakage Current
CE
≥ VIH ≤ V
CC
I
IO
–1.0 +1.0 µA
Output Current @ 2.2V I
OH
–1.0 mA 14
Output Current @ 0.4V I
OL
2.0 mA 14
Standby Current CE = 2.2V I
CCS1
50 250 µA
Standby Current CE = VCC–0.2V I
CCS2
30 150 µA
Operating Current I
CCO1
50 mA
Write Protection Voltage V
TP
2.8 2.9 3.0 V
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
IN
5 10 pF
Input/Output Capacitance C
I/O
5 10 pF
Page 4
DS1330W
022598 4/11
AC ELECTRICAL CHARACTERISTICS (tA: See Note 10) (VCC=3.3V ±0.3V)
DS1330W–150
PARAMETER SYMBOL
MIN MAX
TYPE UNITS NOTES
Read Cycle Time t
RC
150 ns
Access Time t
ACC
150 ns
OE to Output Valid t
OE
70 ns
CE to Output Valid t
CO
150 ns
OE or CE to Output Active t
COE
5 ns 5
Output High Z from Deselection t
OD
35 ns 5
Output Hold from Address
Change
t
OH
5 ns
Write Cycle Time t
WC
150 ns
Write Pulse Width t
WP
100 ns 3
Address Setup Time t
AW
0 ns
Write Recovery Time t
WR1
t
WR2
5
20
ns 12
13
Output High Z from WE t
ODW
35 ns 5
Output Active from WE t
OEW
5 ns 5
Data Setup Time t
DS
60 ns 4
Data Hold Time t
DH1
t
DH2
0
20
ns 12
13
READ CYCLE
t
RC
t
ACC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
OH
V
IH
t
OD
t
OD
V
IH
V
OH
V
OL
V
OH
V
OL
t
COE
t
COE
OUTPUT
DATA VALID
D
OUT
OE
ADDRESSES
V
IH
V
IH
t
OE
V
IL
V
IL
CE t
CO
SEE NOTE 1
Page 5
t
WC
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
ADDRESSES
CE
WE
D
OUT
D
IN
DATA IN STABLE
t
AW
t
WP
t
WR2
V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
t
COE
t
ODW
t
DS
t
DH2
V
IL
V
IH
V
IL
V
IH
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
DS1330W
022598 5/11
WRITE CYCLE 1
t
WC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
ADDRESSES
t
AW
DATA IN STABLE
HIGH
IMPEDANCE
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
t
WP
t
WR1
t
ODW
t
OEW
t
DS
t
DH1
V
IH
V
IL
V
IH
V
IL
CE
WE
D
OUT
D
IN
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
Page 6
DS1330W
022598 6/11
POWER–DOWN/POWER–UP CONDITION
V
CC
2.7V
t
F
t
PD
t
R
t
REC
BACKUP CURRENTSUPPLIED FROM
LITHIUM BATTERY
CE
,
WE
V
TP
t
BPU
t
RPU
t
RPD
RST
BW
V
IL
V
IH
SLEWS WITH
V
CC
V
IL
SEE NOTES 11 AND 14
t
DR
SLEWS WITH
V
CC
t
PU
V
IH
BATTERY WARNING DETECTION
BATTERY
t
BPU
V
TP
V
BAT
TEST
ACTIVE
BW
t
BTC
t
BW
t
BTPW
V
CC
V
IL
SEE NOTE 14
2.6V
Page 7
DS1330W
022598 7/11
POWER–DOWN/POWER–UP TIMING (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to CE and WE
Inactive
t
PD
1.5 µs 11
VCC slew from VTP to 0V t
F
150 µs
VCC Fail Detect to RST Active t
RPD
15 µs
14
VCC slew from 0V to V
TP
t
R
150 µs
VCC Valid to CE and WE
Inactive
t
PU
2 ms
VCC Valid to End of Write
Protection
t
REC
125 ms
VCC Valid to RST Inactive t
RPU
150 200 350 ms 14
VCC Valid to BW Valid t
BPU
1 s 14
BATTERY WARNING TIMING (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Battery Test Cycle t
BTC
24 hr
Battery Test Pulse Width t
BTPW
1 s
Battery Test to BW Active t
BW
1 s
(tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time t
DR
10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE
= VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. t
WP
is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the
earlier of CE or WE going high.
4. t
DS
is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE
low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain
in a high impedance state during this period.
7. If the CE
high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in high impedance state during this period.
8. If WE
is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers
remain in a high impedance state during this period.
Page 8
DS1330W
022598 8/11
9. Each DS1330W has a built–in switch that disconnects the lithium source until VCC is first applied by the user. The
expected t
DR
is defined as accumulative time in the absence of VCC starting from the time power is first applied
by the user.
10.All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is –40°C to +85°C.
11.In a power down condition the voltage on any pin may not exceed the voltage on V
CC
.
12.t
WR1
and t
DH1
are measured from WE going high.
13.t
WR2
and t
DH2
are measured from CE going high.
14.RST
and BW are open–drain outputs and cannot source current. External pull–up resistors should be connected
to these pins for proper operation. Both pins will sink 10 mA.
DC TEST CONDITIONS
Outputs Open
Cycle = 200 ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 – 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
ORDERING INFORMATION
DS1330 W P –
SSS –
III
Operating Temperature Range
blank: 0° to 70°
IND: –40° to +85°C
Access
150:
Speed
150 ns
Package Type
blank: 28–pin 600 mil DIP
P: 34–pin PowerCap Module
Page 9
DS1330W
022598 9/11
DS1330W NONVOLATILE SRAM, 34–PIN POWERCAP MODULE
PKG
DIM
INCHES
MIN NOM MAX
A 0.920 0.925 0.930
B 0.980 0.985 0.990
C – – 0.080
D 0.052 0.055 0.058
E 0.048 0.050 0.052
F 0.015 0.020 0.025
G 0.020 0.025 0.030
TOP VIEW
SIDE VIEW
BOTTOM VIEW: REFERENCE ONLY
COMPONENTS AND PLACEMENTS
MAY DIFFER FROM THOSE SHOWN
Page 10
DS1330W
022598 10/11
DS1330W NONVOLATILE SRAM, 34–PIN POWERCAP MODULE WITH POWERCAP
PKG
DIM
INCHES
MIN NOM MAX
A 0.920 0.925 0.930
B 0.955 0.960 0.965
C 0.240 0.245 0.250
D 0.052 0.055 0.058
E 0.048 0.050 0.052
F 0.015 0.020 0.025
G 0.020 0.025 0.030
TOP VIEW
SIDE VIEW
BOTTOM VIEW: REFERENCE ONLY
COMPONENTS AND PLACEMENTS
MAY DIFFER FROM THOSE SHOWN
ASSEMBLY AND USE
Reflow soldering
Dallas Semiconductor recommends that
PowerCap Module bases experience
one pass through solder reflow oriented
label–side up (live–bug).
Hand soldering and touch–up
Do not touch soldering iron to leads for
more than 3 seconds. To solder, apply
flux to the pad, heat the lead frame pad
and apply solder. To remove part, apply
flux, heat pad until solder reflows, and
use a solder wick.
LPM replacement in a socket
To replace a Low Profile Module in a
68–pin PLCC socket, attach a
DS9034PC PowerCap to a module base
then insert the complete module into the
socket one row of leads at a time, pushing only on the corners of the cap. Never
apply force to the center of the device.
To remove from a socket, use a PLCC
extraction tool and ensure that it does
not hit or damage any of the module IC
components. Do not use any other tool
for extraction.
Page 11
DS1330W
022598 11/11
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
DIM
INCHES
MIN NOM MAX
A – 1.050 –
B – 0.826 –
C – 0.050 –
D – 0.030 –
E – 0.112 –
A
D
B
C
E
16 PL
RECOMMENDED POWERCAP MODULE SOLDER STENCIL
PKG
DIM
INCHES
MIN NOM MAX
A – 1.050 –
B – 0.890 –
C – 0.050 –
D – 0.030 –
E – 0.080 –
A
D
B
C
E
16 PL
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