Page 1
Advance Data Sheet
4
March 2000
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
DNC3X3825
Features
Octal 10 Mbits/s Transceiver
■
DSP based.
■
Compatible with
for twisted-pair cable.
■
Half- and full-duplex operations.
■
Autopolarity detection and correction.
■
Adjustable squelch level for extended wire-length
capability (two levels).
■
Interfaces with
interface (MII) or a serial 10 Mbits/s 7-pin interface.
■
On-chip filtering eliminates the need for external filters.
Octal 100 Mbits/s Transceiver
■
Compatible with
PCS/PMA (clause 24), PMD (clause 25), MII management, and autonegotiation (clause 28) specifications.
■
Selectable 5-bit code-group (PDT/PDR interface)
or 4-bit data nibbles (MII interface) input/output.
■
Full- or half-duplex operations.
■
Optional carrier integrity monitor (CIM).
■
Selectable carrier sense signal generation (MCRS)
asserted during either transmis sion or reception in
half duplex (MCRS asserted during reception only
in full duplex).
■
Adaptive equalization and baseline wander correction.
IEEE
* 802.3 10Base-T standard
IEEE
802.3u media independent
IEEE
802.3u MII (clause 22),
Octal 100 Mbits/s FX Transceiver
■
Compatible with
IEEE
802.3u 100Base-FX stan-
dard.
■
Reuses existing twisted-pair I/O pins for compatible
fiber-optic transceiver pseudo-ECL (PECL) data.
■
Fiber mode automatically configures port:
— FX mode enable is pin or register selectable
— Disables autonegotiation and 10Base-T.
— Enables 100Base-FX remote fault signaling.
— Disables MLT-3 encoder/decoder.
— Disables scrambler/descrambler.
General
■
Ports individually configurable
■
Autonegotiation and management:
— Fast link pulse (FLP) burst generator.
— Arbitration function.
— Accepts preamble suppression.
— Operates up to 12.5 MHz.
■
Supports the MII station management protocol and
frame format (clause 22): basic and extended register set.
■
Supports next page.
■
Provides status signals: receive activity, transmit
activity, full duplex, collision/jabber, link integrity,
and speed indication.
■
Powerdown mode for 10 Mbits/s and 100 Mbits/s
operation.
■
Loopback testing for 10 Mbits/s and 100 Mbits/s
operation.
■
0.25 µm low-power CMOS technology.
■
Single 3.3 V power supply operation.
■
■
On-chip filtering eliminates the need for external
filters.
*
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact
your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.
25 MHz XTAL oscillator input or 25 MHz/50 MHz/
125 MHz clock input.
■
Compatible with RMII (standard version) and SMII
(standard version).
Page 2
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Table of Contents
Contents Page
Features ................................... .............................................. ...................................... .............................................1
Octal 10 Mbits/s Transceiver...................................................................................................................................1
Octal 100 Mbits/s Transceiver............. ....... ...... ....... ...... ....... ...... ....... ................................................... ....... ............1
Octal 100 Mbits/s FX Transceiver.................................................................. ....... ...... ....... ......................................1
General ......... ...... ....... ............................................. ...... ....... ...... ....................................... ...... ....... ...... ....... ...... ......1
Description ......................................................... ....... ...... ....... ...... ....... ...... ...... ....................................... ....... ...... ......4
Functional Block Diagram .......................................................................................................................................4
Macrocell I/Os.........................................................................................................................................................5
Signal Information......................................................................................................................................................6
Signal Descriptions .................................... ...... ....... ...... ....... ...... ....... ...... ...... ....................................... ....... ...... ......6
MII Station Management ................. ...... ....... ...... ....... ...... ....... ...... ....... ............................................. ...... ....... ...... ....13
Basic Operation ....................................................................................................................................................13
MII Interface Design ........................ ...... ....... ...... ....... ...... ....... ...... ....... ...... ...... .............................................. ..........14
Absolute Maximum Ratings.....................................................................................................................................14
Electrical Characteristics.........................................................................................................................................15
Register Information ................................................................................................................................................19
Register Descriptions............................................................................................................................................19
Application Notes: Board Layout.............................................................................................................................31
Board Layout Considerations................................................................................................................................31
Tables Page
Table 1. MII/5-Bit Serial Interface Signals.................................................................................................................6
Table 2. MII Management Signals ............................................................................................................................7
Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Signals.....................................................................................7
Table 4. Status Signals .............................................................................................................................................8
Table 5. Clock and Reset Signals.............................................................................................................................9
Table 6. Control/Status Signals ..............................................................................................................................10
Table 7. Testability Signals......................................................................................................................................12
Table 8. MII Management Frame Format................................................................................................................13
Table 9. MII Management Frames—Field Description............................................................................................13
Table 10 . Absolute Maximum Ratings ...................................................................................................................14
Table 11 . Operating Conditions .............................................................................................................................14
Table 12. Summary of Management Registers (MR) .............................................................................................19
Table 13. MR0—Control Register Bit Descriptions.................................................................................................20
Table 14. MR1—Status Register Bit Descriptions ..................................................................................................21
Table 15. MR2, MR3—PHY Identification Registers (1 and 2) Bit Descriptions .....................................................22
Table 16. MR4—Autonegotiation Advertisement Register Bit Descriptions............................................................22
Table 17. MR5—Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................23
Table 18. MR5—Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions.........................23
Table 19. MR6—Autonegotiation Expansion Register Bit Descriptions..................................................................24
Table 20. MR7—Next Page Transmit Register Bit Descriptions..............................................................................25
Table 21. MR16—PCS Control Register Bit Descriptions.......................................................................................25
Table 22. MR17—Autonegotiation Read Register A...............................................................................................26
Table 23. MR18—Autonegotiation Read Register B...............................................................................................26
Table 24. MR20—User-Defined Register ...............................................................................................................27
Table 25. MR21—RXER Counter ...........................................................................................................................27
2
Page 3
Advance Data Sheet DNC3X3825
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Table of Contents
Tables
Table 26. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions...................................................27
Table 27. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions.............................................28
Table 28. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions...............................................29
Table 29. MR31—Device-Specific Register 4 (Quick Status) Bit Descriptions .......................................................30
(continued)
(continued)
Page
Figures Page
Figure 1. DNC3X3825 Functional Block Diagram ....................................................................................................4
Figure 2. I/Os of the DNC3X3825 Macrocell ............................................................................................................5
Figure 3. DNC MII TX Logic ...................................................................................................................................15
Figure 4. DNC MII RX Logic...................................................................................................................................15
Figure 5. DNC Maintenance Logic .........................................................................................................................15
Figure 6. Typical Application (One Channel Shown) ..............................................................................................16
Figure 7. Pinout Assignment ..................................................................................................................................17
Figure 8. Typical Single-Channel Twisted-Pair (TP) Interface.................................................................................18
3
Page 4
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Description
The DNC3X3825 is a twisted-pair transceiver macrocell that supports transmission and reception over category 3
unshielded twisted-pair (UTP) cable and category 5 UTP.
The DNC3X3825 has been designed specifically for applications that support both 10Base-T and 100Base-X, such
as network interface cards (NICs), switches.
Figure 1 represents a functional block diagram of the DNC3X3825 macrocell.
Figure 2 shows the I/Os of the DNC3X3825 macrocell.
Functional Block Diagram
100 Mbits/s TRANSCEIVER
MII
INTERFACE
INTERFACE
MANAGEMENT
RMCLK
125 MH
MTXD[3:0]
MCRS
MCOL
MRXD[3:0]
MRX_DV
MRX_ER
MRXCLK
MTXCLK
MTXD[3:0]
MTX_EN
MTX_ER
SERIAL/PARALLEL
INTERFACE
MDC
MDIO
FREQ.
SYNTH.
Z
MII
CLK20
25 MHz
125 MHz
20 MHz
4B/5B
ENCODER
TX STATE
MACHINE
CIM
5B/4B
DECODER
FAR-END
FAULT DETECT
10 Mbits/s TRANSCEIVER
MANAGEMENT
SD
CAR_STAT
RXERR_ST
MII
FAR-END
FAULT GEN.
COLLISION
DETECT
CARRIER
DETECT
ALIGNER
LC10 LS10
AUTONEGOTIATION
AND LINK MONITOR
SCRAMBLER
RX STATE
MACHINE
SD
DESCRAMBLER
LC100
LS100
SD
PDT
PDR/
DCRU
SD
PMD
TX
PMD
RX
TPO
TPI
±
±
25 MHz
CRYSTAL
5-5136(F).j
Figure 1. DNC3X3825 Functional Block Diagram (1 Channel Shown)
4
Page 5
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Description
Macrocell I/Os
(continued)
APFE_PIN[7:0]
AUTO_EN[7:0]
BYPPD125
BYPPD160
CARIN_IN[7:0]
CK125_BUF
CRS_SEL[7:0]
EDBT[7:0]
ELLE_PIN[7:0]
EN_RMCK
EN_XTL
FASTSEL[1:0]
FASTTEST
FX_MODE[7:0]
F_DUP[7:0]
HBT_PIN[7:0]
HWRESET
IN125
INT_MASK[7:0]
ISOLATE[7:0]
LED_STR_EN
LED_BLINK_EN
LITF_ENH
LPBK_PIN[7:0]
MDC
MDIO_IN
MGT_ADD[4:2]
MODEL[5:0]
MTXD[3:0][7:0]
MTX_EN[7:0]
MTX_ER[7:0]
NOLP_PIN[7:0]
OUI[24:3]
POR
PWRDN[7:0]
REV_ADD
RMCLK
SDBT[7:0]
SDFX[7:0]
SECUR[7:0]
SER_SEL_PIN[7:0]
SPEED_PIN[7:0]
TESTMDC
TESTMDIN
TESTSEL[3:0]
TESTTXD[3:0]
TESTTXEN
TESTTXER
TPI[7:0]
TPIB[7:0]
VERSION[3:0]
XLO
ATBON
AUTODONE[7:0]
FDUP_OUT[7:0]
REG20_OUT[15:0][7:0]
RST_10_BUSY[7:0]
RST_BUSY[7:0]
RST_TX_BUSY[7:0]
SERIAL_SEL[7:0]
TESTRXCK[7:0]
TESTRXDV[7:0]
TESTRXD[3:0][7:0]]
TESTRXER[7:0]
TESTTXCK[7:0]
ATBOP
CK125P
CK160
CLK25RAW
CS[7:0]
ECLN
ECLP
INT_R31[7:0]
LS100_OK[7:0]
LS10_OK[7:0]
LS_OK[7:0]
MCOL[7:0]
MCRS[7:0]
MDIO_HI_Z
MDIO_OUT
MRXCLK[7:0]
MRXD[3:0][7:0]
MRX_DV[7:0]
MRX_ER[7:0]
MTXCLK[7:0]
REXT10
REXT100
REXTBS
RMCLKRAW
RS[7:0]
SLOWCLK[7:0]
TESTCOL[7:0]
TESTCRS[7:0]
TESTMDHZ
TESTMDOUT
TPAPS[7:0]
TPJS[7:0]
TPO[7:0]
TPOB[7:0]
XHI
XS[7:0]
DNC3X3825
Figure 2. I/Os of the DNC3X3825 Macrocell
5-7541(F).a.r2
5
Page 6
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Signal Information
Signal Descriptions
Table 1. MII/5-Bit Serial Interface Signals
Signal Type Name/Description
MCOL[7:0] O
MCRS[7:0] O
MRXCLK
[7:0]
MRXD[3:0]
[7:0]
Collision Detect.
the network. MCOL is asserted high whenever there is transmit and receive activity on the
UTP media. MCOL is the logical AND of MTX_EN and receive activity, and is an asynchronous output. When SER_SEL_PIN is high and in 10Base-T mode, MCOL indicates the
jabber timer has expired.
Carrier Sense.
transmit or receive medium is nonidle. This signal remains asserted throughout a collision
condition. When CRS_SEL is high, MCRS is asserted on receive activity only. CRS_SEL is
set via the MII management interface or the CRS_SEL signal.
Receive Clock.
O
nibble mode, and 10 MHz in 10 Mbits/s serial mode. MRXCLK has a worst-case 35/65 duty
cycle. MRXCLK provides the timing reference for the transfer of MRX_DV, MRXD, and
MRX_ER signals.
Receive Data
O
MRX_ER is asserted high in 100 Mbits/s mode, an error code will be presented on
MRXD[3:0] where appropriate. The codes are as follows:
This signal signifies in half-duplex mode that a collision has occurred on
When CRS_SEL is low, this signal is asserted high when either the
25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output in 10 Mbits/s
. 4-bit parallel data outputs that are synchronous to MRXCLK. When
MRX_DV
[7:0]
MRX_ER
[7:0]
MTXCLK
[7:0]
MTXD[3:0]
[7:0]
MTX_EN
[7:0]
MTX_ER
[7:0]
Packet errors: ERROR_CODES = 2h.
Link error s: ERROR_CODES = 3h. (Packet a nd link erro r codes will only be repeated if
registers [29.9] and [29.8] are enabled.)
Premature end errors: ERROR_CODES = 4h.
Code errors: ERROR_CODES = 5h.
When SER_SEL_PIN is active-high and 10 Mbits/s mode is selected, MRXD[0] is used for
data output and MRXD[3:1] are 3-stated.
Receive Data Valid.
O
and decoding valid nibbles on MRXD[3:0], and the data is synchronous with MRXCLK.
MRX_DV is synchronous with MRXCLK. This signal is not used in serial 10 Mbits/s mode.
Receive Error.
O
error in the frame presently being received. MRX_ER is synchronous with MRXCLK.
Transmit Clock.
O
MII mode, 10 MHz output in 10 Mbits/s serial mode. MTXCLK provides timing reference for
the transfer of the MTX_EN, MTXD, and MTX_ER signals sampled on the rising edge of
MTXCLK.
Transmit Data.
I
active-high and 10 Mbits/s mode is selected, only MTXD[0] is valid.
Transmit Enable.
I
MTX_EN is synchronous with MTXCLK. When SER_SEL_PIN is active-high and
10 Mbits/s mode is selected, this signal indicates there is valid data on MTXD[0].
Transmit Coding Error.
I
corrupt the byte being transmitted across the MII (00100 will be transmitted). When in
10 Mbits/s mode, this signal is ignored.
When this signal is high, it indicates the DNC3X3825 is recovering
When high, MRX_ER indicates the DNC3X3825 has detected a coding
25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output in 10 Mbits/s
4-bit parallel input synchronous with MTXCLK. When SER_SEL_PIN is
When driven high, this signal indicates there is valid data on MTXD[3:0].
When driven high, this signal causes the encoder to intentionally
6
Page 7
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Signal Information
Table 2. MII Management Signals
Signal
MDC I
MDIO_IN I
MDIO_OUT O
MDIO_HI_Z O
INT_MASK[7:0] I
INT_R31[7:0] O
(continued)
Type
Name/Description
Management Data Clock.
on the MDIO signal. This signal may be asynchronous to MRXCLK and
MTXCLK. The maximum clock rate is 12.5 MHz.
When running MDC above 6.25 MHz, MDC must be synchronous with
CLK25RAW and have a setup time of 15 ns and a hold time of 5 ns with respect
to CLK25RAW.
Management Data Input.
ment, synchronous with MDC, onto this input.
Management Data Output.
synchronous with MDC, onto this output.
Management Data Output Enable.
3-state the MDIO bidirectional buffer (external to the DNC3X3825).
Interrupt Mask.
When set low, interrupts are generated according to bit [31.7]. This signal is
ORed with bit [31.6].
Maskable Status Interrupt.
in status as defined in Table 27.
When set high, no interrupt is generated under any condition.
This is the timing reference for the transfer of data
Control information is driven by the station manage-
Status information is driven by the DNC3X3825,
When high, this signal can be used to
This signal will go high whenever there is a change
Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Signals
Signal Type Name/Description
TPI
[7:0]
TPIB
[7:0]
TPO
[7:0]
TPOB
[7:0]
REXT10 PADO
REXT100 PADO
REXTBS PADO
PADI
PADI
PADO
PADO
Received Data.
Manchester data from magnetics.
Fiber-Optic Data Input.
data from fiber transceiver.
Received Data.
Manchester data from magnetics.
Fiber-Optic Data Input.
data from fiber transceiver.
Transmit Data.
Manchester data to magnetics.
Fiber-Optic Data Output.
compatible data to fiber transceiver.
Transmit Data.
Manchester data to magnetics.
Fiber-Optic Data Output.
ECL compatible data to fiber transceiver.
Current Setting 10 Mbits/s.
signal to ground to set the 10 Mbits/s TP driver transmit output level.
Current Setting 100 Mbits/s.
signal to ground to set the 100 Mbits/s TP driver transmit output level.
Band Gap Reference for the Receive Channel.
24.9 kΩ ± 1% resistor to ground. The parasitic load capacitance should be less
than 15 pF.
Positive differential received 125 Mbaud MLT3 or 10 Mbaud
Positive differential received 125 Mbaud pseudo-ECL
Negative differential received 125 Mbaud MLT3 or 10 Mbaud
Negative differential received 125 Mbaud pseudo-ECL
Positive differential transmit 125 Mbaud MLT3 or 10 Mbaud
Negative differential transmit 125 Mbaud MLT3 or 10 Mbaud
Positive differential transmit 125 Mbaud pseudo-ECL
Negative differential transmit 125 Mbaud pseudo-
An external resistor (21.0 kΩ) is placed from this
An external resistor (21.5 kΩ) is placed fro m this
Connect this signal to a
7
Page 8
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Signal Information
LEDs operate as follows
LED_STR_EN = 0, LED_BLINK_EN = 0 => No stretching/blinking.
LED_STR_EN = 1, LED_BLINK_EN = 0 => Stretch to 42 ms, minimum.
LED_STR_EN = 0, LED_BLINK_EN = 1 => Every activity causes 42 mS ON, 42 mS OFF blink.
LED_STR_EN = 1, LED_BLINK_EN = 1 => Every activity causes 0.5 second ON, 0.5 second OFF blink.
Table 4. Status Signals
Signal Type Name/Description
XS[7:0] O
RS[7:0] O
CS[7:0] O
LS10_OK[7:0] O
LS100_OK[7:0] O
LS_OK[7:0] O
FDUP_OUT[7:0] O
TPJS[7:0] O
TPAPS[7:0] O
(continued)
:
Transmit Status.
stretched or blinked per the description given above.
Receive St atus
stretched or blinked per the description given above.
Collision Status
be stretched or blinked per the description given above.
Link10
Link100.
Link Status.
Full-Duplex Status
low, then the link is half duplex.
Jabber Status.
TP Autopolarity Status.
corrected.
This signal indicates transmit activity. This output can be
. This signal indicates receive activity . This output can be
. This signal indicates collision occurrence. This output can
. This signal indicates good link status for 10 Mbits/s.
This signal indicates good link status for 100 Mbits/s.
Indicates link status.
. If this signal is high, it indicates full-duplex link, and if it is
Indicates that there is a jabber condition (only in 10 Mbits/s).
Indicates if autopolarity has been detected and
8
Page 9
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Signal Information
Table 5. Clock and Reset Signals
Signal Type Name/Description
EN_RMCK I
RMCLK PA D I*
IN125 I
EN_XTL I
XLO PADI
XHI PADO
CLK25RAW O
RMCLKRAW O
SLOWCLK[7:0] O
HWRESET I
POR I
RST_BUSY[7:0] O
RST_10_BUSY[7:0] O
RST_TX_BUSY[7:0] O
BYPPD125 I This pin, when high, powers up the 125 MHz PLL permanently , allowing
BYPPD160 I This pin, when high, powers up the 160 MHz PLL permanently , allowing
CK125_BUF I This pin is the feedback for CK125P. Normally this will be connected to
CK160 O This is a 160 MHz output clock; this will be available if 10Base-T is enabled or
CK125P O This is a 125 MHz output clock, which must be fed back to CK125_BUF. This
(continued)
†
(optional)
Enable RMCLK
This signal and EN_XTL cannot be high simultaneously.
Primary Input Clock.
50 MHz. IN125 is used to indicate the appropriate frequency. This clock input
is used when EN_RMCK is high.
Input Clock Frequency Select
frequency of RMCLK is 125 MHz; else the clock frequency is 50 MHz.
Enable Crystal Input
(XLO) as the clock input. This signal and EN_RMCK cannot be high simultaneously.
Crystal Oscillator Input.
across XLO and XHI. Alternately, a 25 MHz external CMOS oscillator can be
connected to this input. This clock input is used when EN_XTL is high.
Crystal Oscillator Output
is not used.
CLK25RAW.
RMCLKRAW.
125 MHz, depending on RMCLK frequency.
24 Hz Clock Output.
Full-Chip Reset.
when reset is complete. 10Base-T and 100Base-TX/-FX are in reset until
enabled and take 1.3 ms to come out of reset.
Po wer-On Reset.
then tie this input low.
Reset Busy.
10Base-T in Reset.
100Base-TX Reset.
CK125P to be used for external logic at all times.
CK160 to be used for external logic at all times.
CK125P or any external chip clock buffers for CK125P.
BYPPD160 is high.
will be available when in 100Base-Tx mode or if BYPPD125 is high or if IN125
is high.
. When high, this signal selects RMCLK as the clock input.
The frequency of this clock can be either 125 MHz or
. When high, this signal will indicate that the
. This signal, when high, will select the crystal input
A 25 MHz crystal ± 25 ppm can be connected
. This pad does not have to be bonded out if crystal
25 MHz output clock.
Buffered version of the RMCLK. This is either 50 MHz or
This is a 24 Hz output signal.
Reset is active-high. The RST_BUSY signal will go low
If a powerup reset (PUR) cell from ASIC library is not used,
This signal indicates that the DNC3X3825 is in reset.
This signal indicates that the 10 Mbits/s logic is in reset.
This signal indicates that the 100 Mbits/s logic is in reset.
* Double bonded with XLO.
† Double bonded with RMCLK.
9
Page 10
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Signal Information
Table 6. Control/Status Signals
Signal Type Description
AUTO_EN[7:0] I
F_DUP[7:0] I
CRS_SEL[7:0] I
SER_SEL_PIN[7:0] I
CARIN_IN[7:0] I
EDBT[7:0] I
SDBT[7:0] I
SPEED_PIN[7:0] I
(continued)
Autonegotiation Enable.
enabled. Pulsing this signal will cause autonegotiation to restart. This input
has the same function as register 0, bit 12. This input and the register bit are
ANDed together.
Full-Duplex Mode.
duplex mode. A low on this signal will put it in half-duplex mode. This signal
is ignored when autonegotiation is enabled. This is the same function as
register 0, bit 8. This input and the register bit are ORed together.
Carrier Sense Select.
MCRS operation. When this signal is pulled high, MCRS will be asserted on
receive activity only. This is the same function as register 29, bit 10. This
input and the register bit are ORed together.
Serial Mode Select.
tion of register 30, bit 1 by pulling it high, if station management is unavailable. This input and the register bit are ORed together.
Carrier Integrity Enable.
carrier integrity function of register 29, bit 3, if station management is
unavailable. This input and the register bit are ORed together.
Encoder/Decoder Bypass.
encoder/decoder bypass function of register 29, bit 6, if station management
is unavailable. This input and the register bit are ORed together.
Scrambler/Descrambler.
descrambler bypass function by pulling this signal high, if station management is unavailable. This is the same function as register 29, bit 4. This
input and the register bit are ORed together.
Speed.
same function as register 0, bit 13:
This signal can be used to select the operating speed and is the
When this signal is high, autonegotiation is
When this signal is set high, the PHY will be in full-
This signal may be used to select the mode of
This signal may be used to set the SERIAL_SEL func-
If this signal is pulled high, it will enable the
If this signal is pulled high, it will enable the
This signal may be used to enable the scrambler/
MGT_ADD[4:2] I
REV_ADD I
FX_MODE[7:0] I
10
■
If this signal is pulled high, it will enable 100 Mbits/s operation.
■
If this signal is pulled low, it will enable 10 Mbits/s operation.
This signal is ignored when autonegotiation is enabled. This signal and the
register bit are ANDed.
Management Address [4:2]
addresses and are decoded as follows:
MGT_ADD[4:2] PHY 0, PHY 1, PHY 2, PHY 3, . . . , PHY 7
000 0, 1, 2, 3, 4, 5, 6, 7
001 8, 9, 10, 11, 12, 13, 14, 15
010 16, 17, 18, 19, 20, 21, 22, 23
011 24, 25, 26, 27, 28, 29, 30, 31
100 6, 7, 8, 9, 10, 11, 12, 13
101 12, 13, 14, 15, 16, 17, 18, 19
110 18, 19, 20, 21, 22, 23, 24, 25
111 0, 0, 0, 0, 0, 0, 0, 0
Reverse Phy Address
Access. (PHY0 is highest address, PHY7 is lowest address)
FX_MODE
mode. This signal is ORed with register 29, bit 0 [29.0].
. When this signal is high, it puts DNC3X3825 in fiber-optic
. These signals set the management
. Reverse the order of Ports for Management
Page 11
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Signal Information
Table 6. Control/Status Signals
Signal Type Description
FASTTEST I
FASTSEL[1:0] I
LITF_ENH I
SDFX[7:0] PAD
SECUR[7:0] I
ISOLATE[7:0] I
APFE_PIN[7:0] I
(continued)
(optional I)
(continued)
Fast Test
internal timers run faster than normal, with the speedup determined by
FASTSEL[1:0]
Fast Speed Select.
(10 Mbit/s NLP link, 10 Mbit/s jabber, reset timers, autonegotiation counters)
is as follows:
00 = No speedup.
01 = 16x speedup.
10 = 64x speedup.
11 = 256x speedup. (Autonegotiation does not work at this speedup.)
Enhanced Link Integrity Test Function.
will be deasserted when 31 Manchester violations have occurred.
SDFX.
bonded out if fiber mode is not used.
Security.
transmitted.
Isolate.
isolate mode per the
come out of reset in normal mode. When isolated, all receive outputs are
low, and all transmit requests are ignored. While isolated, the macrcell will
respond to management transactions, detect, and transmit link pulses.
Register 0, bit 10, is used to put the transceiver in/out of isolate mode.
Autopolarity Function Enable (Active Low).
and the DNC3X3625 is operating at 10 Mbits/s, the autopolarity function will
determine if the TP link is wired with a polarity reversal:
. This signal should be low for normal operation. When high, the
When FASTTEST is high, the speedup of the timers
When this input is high, The link
Signal detect from fiber-optic receiver. This pad does not have to be
When this input is high and MTX_EN is high, JAM pattern (55) is
When this signal is high, the macrocell will come out of reset in
IEEE
standard. If this is low, then the macrocell will
When this signal is set low
ELLE_PIN[7:0] I
HBT_PIN[7:0] I
LPBK_PIN[7:0] I
NOLP_PIN[7:0] I
LED_STR_EN I
■
The DNC3X3625 will assert the autopolarity status (APS) bit (register 28,
bit 6) and correct the polarity reversal.
■
If this signal is set high and the DNC3X3625 is operating at 10 Mbits/s,
the reversal will not be corrected.
Extended Line Length Enable.
squelch level is reduced from a nominal 435 mV to 350 mV, allowing reception of signals with lower amplitude. This is the same function as register 30,
bit 4. The input and the register bit are ORed together.
Heartbeat Enable.
function (serial mode). This is the same function as register 30, bit 5. The
input and the register bit are ORed together.
Loopback.
mode. No data transmission will take place on the media and any receive
data will be ignored. This is the same function as register 0, bit 14. The input
and the register bit are ORed together.
No Link Pulse Mode.
with link pulses disabled. If the DNC3X3825 is configured for
100 Mbits/s operation, this signal is ignored. This is the same function as
register 30, bit 0. The input and the register bit are ORed together.
LED Stretch Enable.
the LED output is stretched to 42 ms minimum, unless LED_BLINK_EN is
high. This signal is ORed with register 29, bit 7.
When this signal is asserted high DNC3X3825 is in loopback
When asserted high, this input will enable the heartbeat
Setting this signal high will allow 10 Mbits/s operation
This pin, when low, disables stretching. When high,
When this signal is set high, the receive
11
Page 12
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Signal Information
Table 6. Control/Status Signals
Signal Type Description
LED_BLINK_EN I
OUI[24:3] I
MODEL[5:0] I
VERSION[3:0] I
PWRDN[7:0] I
SERIAL_SEL[7:0] O
AUTODONE[7:0] O
RG20_OUT[15:0]
[7:0]
(continued)
O
(continued)
LED Blink Enable.
LED output will blink high for 42 ms and low for 42 ms whenever there is
activity, unless LED_STR_EN is high, in which case the blinking is 0.5
seconds high and 0.5 seconds low. This signal is ORed with register 29, bit
11.
Organizationally Unique Identifier.
upon instantiation of the macro.
Model Numb er.
upon instantiation.
Revision Number.
programmed upon instantiation.
Powerdown.
management registers.
Serial Select.
When SERIAL_SEL is low , the macro is in 100 Mbits/s or 10 Mbits/s parallel
mode.
Autonegotiation Done.
has completed. It will go low if autonegotiation has to restart.
Register 20 Access.
A write to this register can be through MDIO.
This pin, when low, disables blinking. When high, the
This can be programmed by the user,
6-bit model number of the device. This can be programmed
The value of the present revision number. This can be
When high, this signal powers down the PHY and resets all
When this signal is high, it indicates 10 Mbit/s serial mode.
This signal goes high whenever autonegotiation
This bus provides access to the user-defined register.
Table 7. Testability Signals
Signal Type Description
TESTSEL[3:0] I
TESTMDC I
TESTTXD[3:0]
TESTTXER
TESTTXEN
TESTCRS[7:0] O
TESTCOL[7:0]
TESTRXCK[7:0]
TESTTXCK[7:0]
TESTRXD[3:0][7:0]
TESTRXER[7:0]
TESTRXDV[7:0]
ATBOP PADO
ATBON
ECLP
ECLN
TESTMDIN I
TESTMDOUT O
TESTMDHZ O
(optional)
Test Mode Select.
modes: scan, analog, etc. Lucent requires access to these pins for
manufacturing testing. They should be held low for normal operation.
Test Mode Inputs.
bility to the macrocell, either as scan inputs or as digital/analog test
inputs/controls depending on the test mode selected by TESTSEL[3:0].
Test Mode Outputs.
form of either scan outputs or digital/analog test outputs depending on
the test mode selected by TESTSEL[3:0]. The TESTRXD[3:0][7:0] and
TESTRXER[7:0] must be mapped to outputs during test. The other test
output should be mapped, if possible, to ease PHY debugging.
Analog Test Output Pins
should be connected to bond pads, but are not required to be
connected to package pins.
Test Mode MDIN, MDOUT, and MDHZ.
signals from/to a bidirectional buffer .
These pins enable the PHY to be in various test
These test inputs provide a high level of controlla-
These test output pins provide observability in the
. These are used in Lucent test modes. They
Input, output, and I/O control
12
Page 13
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
MII Station Management
Basic Operation
The primary function of station management is to transfer control and status information about the DNC3X3825 to
a management entity. This function is accomplished by the MDC clock input, which has a maximum frequency of
25 MHz, along with the MDIO signal.
The MII management interface uses MDC and MDIO to physically transport information between the PHY and the
station management entity.
In the DNC3X3825, the MDIO pin is implemented as three signals: MDIO_IN, MDIO_OUT, and MDIO_HIZ.
MDIO_IN is the information coming from the MAC and is ignored during the TA and DATA fields for MDIO reads.
MDIO_HIZ will be high except during MDIO reads, in which case MDIO_OUT is the PHY data. Under no condition
should the input MDIO_IN be 3-stated. These can be connected to control an I/O buffer if off-chip access is
required.
A specific set of registers and their contents (described in Table 9) defines the nature of the information transferred
across the MDIO interface. Frames transmitted on the MII management interface will have the frame structure
shown in Tab le 8. The order of bit transmission is from left to right. Note that reading and writing the management
register must be completed without interruption. The port addresses are set by the MGT_ADD pin (see Table 6 for
more detail).
Table 8. MII Management Frame Format
Read/Write
(R/W)
R 1 . . . 1 01 10 AAAAA RRRRR Z0 DDDDDDDDDDDDDDDD Z
W 1 . . . 1 01 01 AAAAA RRRRR 10 DDDDDDDDDDDDDDDD Z
Table 9. MII Management Frames—Field Description
Field Descriptions
Pre
ST
OP
PHYADD
REGAD
TA
DA TA
IDLE
Pre ST OP PHYAD REGAD TA DAT A IDLE
Preamble
register 1, bit 6.
Start of Frame.
Operation Code
transaction is a 01.
PHY Address
bit transmitted and received is the MSB of the address. A station management entity that is
attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for
each entity.
Register Address.
The first register address bit transmitted and received is the MSB of the address.
Turnaround
the data field of a frame, to avoid drive contention on MDIO during a read transaction. During a
write to the DNC3X3825, these bits are driven to 10 by the station. During a read, the MDIO is not
driven during the first bit time and is driven to a 0 by the DNC3X3825 during the second bit time.
Data
being addressed.
Idle Condition.
be disabled and the PHY’s pull-up resistor will pull the MDIO line to a logic 1.
. The DNC3X3825 will accept frames with no preamble. This is indicated by a 1 in
The start of frame is indicated by a 01 pattern.
. The operation code for a read transaction is 10. The operation code for a write
. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
The register address is 5 bits, allowing for 32 unique registers within each PHY.
. The turnaround time is a 2-bit time spacing between the register address field, and
. The data field is 16 bits. The first bit transmitted and received will be bit 15 of the register
The IDLE condition on MDIO is a high-impedance state. All three state drivers will
13
Page 14
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
MII Interface Design
The chip layout will affect MII electrical specifications. Figures 3, 4, and 5 show the PHY logic on the interfaces. If
the MAC logic follows the rules below, then the interface should function properly:
1. Transmit signals should change on the positive edge of TxClk.
2. Receive signals should be captured on the positive edge of RxClk.
3. Management output should change on the negative edge of MDC (and be stable on its positive edge) management inputs should be latched on the positive edge of MDC.
Absolute Maximum Ratings
(TA = 25 °C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Table 10. Absolute Maximum Ratings
Parameter Symbol Min Max Unit
Ambient Operating Temperature T
Storage Temperature T
Power Dissipation P
A
stg
D
Voltage on Any Pin with Respect to Ground — –0.5 V
070°C
–40 125 °C
—3.5W
DD
+ 0.5 V
Maximum Supply Voltage — — 3.5 V
Table 11. Operating Conditions
Parameter Symbol Min Typ* Max Unit
Operating Supply Voltage — — 3.3 3.465 V
Power Dissipation:
All Ports Autonegotiating
All Ports 10Base-T Link
10Base-T TX/RX 100%
100Base-T TX
D
P
D
P
D
P
D
P
—
—
—
—
—
—
—
3200
—
—
—
—
mW
mW
mW
mW
* Typical power dissipations are specified at 5 V and 25 °C. This is the power dissipated by the DNC3X3825. An additional 0.2 W of power is
required for the external twisted-pair driver termination resistors.
14
Page 15
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Electrical Characteristics
The following specifications apply for VDD = 3 V ± 5%.
MTXD
MTX_ER
MTX_EN
TEST
RXDTX, RXDVTX,
RXERTX
RXCLKTX
RXER10,
RXD10, RXDV10
RXCLK10
TXDTX
TXCLKTX
TXCLK10
TXD10
DNC MII TX LOGIC
Figure 3. DNC MII TX Logic
MRXD, MRX_ER,
MRX_DV
MRXCLK
DNC MII RX LOGIC
Figure 4. DNC MII RX Logic
MTXCLK
5-7722(F).r2
5-7723(F).r1
MDIO_IN
MDC
DNC MII MAINTENANCE LOGIC
Figure 5. DNC Maintenance Logic
MDIO_OUT
MDIO_HI_Z
5-7724(F)
15
Page 16
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Electrical Characteristics
XLO/RMCLK BONDED
TO SAME PIN
SEE APPLICATION FOR
DETAILS ON EXTERNAL
COMPONENTS
RJVS
FOR TEST SET ONLY,
OPEN ON ACTUAL BOARD
(continued)
XLO
RMCLK
XHI
REXT10
REXT100
REXTBS
TPI
TPIB
TPO
TPOB
ECLP
ECLN
ATBON
ATBOP
DNC
CLK125BUF
CK125P
MTXD, MTX_EN,
MTX_ER
MTXCLK
MRXD, MRX_ER,
MRX_DV
RXCLK
MDIO_OUT
MDIO_IN
MDC
TESTTXD
TESTTXEN
TESTTXER
TESTCRS
TESTCOL
TESTTXCK
TESTRXCK
TESTRXD
TESTRXER
TESTRXDV
TESTMDIN
TESTMDOUT
MAC TX
LOGIC
SOME ARE
OPTIONAL
MAY BUFFER IF
MAC USES CK125P
MAC RX
LOGIC
MANAGEMENT
MAC
LOGIC
MAC
LOGIC
PHYTESTEN
MAC
LOGIC
MAC
LOGIC
6
10
1
I/O
16
TESTMDC
PHYTESTEN
PHYTESTEN
PHYTESTEN
TESTSEL
[3:0]
MAC
LOGIC
Figure 6. Typical Application (One Channel Shown)
4
PHY
TEST
EN
TEST I/O CAN BE SHARED WITH OTHER I/Os
5-7725(F).r1
Page 17
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Electrical Characteristics
SSA
V
DDA
V
TPI7
TPIB7
SSA
V
DDA
V
TPI6
TPIB6
SSA
V
DDA
V
TPI5
TPIB5
SSA
V
DDA
V
TPI4
TPIB4
SSA
V
DDA
V
TPI3
TPIB3
SSA
V
SSA
V
TPI2
TPIB2
SSA
V
DDA
V
TPI1
TPIB1
SSA
V
DDA
V
TPI0
TPIB0
SSA
V
DDA
V
REXTBS
SSA
V
DDM
V
SSM
V
DDA
V
RMCLK
XLO
XHI
SSA
V
DDA
V
REXT100
REXT10
SSA
V
SSO
V
TPOB7
TPO7
SSO
V
SSO
V
TPOB6
TPO6
SSO
V
SSO
V
TP0B5
TPO5
SSO
V
SSO
V
TPOB4
TPO4
SSO
V
SSO
V
TPOB3
TPO3
SSO
V
SSO
V
TPOB2
TPO2
SSO
V
SSO
V
TPOB1
TPO1
SSO
V
SSO
V
TPOB0
TPO0
SSO
V
(continued)
LOW-SPEED DIGITAL
I/Os CAN GO HERE
DOUBLE BONDED TO SAME PIN
LOW-SPEED DIGITAL
I/Os CAN GO HERE
DDA
SSAVSSAVDDAVSSE
ATBON
V
ATBOP
V
SDFX
DO NOT NEED TO
BE BONDED OUT
VDDV
VSSV
DD
ECLN
ECLP
V
LOW-SPEED
DIGITAL I/Os
DDE
SS
LOW-SPEED
DIGITAL I/Os
5-7725(F).r1
Figure 7. Pinout Assignment
17
Page 18
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Electrical Characteristics
TPO
10 pF
TPOB
DNC3X3825
TPI
Ω
50
Ω
50
TPIB
(continued)
V
Ω
50
Ω
50
0.01 µF
DDO
0.01 µF
1:1
1:1
0.01 µF
Ω
75
0.01 µF
Ω
75
0.01 µF
75
Ω
Ω
75
0.01 µF
RJ-45
1
2
3
4
5
6
7
8
Figure 8. Typical Single-Channel Twisted-Pair (TP) Interface
5-5433(F).o
18
Page 19
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information
Register Descriptions
The MII management 16-bit register set implemented is as follows. The PHY address pins control the management
pins.
Table 12. Summary of Management Registers (MR)
Register
Address
0 MR0 Control 3000h
1 MR1 Status 7849h
2 MR2 PHY Identifier 1 TBD
3 MR3 PHY Identifier 2 TBD
4 MR4 Autonegotiation Advertisement 01E1h
5 MR5 Autonegotiation Link Partner Ability 0000
6 MR6 Autonegotiation Expansion 0000
7 MR7 Next Page Transmit 0000
8—15 MR8—MR15 (Reserved) —
16 MR16 PCS Control Register 0000
17 MR17 Autonegotiation (read register A) 0000
18 MR18 Autonegotiation (read register B) 0000
19 MR19 Lucent Analog Test Register —
20 MR20 User-defined Register —
21 MR21 RXER Counter 0000
22 MR22 Lucent Analog Test Registers —
23 MR23
24 MR24
25 MR25 Lucent Analog Test (Tuner) Registers —
26 MR26
27 MR27
28 MR28 Device Specific 1 —
29 MR29 Device Specific 2 2080
30 MR30 Device Specific 3 0000
31 MR31 Quick Status Register —
Symbol Name
(Hex Code)
Default
19
Page 20
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Register Information
Table 13. MR0—Control Register Bit Descriptions
Bit
*
0.15 (SW_RESET) R/W
0.14 (LOOPBACK) R/W
0.13 (SPEED100) R/W
0.12 (NWAY_ENA) R/W
0.11 (PWRDN) R/W
0.10 (ISOLATE) R/W
0.9 (REDONWAY) R/W
0.8 (FULL_DUP) R/W
0.7 (COLTST) R/W
0.6:0 (RESERVED) NA
Type
(continued)
†
Reset.
Setting this bit to a 1 will reset the DNC3X3825. All registers will be set
to their default state. This bit is self-clearing. The default is 0.
Loopback.
media. Any receive data will be ignored. The loopback signal path will contain
all circuitry up to, but not including, the PMD. The default value is a 0.
Speed Selection.
(1 = 100 Mbits/s; 0 = 10 Mbits/s). This bit will only affect operating speed when
the autonegotiation enable bit (register 0, bit 12) is disabled (0). This bit is
ignored when autonegotiation is enabled (register 0, bit 12). This bit is ANDed
with the SPEED_PIN signal.
Autonegotiation Enable.
ting this bit to a 1. The default state is a 1.
Powerdown.
this bit to a 1, both the 10 Mbits/s transceiver and the 100 Mbits/s transceiver
will be powered down. While in the powerdown state, the DNC3X3825 will
respond to management transactions. The default state is a 0.
Isolate.
impedance state. The default state is a 0.
Restart Autonegotiation.
powerup. The process may be restarted by setting this bit to a 1. The default
state is a 0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes to
a 1. This bit is self-cleared when autonegotiation restarts.
Duplex Mode.
duplex). This bit is ignored when the autonegotiation enable bit (register 0,
bit 12) is enabled. The default state is a 0. This bit is ORed with the
F_DUP pin.
Collision Test.
MCOL signal in response to MTX_EN.
Reserved.
When this bi t is set to 1, n o dat a tr ansmis sion w ill ta ke place on th e
The value of this bit reflects the current speed of operation
The DNC3X3825 may be placed in a low-power state by setting
When this bit is set to a 1, the MII outputs will be brought to the high-
This bit reflects the mode of operation (1 = full duplex; 0 = half
When this bit is set to a 1, the DNC3X3825 will assert the
All bits will read 0.
Description
The autonegotiation process will be enabled by set-
Normally, the autonegotiation process is started at
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write, NA = not applicable.
20
Page 21
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information
Table 14. MR1—Status Register Bit Descriptions
Bit
*
1.15 (T4ABLE) R
1.14 (TXFULDUP) R
1.13 (TXHAFDUP) R
1.12 (ENFULDUP) R
1.11 (ENHAFDUP) R
1.10:7 (RESERVED ) R
1.6 (NO_PA_OK) R
1.5 (NWAYDONE) R
1.4 (REM_FLT) R
1.3 (NWAYABLE) R
1.2 (LSTAT_OK) R
1.1 (JABBER) R
1.0 (EXT_ABLE) R
Type
(continued)
†
100Base-T4 Ability.
0: Not able.
1: Able.
100Base-TX Full-Duplex Ability.
0: Not able.
1: Able.
100Base-TX Half-Duplex Ability.
0: Not able.
1: Able.
10Base-T Full-Duplex Ability.
0: Not able.
1: Able.
10Base-T Half-Duplex Ability.
0: Not able.
1: Able.
Reserved.
Suppress Preamble.
DNC3X3825 accepts management frames with the preamble suppressed.
Autonegotiation Complete.
process has been completed. The contents of registers MR4, MR5, MR6, and
MR7 are now valid. The default value is a 0. This bit is reset when autonegotiation is started.
Remote Fault.
This bit will remain set until cleared by reading the register. The default is a 0.
Autonegotiation Ability.
autonegotiation. The value o f this bit is always a 1.
Link Status.
This bit has a latching function: a link failure will cause the bit to clear and stay
cleared until it has been read via the management interface.
Jabber Detect.
remain set until it is read, and the jabber condition no longer exists.
Extended Capability.
extended register set (MR2 and beyond). It will always read a 1.
All bits will read as a 0.
When this bit is a 1, it indicates a remote fault has been detected.
When this bit is a 1, it indicates a valid link has been established.
This bit will be a 1 whenever a jabber condition is detected. It will
Description
This bit will always be a 0.
This bit will always be a 1.
This bit will always be a 1.
This bit will always be a 1.
This bit will always be a 1.
When this bit is set to a 1, it indicates that the
When this bit is a 1, it indicates the autonegotiation
When this bit is a 1, it indicates the ability to perform
This bit indicates that the DNC3X3825 supports the
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read.
21
Page 22
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Register Information
(continued)
Table 15. MR2, MR3—PHY Identification Registers (1 and 2) Bit Descriptions
Bit
*
2.15:0 (OUI[3:18]) R
Type
†
Organizationally Unique Identifier.
Description
The third through the twenty-fourth bit of the
OUI assigned to the PHY manufacturer by the
IEEE
are to be placed in bits
2.15:0 and 3.15:10. This value is programmable.
3.15:10 (OUI[19:24]) R
Organizationally Unique Identifier.
The remaining 6 bits of the OUI. The value
for bits 24:19 is programmable.
3.9:4 (MODEL[5:0]) R
Model Number.
6-bit model number of the device. The model number is
programmable.
3.3:0 (VERSION[3:0]) R
Revision Number.
The value of the present revision number. The version num-
ber is programmable.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read.
Table 16. MR4—Autonegotiation Advertisement Register Bit Descriptions
Bit
*
4.15 (NEXT_PA GE) R/W
Type
†
Next Page.
Name/Description
The next page function is activated by setting this bit to a 1. This will
allow the exchange of additional data. Data is carried by optional next pages of
information.
4.14 (ACK) R/W
4.13 (REM_FAULT) R/W
Acknowledge.
Remote Fault.
This bit is the acknowledge bit from the link code word.
When set to 1, the DNC3X3825 indicates to the link partner a
remote fault cond ition.
4.12:11 R/W
4.10 (PAUSE) R/W
Reserved.
Pause.
When set to a 1, it indicates that the DNC3X3625 wishes to exchange flow
control information with its link partner.
4.9 (100BASET4) R/W
4.8 (100B ASET_FD) R/W
100Base-T4.
100Base-TX Full Duplex.
This bit should always be set to 0.
If written to 1, autonegotiation will advertise that the
DNC3X3825 is capable of 100Base-TX full-duplex operation.
4.7 (100BASETX) R/W
100Base-TX.
If written to 1, autonegotiation will advertise that the DNC3X3825 is
capable of 100Base-TX operation.
4.6 (10BASET_FD) R/W
10Base-T Full Duplex.
If written to 1, autonegotiation will advertise that the
DNC3X3825 is capable of 10Base-T full-duplex operation.
4.5 (10BASET) R/W
10Base-T.
If written to 1, autonegotiation will advertise that the DNC3X3825 is
capable of 10Base-T operation.
4.4:0 (SELECT) R/W
Selector Field
. Reset with the value 00001 for
IEEE
802.3.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
22
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Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information
Table 17. MR5—Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions
Bit
*
5.15 (LP_NEXT_PAGE) R
5.14 (LP_ACK) R
5.13 (LP_REM_FAULT) R
5.12:5 (LP_TECH_ABILITY) R
5.4:0 (LP_SELECT) R
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read.
Table 18. MR5—Autonegotiation Link P artner (LP) Ability Register (Next Page) Bit Descriptions
Bit
*
5.15 (LP_NEXT_PAGE) R
5.14 (LP_ACK) R
5.13 (LP__MES_PAGE) R
5.12 (LP_ACK2) R
5.11 (LP_TOGGLE) R
5.10:0 (MCF) R
(continued)
†
Type
Link Partner Next Page.
partner wishes to engage in next page exchange.
Link Partner Acknowledge.
link partner has successfully received at least three consecutive and consistent FLP bursts.
Remote Fault.
a fault.
Technology Ability Field.
link partner. These bits are similar to the bits defined for the MR4 register
(see Table 16).
Selector Field.
ner. For
†
Type
Next Page
page to be transmitted. A logic 1 indicates that additional pages will follow.
Acknowledge.
partner has successfully received its partner’s link code word.
Message Page.
ate a message page (logic 1) from an unformatted page (logic 0).
Acknowledge 2.
that a device has the ability to comply with the message (logic 1) or not
(logic 0).
Toggle
tion with the link partner during next page exchange. Logic 0 indicates that
the previous value of the transmitted link code word was logic 1. Logic 1
indicates that the previous value of the transmitted link code word was
logic 0.
Message/Unformatted Code Field
possible messages. Message code field definitions are described in annex
28C of the
Description
When this bit is set to 1, it indicates that the link
When this bit is set to 1, it indicates that the
When this bit is set to 1, it indicates that the link partner has
This field contains the technology ability of the
This field contains the type of message sent by the link part-
IEEE
802.3 compliant link partners, this field should read 00001.
Description
. When this bit is set to a logic 0, it indicates that this is the last
When this bit is set to a logic 1, it indicates that the link
This bit is used by the NEXT _PAGE function to differenti-
This bit is used by the NEXT_PAGE function to indicate
. This bit is used by the arbitration function to ensure synchroniza-
. With these 11 bits, there are 2048
IEEE
802.3u standard.
* The format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read.
23
Page 24
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Register Information
Table 19. MR6—Autonegotiation Expansion Register Bit Descriptions
Bit
*
6.15:5 (RESERVED) R
6.4 (PAR_DET_FAULT) R/LH
6.3 (LP_NEXT_PAGE_ABLE) R
6.2 (NEXT_PAGE_ABLE) R
6.1 (PAGE_REC) R/LH
6.0 (LP_NWAY_ABLE) R
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, LH = latched high.
(continued)
†
Type
Description
Reserved
Parallel Detection Fault.
has been detected in the parallel detection function. This fault is due to
more than one technology detecting concurrent link conditions. This bit
can only be cleared by reading this register.
Link Partner Next Page Able.
the link partner supports the next page function.
Next Page Able.
the NEXT_PAGE function.
Page Received
has been received.
Link Partner Autonegotiation Capable.
cates that the link partner is autonegotiation capable.
.
When this bit is set to 1, it indicates that a fault
When this bit is set to 1, it indicates that
This bit is set to 1, indicating that this device supports
. When this bit is set to 1, it indicates that a NEXT_PAGE
When this bit is set to 1, it indi-
24
Page 25
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information
(continued)
Table 20. MR7—Next Page Transmit Register Bit Descriptions
Bit
*
7.15 (NEXT_PAGE) R/W
Type
†
Next Page.
This bit indicates whether or not this is the last next page to be transmitted. When this bit is 0, it indicates that this is the last page. When this bit is 1, it
indicates there is an additional next page.
7.14 (ACK) R
7.13 (MESSAGE) R/W
Acknowledge.
Message Page.
This bit is the acknowledge bit from the link code word.
This bit is used to differentiate a message page from an unformatted page. When this bit is 0, it indicates an unformatted page. When this bit is 1, it
indicates a formatted page.
7.12 (ACK2) R/W
Acknowledge 2.
This bit is used by the next page function to indicate that a device
has the ability to comply with the message. It is set as follows:
■
When this bit is 0, it indicates the device cannot comply with the message.
■
When this bit is 1, it indicates the device will comply with the message.
7.11 (TOGGLE) R
Toggle.
This bit is used by the arbitration function to ensure synchronization with
the link partner during next page exchange. This bit will always take the opposite
value of the toggle bit in the previously exchanged link code word:
■
If the bit is a logic 0, the previous value of the transmitted link code word was a
logic 1.
■
If the bit is a 1, the previous value of the transmitted link code word was a 0.
Description
The initial value of the toggle bit in the first next page transmitted is the inverse of
the value of bit 11 in the base link code word, and may assume a value of 1 or 0.
7.10:0 (MCF) R/W
Message/Unformatted Code Field.
messages. Message code field definitions are described in annex 28C of the
With these 11 bits, there are 2048 possible
IEEE
802.3u standard.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
Table 21. MR16—PCS Control Register Bit Descriptions
Bit
*
16.15 (LOCKED) R
16.14-12 (Reserved) R
16.11 (ANA_RG21) R/W
16.10 (LPWR_TUN) R/W
16.9 (SMFIX_DA) R/W
16.8 (EN_NOWR) R/W
16.7-6 (ATST1:0) R/W
16.5 (BYPPD125) R/W
16.4 (BYPPD160) R/W
16.3 (LOOPBACK) R/W
Type
†
Locked.
Reserved.
Analog Regiser 21.
Low Power Tuner.
State Machine Fix.
Reserved.
Locked pin from descrambler block.
Should be written as 0.
Lucent Debug Register - Should be wrtten as 0.
Lucent Debug Register - Should be wrtten as 0.
Lucent Debug Register - Should be written as 0.
Should be written as 0.
Autonegotiation Testmode (1:0).
Bypass Powerdown 125.
Bypass Powerdown 160.
Loopback Configure.
OR’d with BYPPD125 Input
OR’d with BYPPD160 Input
When this bit is high, the entire loopback is performed in the
Description
Lucent Debug Register - Should be written 0
PCS macro. When this bit is low, only the collision pin is disabled in loopback.
16.2 (SCAN) R/W
16.1 (FORCE
R/W
LOOPBACK)
16.0 (SPEEDUP
R/W
COUNTERS)
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
Scan Test Mode
Force Loopback.
abling the collision pin.
Speedup Counters.
FASTTEST = 1.)
.
Force a loopback without forcing idle on the transmit side or dis-
Reduce link monitor counter to 10 µs from 620 µs. (Same as
25
Page 26
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Register Information
(continued)
Table 22. MR17—Autonegotiation Read Register A
Bit
*
17.15-13 R
17.12 R
17.11 R
17.10 R
17.9 R
17.8 R
17.7 R
17.6 R
17.5 R
17.4 R
17.3 R
17.2 R
17.1 R
17.0 R
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
Type
†
Description
Reserved. Always 0.
Next Page Wait.
Wait Link_Fail_Inhibit_Wait_Timer (Link Status Check).
Wait A utoneg_Wait_Timer (Link Status Check).
Wait Break_Link_Timer (Transmit Disable).
Parallel Detection Fault.
Autonegotiation Enable.
FLP Link Good Check.
Complete Acknowledge.
Acknowledge Detect.
FLP Link Good.
Link Status Check.
Ability Detect.
Transmit Disable.
Table 23. MR18—Autonegotiation Read Register B
Bit
*
18.15 R
18.14 R
18.13 R
18.12 R
18.11 R
18.10 R
18.9 R
18.8 R
18.7 R
18.6 R
18.5 R
18.4 R
18.3 R
18.2 R
18.1 R
18.0 R
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
Type
†
Receiving FLPs
FLP Pass
Link Pulse Count
Link Pulse Detect
T est Pass
Test Fail Count
Test Fail Extend
Wait Max Timer Ack
Detect Freeze
Test Fail
(NLP Rcv) .
Transmit Count Ack
Transmit Data Bit
Transmit Clock Bit
Transmit Ability
. Any of FLP Capture, Clock, Data_0, or Data_1 (FLP Rcv).
(FLP Rcv).
(FLP Rcv).
(FLP Rcv).
(NLP Rcv).
(NLP Rcv).
(NLP Rcv).
(NLP Rcv).
(NLP Rcv).
(FLP Xmit).
(FLP Xmit).
(FLP Xmit).
(FLP Xmit).
Transmit Remaining Acknowledge
Idle
(FLP Xmit).
Description
(FLP Xmit).
26
Page 27
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information
Table 24. MR20—User-Defined Register
Bit
*
20.15:0 R/W The data written into this user-defined register appears on the RG20_OUT[15:0]
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
Table 25. MR21—RXER Counter
Bit
*
21.0 W This bit, when 0 puts this register in 16-bit counter mode. When 1, it puts this regis-
21.15:0 R When in 16-bit counter mode, these maintain a count of RXERs. It is reset on a read
21.7:0 R When in 8-bit counter mode, these maintain a count of RXERs. It is reset on a read
21.11:8 R When in 8-bit mode, these contain a count of false carrier events (802.3 Section
21.15:12 R When in 8-bit mode, these contain a count of disconnect events (Link Unstable 6,
Type
Type
(continued)
†
bus.
†
ter in 8-bit counter mode. This bit is reset to a 0 and cannot be read.
operation.
operation.
27.3.1.5.1). It is reset on a read operaton.
802.3 Section 27.3.1.5.1). It is reset on a read operation.
Description
Description
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
Table 26. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions
Bit
*
28.15:9 (UNUSED) R
28.8 (BAD_FRM) R/LH
28.7 (CODE) R/LH
28.6 (APS) R
28.5 (DISCON) R/LH
28.4 (UNLOCKED) R/LH
28.3 (RXERR_ST) R/LH
28.2 (FRC_JAM) R/LH
Type
†
Unused.
Bad Frame.
SFD . This bit is only valid in 10 Mbits/s mode.
This bit is latching high and will only clear after it has been read or the device has
been reset.
Code Violation.
occurred. The error code will be output on the MRXD lines. Refer to Table 1 for a
detailed description of the MRXD pin error codes. This bit is only valid in
10 Mbits/s mode.
This bit is latching high and will only clear after it has been read or the device has
been reset.
Autopolarity Status.
the DNC3X3825 has detected and corrected a polarity reversal on the twisted pair.
If the APF_EN bit (register 30, bit 3) is set, the reversal will be corrected inside the
DNC3X3825. This bit is not valid in 100 Mbits/s operation.
Disconnect.
read. This bit is only valid in 100 Mbits/s mode.
Unlocked.
read. This bit is only valid in 100 Mbits/s mode.
RX Error Status.
is only valid in 100 Mbits/s mode.
Force Jam.
mode.
Read as 0.
If this bit is a 1, it indicates a packet has been received without an
When this bit is a 1, it indicates a Manchester code violation has
When register 30, bit 3 is set and this bit is a 1, it indicates
If this bit is a 1, it indicates a disconnect. This bit will latch high until
Indicates that the TX scrambler lost lock. This bit will latch high until
Indicates a false carrier. This bit will latch high until read. This bit
This bit will latch high until read. This bit is only valid in 100 Mbits/s
Description
27
Page 28
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Register Information
Table 26. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions
Bit
*
28.1 (LNK100UP) R
Type
(continued)
†
Link Up 100.
(continued)
Description
This bit, when set to a 1, indicates a 100 Mbits/s transceiver is up
and operational.
28.0 (LNK10UP) R
Link Up 10.
This bit, when set to a 1, indicates a 10 Mbits/s transceiver is up and
operational.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, LH = latched high.
Table 27. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions
Bit
*
29.15 (LOCALRST) R/W
Type
†
Management Reset.
Description
This is the local management reset bit. Writing a logic 1 to
this bit will cause the lower 16 registers and registers 28 and 29 to be reset to
their default values. This bit is self-clearing.
29.14 (RST1) R/W
29.13 (RST2) R/W
29.12 (100_OFF) R/W
Generic Reset 1.
Generic Reset 2.
100 Mbits/s Transmitter Off.
This register is used for manufacture test only.
This register is used for manufacture test only.
When this bit is set to 0, it forces TPI low and
TPIB high. This bit defaults to 1.
29.11 (LE D_BLINK R/W
29.10 (CRS_SEL) R/W
LED Blinking.
LED_BLINK_EN. Default is 0.
Carrier Sense Select.
This register, when 1, enables LED blinking. This is ORed with
MCRS will be asserted on receive only when this bit is
set to a 1. If this bit is set to logic 0, MCRS will by asserted on receive or transmit. This bit is ORed with the CRS_SEL pin.
29.9 (LINK_ERR) R/W
Link Error Indication.
When this bit is a 1, a link error code will be reported on
MRXD[3:0] of the DNC3X3825 when MRX_ER is asserted on the MII. The specific error codes are listed in the MRXD pin description. If it is 0, it will disable this
function.
29.8 (PKT_ERR) R/W
Packet Error Indication Enable.
When this bit is a 1, a packet error code,
which indicates that the scrambler is not locked, will be reported on MRXD[3:0]
of the DNC3X3825 when MRX_ER is asserted on the MII. When this bit is 0, it
will disable this function.
29.7 (PULSE_STR) R/W
Pulse Stretching.
When this bit is set to 1, the CS, XS, and RS output signals
will be stretched between approximately 42 ms—84 ms. If this bit is 0, it will disable this feature. Default state is 0.
29.6 (EDB) R/W
Encoder/Decoder Bypass.
When this bit is set to 1, the 4B/5B encoder and
5B/4B decoder function will be disabled. This bit is ORed with the EDBT pin.
29.5 (SAB) R/W
Symbol Aligner Bypass.
When this bit is set to 1, the aligner function will be
disabled.
29.4 (SDB) R/W
Scrambler/Descrambler Bypass.
When this bit is set to 1, the scrambling/
descrambling functions will be disabled. This bit is ORed with the SDBT pin.
29.3 (CARIN_EN) R/W
Carrier Integrity Enable.
When this bit is set to a 1, carrier integrity is enabled.
This bit is ORed with the CARIN_EN pin.
29.2 (JAM_COL) R/W
Jam Enable.
When this bit is a 1, it enables JAM associated with carrier integrity
to be ORed with MCOLMCRS.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
28
Page 29
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Register Information
Table 27. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions
Bit
*
29.1 (FEF_EN) R/W
29.0 (FX) R/W
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
Table 28. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions
Bit
*
30.15 (Test10TX) R/W When high and 10Base-T is powered up, a continuous 10 MHz signal (1111)
30.14 (RxPLLEn) R/W When high, all 10Base-T logic will be powered up when the link is up. Other-
30.13 (JAB_DIS) R/W
30.12:7 (Reserved) R/W
30.6 (LITF_ENH) R/W
30.5 (HBT_EN) R/W
30.4 (ELL_EN) R/W
30.3 (APF_EN) R/W
Type
Type
(continued)
(continued)
†
Far-End Fault Enable
transmission capability. This capability may only be used if autonegotiation is
disabled. This capability is to be used only with media which does not support
autonegotiation. Setting this bit to 1 enables far-end fault detection, and logic 0
will disable the function. Default state is 0.
Fiber-Optic Mode.
This bit is ORed with FX_MODE.
†
will be transmitted. This is only meant for testing. Default is 0.
wise, portions of the logic will be powered down when no data is being
received to conserve power. Default is 0.
Jabber Disable.
10Base-T receive. Default is 0.
Reserved.
Enhanced Link Integrity Test Function.
This is ORed with the LITF_ENH input. Default is 0.
Heartbeat Enable.
Valid in 10 Mbits/s mode only.
Extended Line Length Enable.
els are reduced from a nominal 435 mV to 350 mV, allowing reception of signals with a lower amplitude. Valid in 10 Mbits/s mode only.
Autopolarity Function Disable.
in 10 Mbits/s mode, the autopolarity function will determine if the TP link is
wired with a polarity reversal.
When this bit is 1, disables the jabber function of the
Should be written as 0.
. This bit is used to enable the far-end fault detection and
When this bit is a 1, the DNC3X3825 is in fiber-optic mode.
When this bit is a 1, the heartbeat function will be enabled.
Description
Description
When high, function is enabled.
When this bit is a 1, the receive squelch lev-
When this bit is a 0 and the DNC3X3825 is
If there is a polarity reversal, the DNC3X3825 will assert the APS bit (register
28, bit 6) and correct the polarity reversal. If this bit is a 1 and the device is in
10 Mbits/s mode, the reversal will not be corrected.
30.2 (RESERVED) R/W
30.1 (SERIAL _SEL) R/W
30.0 (ENA_NO_LP) R/W
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
Reserved
Serial Select.
selected. When the DNC3X3825 is in 100 Mbits/s mode, this bit will be
ignored.
No Link Pulse Mode.
with link pulses disabled. If the DNC3X3825 is configured for 100 Mbits/s
operation, setting this bit will not affect operation.
. Should be written as 0.
When this bit is set to a 1, 10 Mbits/s serial mode will be
Setting this bit to a 1 will allow 10 Mbits/s operation
29
Page 30
DNC3X3825 Advance Data Sheet
Octal 10/100 Mbits/s Ethernet Transceiver Macrocell March 2000
Register Information
(continued)
Table 29. MR31—Device-Specific Register 4 (Quick Status) Bit Descriptions
Register/Bit
31.15 (ERROR) R
31.14 (RXERR_ST)/
(LINK_STAT_CHANGE)
31.13 (REM_FLT) R
31.12 (UNLOCKED)/
(JABBER)
31.11 (LSTAT_OK) R
31.10 (PAUSE) R
31.9 (SPEED100) R
31.8 (FULL_DUP) R
31.7 (INT_CONF) R/W
31.6 (INT_MASK) R/W
31.5:3
(LOW_AUTO__STATE)
31.2:0
(HI_AUTO_STATE)
*
Type
R
R
R
R
†
Receiver Error.
detected. This bit is valid in 100 Mbits/s only. This bit will remain set until cleared by
reading the register. Default is a 0.
False Carrier.
detect state machine has found a f alse carrier . This bit is valid in 100 Mbits/ s only. This
bit will remain set until cleared by reading the register. Default is 0.
Link Status Change.
LINK_STAT_CHANGE bit and goes high whenever there is a change in link status (bit
[31.11] changes state).
Remote Fault.
bit will remain set until cleared by reading the register. Default is a 0.
Unlocked/Jabber.
that the TX descrambler has lost lock. If this bit is set when operating in 10 Mbits/s
mode, it indicates a jabber condition has been detected. This bit will remain set until
cleared by reading the register.
Link Status.
has a latching low function: a link failure will cause the bit to clear and stay cleared
until it has been read via the management interface.
Link Partner Pause.
wishes to exchange flow control information.
Link Speed.
100 Mbits/s. When this bit is a 0, it indicates that the link is operating at 10 Mbits/s.
Duplex Mode.
full-duplex mode. When this bit is a 0, it indicates that the link has negotiated to halfduplex mode.
Interrupt Configuration.
RXERR_ST bit and the interrupt pin (MASK_STAT_INT) goes high whenever any of
bits [31.15:12] go high, or bit [31.11] goes low. When this bit is set high, it redefines
bit [31.14] to become the LINK_STAT_CHANGE bit, and the interrupt pin
(MASK_STAT_INT) goes high only when the link status changes (bit [31.14] goes
high). This bit defaults to 0.
Interrupt Mask.
condition. When set low, interrupts are generated according to bit [31.7].
Lowest Autonegotiation State.
tiation state reached since the last register read, in the priority order defined below:
000: Autonegotiation enable.
001: Transmit disable or ability detect.
010: Link status check.
011: Acknowledge detect.
100: Complete acknowledge.
101: FLP link good check.
110: Next page wait.
111: FLP link good.
Highest Autonegotiation State.
gotiation state reached since the last register read, as defined above for bit [31.5:3].
When this bit is a 1, it indicates that a receive error has been
When bit [31.7] is set to 0 and this bit is a 1, it indicates that the carrier
When bit [31.7] is set to a 1, this bit is redefined to become the
When this bit is a 1, it indicates a remote fault has been detected. This
If this bit is set when operating in 100 Mbits/s mode, it indicates
When this bit is a 1, it indicates a v ali d link has been estab lished. This bit
When this bit is set to a 1, it indicates that the DNC3X3825
When this bit is set to a 1, it indicates that the link has negotiated to
When this bit is set to a 1, it indicates that the link has negotiated to
When this bit is set to a 0, it defines bit [31.14] to be the
When set high, no interrupt is generated by this channel under any
Description
These 3 bits report the state of the lowest autonego-
These 3 bits report the state of the highest autone-
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
30
Page 31
Advance Data Sheet DNC3X3825
4
March 2000 Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
Application Notes: Board Layout
Board Layout Considerations
In order to obtain optimum performance, careful attention must be paid to the circuit board layout, shielding,
and the placement of components. Careful routing of
high-speed lines is mandatory. Power supply input pins
must be protected from noisy conditions by proper filtering. To achieve these design goals, the following
steps are recommended as a minimum.
1. As a minimum, a four-layer circuit board, with twoounce copper planes, should be used. This will minimize the switching transients by providing a lowimpedance power source. The signal planes should
be isolated from each other by the power and/or
ground planes. Do not segment the ground plane
except around the RJ-45 connectors and magnetics
module as described below. Use a single, continuous plane. The reference design will be a six-layer
board.
2. Po wer and ground planes should extend underneath
the ASIC up to the input of the magnetic module.
Power and ground planes should not extend under
any network signal path, or the magnetics module,
because common-mode power supply noise will be
coupled to the signals. The greater the distance
between the planes and the network signals, the
lower the EMI emissions. Chassis ground may be
used under the RJ-45 connector s if desi red.
3. The power plane of the ASIC should be separated
into three regions: digital power (V
PWB’ s V
driver power (V
V
DDA
plane), analog power (V
DD
). For conservative designs, the
DDO
segment and the V
segment, should be fil-
DDO
tered with a ferrite bead, 10 µF, and 0.01 µF capacitors before connecting to the V
wide trace. Pins 80 V
DDPLL
DD
and 83 V
connected together and filtered with a ferrite bead
and 10 µF and 0.01 µF capacitors for conservative
designs. Refer to Figure 3 for suggested layout. Do
not overlay different power planes on different lay ers,
unless they are separated by a ground plane. When
segmenting power planes on the same layer they
should be separated by at least three times the distance to the nearest ground layer.
4. The liberal use of capacitors on each the power pins
of the ASIC will minimize any noise coupled into the
power plane. Power supply noise contributes to the
EMI emissions in circuit layouts. Low ESR capacitors
this is the
DDD;
), and output
DDA
plane with a heavy
can be
DDPD
between the power and ground planes must be
placed as close as possible to all the DNC3X3825
power pins. Low-inductance short connections to
each power pin and the ground plane are required.
This can be achieved by using short traces to the
power pins and connecting to the ground plane with
two vias. Multilayer ceramic capacitors with good
quality dielectric such as NPO or X7R (avoid using
Z5U) are recommended for the low ESR capacitors.
A 0.01 µF capacitor should be used on every pin, for
conservative designs two capacitors can be used on
every pin a 0.1 µF and a 0.001 µF.
5. Route the transmit and receive pairs between the
ASIC, the magnetics, and the RJ-45 connectors as
short, straight, and equal length as possible. These
traces should be routed with 50 Ω impedance to the
nearest power/ground plane with a differential
impedance of 100 Ω
. Keep the separation between
adjacent pairs on the same layer, 2 mm or more if
possible to minimize crosstalk.
6. The most EMI critical routing is between the magnetic module (after common-mode filters) and the
RJ-45 connectors. Use the chassis of the system to
allow coupled noise to flow to ground via common
mode terminations. The chassis is not a perfect
ground, but with proper power supply design, the
chassis can be used to redirect some commonmode noise.
7. Reduce the number of vias on the transmit path.
Vias can have resonance at critical frequencies
degrading EMI emissions performance. The transmit
differential pairs from the RJ-45 to the magnetics
and the DNC3X3825 can be run on the top layer of
the board. Vias on the receive path should be minimized but are less critical because the signal energy
is less th an on th e tr an smi t pa th. Th e rec eive signa ls
can be run on a buried layer or on the bottom layer.
8. Ensure that the 25 MHz crystal and the load capacitors (33 pF), or the oscillator (25 MHz, 50 MHz, or
125 MHz, if used), are located as close to the XLO/
XHI pins as possible. All bias resistors (pins 13, 25,
42, and 43) and reference capacitor (pin 81) must be
located within close proximity to the PHY. This will
reduce the coupled noise into the bias circuits. Place
receive twisted-pair terminating resistors (100 Ω) as
close to PHY pins as possible.
9. Never route clock or high-speed signal lines under
the ASIC unless the lines are under a ground or
power plane.
31
Page 32
For additional information, contact your Microelectronics Group Account Manager or the following:
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Tel. (86) 21 6440 0468, ext. 316
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Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
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Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
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(Helsinki),
March 2000
DS00-081LAN (replaces DS99-194LAN)
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