Datasheet DAC714U, DAC714P, DAC714HL, DAC714HC, DAC714HB Datasheet (Burr Brown Corporation)
Page 1
®
DAC714
16-Bit DIGITAL-TO-ANALOG CONVERTER
With Serial Data Interface
FEATURES:
● SERIAL DIGITAL INTERFACE
● VOLTAGE OUTPUT:
●
±1 LSB INTEGRAL LINEARITY
16-BIT MONOTONIC OVER TEMPERATURE
●
● PRECISION INTERNAL REFERENCE
● LOW NOISE: 120nV/ √Hz Including Reference
● 16-LEAD PLASTIC AND CERAMIC SKINNY
DIP AND PLASTIC SOIC PACKAGES
A
0
A
1
SDI
CLK
CLR
±10V, ±5V, 0 to +10V
Input Shift Register
D/A Latch
DESCRIPTION
The DAC714 is a complete monolithic digital-toanalog converter including a +10V temperature compensated reference, current-to-voltage amplifier, a
high-speed synchronous serial interface, a serial output which allows cascading multiple converters, and
an asynchronous clear function which immediately
sets the output voltage to midscale.
The output voltage range is ±10V, ±5V, or 0 to +10V
while operating from ±12V or ±15V supplies. The
gain and bipolar offset adjustments are designed so
that they can be set via external potentiometers or
external D/A converters. The output amplifier is protected against short circuit to ground.
The 16-pin DAC714 is available in a plastic 0.3" DIP,
ceramic 0.3" CERDIP, and wide-body plastic SOIC
package. The DAC714P, U, HB, and HC are specified
over the –40°C to +85°C temperature range while the
DAC714HL is specified over the 0°C to +70°C range.
SDO
16
R
FB2
16
Reference
Circuit
V
REF OUT
Adjust
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1994 Burr-Brown Corporation PDS-1252D Printed in U.S.A. July, 1997
+10V
16-Bit D/A Converter
R
BPO
V
OUT
Offset AdjustGain
®
1
DAC714
Page 2
SPECIFICATIONS
At TA = +25°C, +V
PARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error ±4 ±2 ±1 ±1 LSB
T
to T
MIN
MAX
Differential Linearity Error ±4 ±2 ±1 ±1 LSB
T
to T
MIN
MAX
Monotonicity 14 15 16 16 Bits
Monotonicity Over Spec Temp Range 13 14 15 16 Bits
Gain Error
T
to T
MIN
MAX
Unipolar/Bipolar Zero Error
T
to T
MIN
MAX
Power Supply Sensitivity of Gain ±0.003 ±0.003 ±0.003 ±0.003 %FSR/%V
DYNAMIC PERFORMANCE
Settling Time
(to ±0.003%FSR, 5kΩ || 500pF Load)
20V Output Step 6 10 6 10 6 10 6 10 µs
1LSB Output Step
Output Slew Rate 10 10 10 10 V/µs
Total Harmonic Distortion
0dB, 1001Hz, f
–20dB, 1001Hz, f
–60dB, 1001Hz, f
SINAD: 1001Hz, f
Digital Feedthrough
Digital-to-Analog Glitch Impulse
Output Noise Voltage (includes reference)
ANALOG OUTPUT
Output Voltage Range
+V
, –VCC = ±11.4V ±10 ±10 ±10 ±10 V
CC
Output Current ±5 ±5 ±5 ±5mA
Output Impedance 0.1 0.1 0.1 0.1 Ω
Short Circuit to ACOM Duration Indefinite Indefinite Indefinite Indefinite
REFERENCE VOLTAGE
Voltage +9.975 +10.000 +10.025 +9.975 +10.000 +10.025 +9.975 +10.000 +10.025 +9.975 +10.000 +10.025 V
T
to T
MIN
MAX
Output Resistance 1 1 1 1 Ω
Source Current 2 2 2 2 mA
Short Circuit to ACOM Duration Indefinite Indefinite Indefinite Indefinite
INTERFACE
RESOLUTION 16 16 16 16 Bits
DIGITAL INPUTS
Serial Data Input Code
Logic Levels
V
IH
V
IL
(VI = +2.7V) ±10 ±10 ±10 ±10 µA
I
IH
(VI = +0.4V) ±10 ±10 ±10 ±10 µA
I
IL
DIGITAL OUTPUT
Serial Data
V
OL (ISINK
V
OH (ISOURCE
POWER SUPPLY REQUIREMENTS
Voltage
+V
CC
–V
CC
Current (No Load, ±15V Supplies)
+V
CC
–V
CC
Power Dissipation
TEMPERATURE RANGES
Specification
All Grades –40 +85 –40 +85 –40 +85 0 +70 °C
Storage –60 +150 –60 +150 –60 +150 –60 +150 °C
Thermal Coefficient,
NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for ±10V output, FSR = 20V. (3) Errors
externally adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst-case Binary Two’s Complement code changes: FFFF
to FFFFH. (6) During power supply turn on, the transient supply current may approach 3x the maximum quiescent specification. (7) Typical (i.e. rated) supply voltages times maximum currents.
= +12V and +15V, –VCC = –12V, and –15V, unless otherwise noted.
CC
DAC714P, U DAC714HB DAC714HC DAC714HL
±8 ±4 ±2 ±2 LSB
±8 ±4 ±2 ±1 LSB
(3)
(3)
±0.1 ±0.1 ±0.1 ±0.1 %
±0.25 ±0.25 ±0.25 ±0.25 %
±0.1 ±0.1 ±0.1 ±0.1 % of FSR
±0.2 ±0.2 ±0.2 ±0.2 % of FSR
±30 ±30 ±30 ±30 ppm FSR/%V
(4)
(5)
= 100kHz 0.005 0.005 0.005 0.005 %
S
= 100kHz 0.03 0.03 0.03 0.03 %
S
= 100kHz 3.0 3.0 3.0 3.0 %
S
= 100kHz 87 87 87 87 dB
S
(5)
(5)
4444µs
2 2 2 2 nV–s
15 15 15 15 nV–s
120 120 120 120 nV/√Hz
+9.960 +10.040 +9.960 +10.040 +9.960 +10.040 +9.960 +10.040 V
(1)
+2.0
(VCC –1.4)
+2.0
Binary Two’s Complement
(VCC –1.4)
+2.0
(VCC –1.4)
+2.0
(VCC –1.4)
0 +0.8 0 +0.8 0 +0.8 0 +0.8 V
= 1.6mA) 0 +0.4 0 +0.4 0 +0.4 0 +0.4 V
= 500µA), T
MIN
to T
+2.4 +5 +2.4 +5 +2.4 +5 +2.4 +5 V
MAX
+11.4 +15 +16.5 +11.4 +15 +16.5 +11.4 +15 +16.5 +11.4 +15 +16.5 V
–11.4 –15 –16.5 –11.4 –15 –16.5 –11.4 –15 –16.5 –11.4 –15 –16.5 V
(6)
13 16 13 16 13 16 13 16 mA
(7)
θ
JA
®
DAC714
22 26 22 26 22 26 22 26 mA
625 625 625 625 mW
75 75 75 75 °C/W
to 0000H and 0000
H
2
(2)
CC
CC
V
H
Page 3
PIN CONFIGURATION
Top View
1
CLK
2
A
0
3
A
1
4
SDI
5
SDO
6
DCOM
7
+V
CC
8
ACOM
DAC714
16
CLR
15
–V
14
Gain Adjust
13
Offset Adjust
12
V
11
R
10
R
9
V
CC
REF OUT
BPO
FB2
OUT
SOIC/DIP
PIN DESCRIPTIONS
PIN LABEL DESCRIPTION
1 CLK Serial Data Clock
2A
3A
4 SDI Serial Data Input
5 SDO Serial Data Output
6 DCOM Digital Ground
7+V
8 ACOM Analog Ground
9V
10 R
11 R
12 V
13 Offset Adjust Offset Adjust
14 Gain Adjust Gain Adjust
15 –V
16 CLR Clear
0
1
CC
OUT
FB2
BPO
REF OUT
CC
Enable for Input Register (Active Low)
Enable for D/A Latch (Active Low)
Positive Power Supply
D/A Output
±10V Range Feedback Output
Bipolar Offset
Voltage Reference Output
Negative Power Supply
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
ABSOLUTE MAXIMUM RATINGS
to Common .................................................................... 0V to +17V
+V
CC
–V
to Common .................................................................... 0V to –17V
CC
+V
to –VCC....................................................................................... 34V
CC
ACOM to DCOM ............................................................................... ±0.5V
Digital Inputs to Common............................................. –1V to (V
External Voltage Applied to BPO and Range Resistors..................... ±V
V
......................................................... Indefinite Short to Common
REF OUT
V
............................................................... Indefinite Short to Common
OUT
SDO ............................................................... Indefinite Short to Common
Power Dissipation .......................................................................... 750mW
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s)................................................ +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
(1)
CC
–0.7V)
CC
ORDERING INFORMATION
PRODUCT PACKAGE max at +25
DAC714P Plastic DIP ±4 LSB –40°C to +85°C
DAC714U Plastic SOIC ±4 LSB –40°C to +85°C
DAC714HB Ceramic DIP ±2 LSB –40°C to +85°C
DAC714HC Ceramic DIP ±1 LSB –40°C to +85°C
DAC714HL Ceramic DIP ±1 LSB 0°C to +70°C
LINEARITY ERROR TEMPERATURE
°C RANGE
PACKAGE INFORMATION
PRODUCT PACKAGE NUMBER
PACKAGE DRAWING
DAC714P Plastic DIP 180
DAC714U Plastic SOIC 211
DAC714H Ceramic DIP 129
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet,
or Appendix C of Burr-Brown IC Data Book.
(1)
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
3
DAC714
®
Page 4
TIMING SPECIFICATIONS
TA = –40°C to +85°C, +VCC = +12V or +15V, –VCC = –12V or –15V.
SYMBOL PARAMETER MIN MAX UNITS
t
CLK
t
CL
t
CH
t
A0S
t
A1S
t
AOH
t
A1H
t
DS
t
DH
t
DSOP
t
CP
Data Clock Period 100 ns
Clock LOW 50 ns
Clock HIGH 50 ns
Setup Time for A
Setup Time for A
Hold Time for A
Hold Time for A
Setup Time for DATA 50 ns
0
1
0
1
50 ns
50 ns
0ns
0ns
Hold Time for DATA 10 ns
Output Propagation Delay 140 ns
Clear Pulsewidth 200 ns
TIMING DIAGRAMS
Serial Data In
t
CLK
Serial Data Input
MSB First
Latch Data
In D/A Latch
CLK
SDI
t
CH
A
0
A
1
t
CL
t
A0S
t
DS
D
15
TRUTH TABLE
A
A
0
011 → 0 → 1 1 Shift Serial Data into SDI
101 → 0 → 1 1 Load D/A Latch
111 → 0 → 1 1 No Change
001 → 0 → 1 1 Two Wire Operation
X X 1 1 No Change
X X X 0 Reset D/A Latch
NOTES: X = Don’t Care. (1) All digital input changes will appear at the
output.
t
A0H
t
DH
D
14
D
0
CLK CLR DESCRIPTION
1
t
A1S
t
A1H
(1)
Serial Data
Out
CLK
A
SDO
CLR
Serial Data Out
t
CLK
t
CH
0
t
DSOP
t
CL
t
A0S
D
15
D
14
Clear
t
A0H
D
0
t
DSOP
t
CP
®
DAC714
4
Page 5
TYPICAL PERFORMANCE CURVES
1000
100
10
1
1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)
nV/√Hz
V
OUT
SPECTRAL NOISE DENSITY
At TA = +25°C, VCC = ±15V, unless otherwise noted.
POWER SUPPLY REJECTION vs
POWER SUPPLY RIPPLE FREQUENCY
1k
–V
100
10
(ppm of FSR/ %)
1
0.1
[Change in FSR]/[Change in Supply Voltage]
10 100 1k 10k 100k 1M
Frequency (Hz)
± FULL SCALE OUTPUT SWING
10
OUT
0
V (V)
–10
Time (10µs/div)
LOGIC vs V LEVEL
2.0
CC
+V
CC
1.0
A
, A
0
1
CLR
0
I Digital Input (µA)
–1.0
SDI
–2.0
–0.85 0 2.55 4.25 5.95 6.8
0.85 1.7 3.4 5.1
V Digital Input
SETTLING TIME, +10V TO –10V
2500
2000
1500
+5V
0V
(V)
1
A
1000
500
0
–500
–1000
∆ Around –10V (µV)
–1500
–2000
–2500
Time (1µs/div)
2500
SETTLING TIME, –10V TO +10V
2000
1500
1000
500
0
–500
–1000
∆ Around +10V (µV)
–1500
–2000
–2500
Time (1µs/div)
+5V
0V
1
A
®
5
DAC714
Page 6
DISCUSSION OF
SPECIFICATIONS
LINEARITY ERROR
Linearity error is defined as the deviation of the analog
output from a straight line drawn between the end points of
the transfer characteristic.
DIFFERENTIAL LINEARITY ERROR
Differential linearity error (DLE) is the deviation from
1LSB of an output change from one adjacent state to the
next. A DLE specification of ±1/2LSB means that the output
step size can range from 1/2LSB to 3/2LSB when the digital
input code changes from one code word to the adjacent code
word. If the DLE is more positive than –1LSB, the D/A is
said to be monotonic.
MONOTONICITY
A D/A converter is monotonic if the output either increases
or remains the same for increasing digital input values.
Monotonicity of the C and L grades is guaranteed over the
specification temperature range to 16 bits.
SETTLING TIME
Settling time is the total time (including slew time) for the
D/A output to settle to within an error band around its final
value after a change in input. Settling times are specified to
within ±0.003% of Full Scale Range (FSR) for an output
step change of 20V and 1LSB. The 1LSB change is measured at the Major Carry (FFFFH to 0000H, and 0000H to
FFFFH: BTC codes), the input transition at which worst-case
settling time occurs.
TOTAL HARMONIC DISTORTION
Total harmonic distortion is defined as the ratio of the
square root of the sum of the squares of the values of the
harmonics to the value of the fundamental frequency. It is
expressed in % of the fundamental frequency amplitude at
sampling rate f
SIGNAL-TO-NOISE
AND DISTORTION RATIO (SINAD)
SINAD includes all the harmonic and outstanding spurious
components in the definition of output noise power in
addition to quantizing and internal random noise power.
SINAD is expressed in dB at a specified input frequency and
sampling rate, f
DIGITAL-TO-ANALOG GLITCH IMPULSE
The amount of charge injected into the analog output from
the digital inputs when the inputs change state. It is measured at half scale at the input codes where as many as
possible switches change state—from 0000
.
S
.
S
to FFFFH.
H
DIGITAL FEEDTHROUGH
When the A/D is not selected, high frequency logic activity
on the digital inputs is coupled through the device and shows
up as output noise. This noise is digital feedthrough.
OPERATION
The DAC714 is a monolithic integrated-circuit 16-bit D/A
converter complete with 16-bit D/A switches and ladder
network, voltage reference, output amplifier and a serial
interface.
INTERFACE LOGIC
The DAC714 has double-buffered data latches. The input
data latch holds a 16-bit data word before loading it into the
second latch, the D/A latch. This double-buffered organization permits simultaneous update of several D/A converters.
All digital control inputs are active low. Refer to the block
diagram shown in Figure 1.
All latches are level-triggered. Data present when the enable
inputs are logic “0” will enter the latch. When the enable
inputs return to logic “1”, the data is latched.
The CLR input resets both the input latch and the D/A latch
to 0000
LOGIC INPUT COMPATIBILITY
The DAC714 digital inputs are TTL compatible (1.4V switching level), low leakage, and high impedance. Thus the inputs
are suitable for being driven by any type of 5V logic Family,
such as CMOS. An equivalent circuit for the digital inputs
is shown in Figure 2.
The inputs will float to logic “0” if left unconnected. It is
recommended that any unused inputs be connected to DCOM
to improve noise immunity.
Digital inputs remain high impedance when power is off.
INPUT CODING
The DAC714 is designed to accept binary two’s complement (BTC) input codes with the MSB first which are
compatible with bipolar analog output operation. For this
configuration, a digital input of 7FFF
scale output, 8000H produces a minus full scale output, and
0000H produces bipolar zero output.
INTERNAL REFERENCE
The DAC714 contains a +10V reference. The reference
output may be used to drive external loads, sourcing up to
2mA. The load current should be constant, otherwise the
gain and bipolar offset of the converter will vary.
(midscale).
H
produces a plus full
H
®
DAC714
6
Page 7
Gain Adjust
+ Full Scale
All Bits
Logic 0
Range of
Offset Adjust
Offset Adj.
Translates
the Line
Digital Input
All Bits
Logic 1
Analog Output
Full Scale
Range
Gain Adjust
Rotates the Line
– Full Scale
MSB on All
Others Off
Bipolar
Offset
Range of
Gain Adjust
≈ ±0.3%
≈ ±0.3%
14 12
V
REF OUT
+V
– V
CC
7
CC
15
CLK
CLR
180Ω
15kΩ
+2.5V
1
3A
1
16
2A
0
4SDI
5SDO
–V
CC
+10V
Reference
D/A Switches
Shift Register
DAC Latch
16
10kΩ
8 6
ACOM
250Ω
9750Ω
10kΩ
DCOM
R
10
FB2
R
11
BPO
Offset
13
Adjust
V
9
OUT
FIGURE 1. DAC714 Block Diagram.
+V
CC
ESD Protection Circuit
Digital
Input
–V
1kΩ
6.8V 5pF
CC
FIGURE 2. Equivalent Circuit of Digital Inputs.
OUTPUT VOLTAGE SWING
The output amplifier of the DAC714 is designed to achieve
a ±10V output range while operating on ±11.4V or higher
power supplies.
GAIN AND OFFSET ADJUSTMENTS
Figure 3 illustrates the relationship of offset and gain adjustments for a bipolar connected D/A converter. Offset should
be adjusted first to avoid interaction of adjustments. See
Table I for calibration values and codes. These adjustments
have a minimum range of ±0.3%.
FIGURE 3. Relationship of Offset and Gain Adjustments.
Offset Adjustment
Apply the digital input code, 8000
, that produces the maxi-
H
mum negative output voltage and adjust the offset potentiometer
or the offset adjust D/A converter for –10V (or 0V unipolar).
7
DAC714
®
Page 8
DAC714 CALIBRATION VALUES
DIGITAL INPUT CODE ANALOG OUTPUT (V)
BINARY TWO’S BIPOLAR UNIPOLAR
COMPLEMENT, BTC 20V RANGE 10V RANGE DESCRIPTION
7FFF
|
4000
|
0001
0000
FFFF
|
C000
|
8000
H
H
H
H
H
H
H
+9.999695 +9.999847 + Full Scale –1LSB
+5.000000 +7.500000 3/4 Scale
+0.000305 +5.000153 BPZ + 1LSB
0.000000 +5.000000 Bipolar Zero (BPZ)
–0.000305 +4.999847 BPZ – 1LSB
–5.000000 +2.500000 1/4 Scale
–10.00000 0.000000 Minus Full Scale
TABLE I. Digital Input and Analog Output Voltage Calibra-
tion Values.
Gain Adjustment
Apply the digital input that gives the maximum positive
voltage output. Adjust the gain potentiometer or the gain
adjust D/A converter for this positive full scale voltage.
INSTALLATION
GENERAL CONSIDERATIONS
Due to the high-accuracy of the DAC714 system design
problems such as grounding and contact resistance become
very important. A 16-bit converter with a 20V full-scale
range has a 1LSB value of 305µV. With a load current of
5mA, series wiring and connector resistance of only 60mΩ
will cause a voltage drop of 300µV. To understand what this
means in terms of a system layout, the resistivity of a typical
1 ounce copper-clad printed circuit board is 1/2 mΩ per
square. For a 5mA load, a 10 milliinch wide printed circuit
conductor 60 milliinches long will result in a voltage drop of
150µV.
The analog output of DAC714 has an LSB size of 305µV
(–96dB) in the bipolar mode. The rms noise floor of the D/A
should remain below this level in the frequency range of
interest. The DAC714’s output noise spectral density (which
includes the noise contributed by the internal reference,) is
shown in the Typical Performance Curves section.
Wiring to high-resolution D/A converters should be routed
to provide optimum isolation from sources of RFI and EMI.
The key to elimination of RF radiation or pickup is small
loop area. Signal leads and their return conductors should be
kept close together such that they present a small capture
cross-section for any external field. Wire-wrap construction
is not recommended.
POWER SUPPLY AND
REFERENCE CONNECTIONS
Power supply decoupling capacitors should be added as
shown in Figure 4. Best performance occurs using a 1 to
10µF tantalum capacitor at –V
. Applications with less
CC
+12V to +15V
1µF
1
2
3
4
DAC714
5
6
DCOM
7
+V
CC
+
8
ACOM
–V
16
–12V to –15V
15
CC
14
13
12
11
10
1µF
+
9
FIGURE 4. Power Supply Connections.
critical settling time may be able to use 0.01µF at –V
CC
as well as at +VCC. The capacitors should be located
close to the package.
The DAC714 has separate ANALOG COMMON and DIGITAL COMMON pins. The current through DCOM is mostly
switching transients and are up to 1mA peak in amplitude.
The current through ACOM is typically 5µA for all codes.
Use separate analog and digital ground planes with a single
interconnection point to minimize ground loops. The analog
pins are located adjacent to each other to help isolate analog
from digital signals. Analog signals should be routed as far
as possible from digital signals and should cross them at
right angles. A solid analog ground plane around the D/A
package, as well as under it in the vicinity of the analog and
power supply pins, will isolate the D/A from switching
currents. It is recommended that DCOM and ACOM be
connected directly to the ground planes under the package.
If several DAC714s are used or if DAC714 shares supplies
with other components, connecting the ACOM and DCOM
lines to together once at the power supplies rather than at
each chip may give better results.
LOAD CONNECTIONS
Since the reference point for V
OUT
and V
REF OUT
is the
ACOM pin, it is important to connect the D/A converter load
directly to the ACOM pin. Refer to Figure 5.
Lead and contact resistances are represented by R
through
1
R3. As long as the load resistance RL is constant, R1 simply
introduces a gain error and can be removed by gain adjustment of the D/A or system-wide gain calibration. R2 is part
of RL if the output voltage is sensed at ACOM.
In some applications it is impractical to return the load to the
ACOM pin of the D/A converter. Sensing the output voltage
at the SYSTEM GROUND point is reasonable, because there
is no change in DAC714 ACOM current, provided that R
is
3
a low-resistance ground plane or conductor. In this case you
may wish to connect DCOM to SYSTEM GROUND as well.
®
DAC714
8
Page 9
GAIN AND OFFSET ADJUST
Connections Using Potentiometers
GAIN and OFFSET adjust pins provide for trim using
external potentiometers. 15-turn potentiometers provide sufficient resolution. Range of adjustment of these trims is at
least ±0.3% of Full Scale Range. Refer to Figure 6.
Using D/A Converters
The GAIN ADJUST and OFFSET ADJUST circuits of
the DAC714 have been arranged so that these points may
be easily driven by external D/A converters. Refer to
Figure 7. 12-bit D/A converters provide an OFFSET
adjust resolution and a GAIN adjust resolution of 30µV
to 50µV per LSB step.
Nominal values of GAIN and OFFSET occur when the D/A
converters outputs are at approximately half scale, +5V.
OUTPUT VOLTAGE RANGE CONNECTIONS
The DAC714 output amplifier is connected internally to
provide a 20V output range. For other ranges and configurations, see Figures 6 and 7.
DIGITAL INTERFACE
SERIAL INTERFACE
The DAC714 has a serial interface with two data buffers
which can be used for either synchronous or asynchronous
updating of multiple D/A converters. A0 is the enable control
for the input shift register. A1 is the enable for the D/A Latch.
CLK is used to strobe data into the latches enabled by A0 and
A1. A CLR function is also provided and when enabled it sets
the shift register and the D/A Latch to 0000
is midscale).
Multiple DAC714s can be connected to the same CLK and
data lines in two ways. The output of the serial shift register
is available as SDO so that any number of DAC714s can be
cascaded on the same input bit stream as shown in Figures
8 and 9. This configuration allows all D/A converters to be
updated simultaneously and requires a minimum number of
control signals. These configurations do require 16N CLK
cycles to load any given D/A converter, where N is the
number of D/A converters.
The DAC714 can also be connected in parallel as shown in
Figure 10. This configuration allows any D/A converter in
the system to be updated in a maximum of 16 CLK cycles.
(output voltage
H
SDI
CLR
A
A
0
1
DAC714
Bus
Interface
System Ground
V
REFRBPO
10kΩ
V
REF
ACOMDCOM
Alternate Ground
3
Sense Connection
To +V
CC
(1)
0.01µF
0.01µF
To –V
CC
NOTE: (1) Locate close to DAC714 package.
R
10kΩ10kΩ
Analog
Power
Supply
R
FB2
R
1
V
OUT
R
L
R
2
Sense
Output
FIGURE 5. System Ground Considerations for High-Resolution D/A Converters.
9
®
DAC714
Page 10
Internal
+10V Reference
180Ω
15kΩ
IDAC
0-2mA
8
Offset Adjust
9.75kΩ
ACOM
V
REF OUT
Gain Adjust
10kΩ
10kΩ
12
P
1
1kΩ
R
1
100Ω
14
R
2MΩ
13
V
27kΩ
OUT
R
3
10
R
FB2
9
2
+V
CC
10kΩ to 100kΩ
–V
CC
For no external adjustments, pins 13 and 14 are not
connected. External resistors R
values. Range of adjustment at least ±0.3% FSR.
- R3 are standard ±1%
1
FIGURE 6a. Manual Offset and Gain Adjust Circuits; Unipolar Mode (0V to +10V output range).
Internal
+10V Reference
180Ω 250Ω
15kΩ
IDAC
0-2mA
8
Bipolar Offset
Gain Adjust
Offset Adjust
9.75kΩ
ACOM
V
10kΩ
REF OUT
10kΩ
12
11
P
1
1kΩ
R
100Ω
P
2
1kΩ
1
R
100Ω
2
14
13
R
10
R
FB2
9
3
27kΩ
V
OUT
R
10kΩ
4
For no external adjustments, pins 13 and 14 are not
connected. External resistors R
values. Range of adjustment at least ±0.3% FSR.
- R4 are standard ±1%
1
FIGURE 6b. Manual Offset and Gain Adjust Circuits; Bipolar Mode (–5V to +5V output range).
®
DAC714
10
Page 11
Internal
+10V Reference
180Ω 250Ω
V
REF OUT
Bipolar Offset
Gain Adjust
Offset Adjust
12
11
R
200Ω
1
R
1.3kΩ
+10V
2
10kΩ
14
10kΩ
–10V
Suggested Op Amps
OPA177GP, GS or
13
5kΩ
OPA604AP, AU
15kΩ
9.75kΩ
10kΩ
10kΩ
R
FB2
10
R
3
11.8kΩ
R
4
24.3kΩ
RFBV
REF A
0 to +10V
Suggested Op Amps
OPA177GP, GS: Single or
OPA2604AP, AU: Dual
0 to +10V
RFBV
REF B
IDAC
0-2mA
±10V V
DAC714
9
OUT
For no external adjustments, pins 13 and 14 are not
connected. External resistors R
Range of adjustment at least ±0.3% FSR.
- R4 tolerance: ±1%.
1
Suggested D/As
CMOS
DAC7800: Dual: Serial Input, 12-bit Resolution
DAC7801: Dual: 8-bit Port Input, 12-bit Resolution
DAC7802: Dual: 12-bit Port Input, 12-bit Resolution
DAC7528: Dual: 8-bit Port Input, 8-bit Resolution
DAC7545: Dual: 12-bit Port Input, 12-bit Resolution
DAC8043: Single: Serial Input, 12-bit Resolution
BIPOLAR (complete)
DAC813 (Use 11-bit resolution for 0V to +10V output. No op amps required).
FIGURE 7. Gain and Offset Adjustment in the Bipolar Mode Using D/A Converters (–10V to +10V output range).
11
®
DAC714
Page 12
Data
Data Latch
Update
CLK
+5V
+5V
+5V
4
SDI
2
A0
3
A1
CLK
CLR
SDI
A0
A1
CLK
CLR
SDI
A0
A1
CLK
CLR
DAC714
DAC714
DAC714
SDO
SDO
SDO
5
5
5
To other DACs
1
16
4
2
3
1
16
4
2
3
1
16
FIGURE 8a. Cascaded Serial Bus Connection with Synchronous Update.
DAC3 DAC2 DAC1
(1)
Clock
FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210
Data
Data Latch
Update
NOTE: (1) Maximum Clock Frequency is 5.26MHz.
FIGURE 8b. Timing Diagram For Figure 8a.
®
DAC714
12
Page 13
Data
Data Latch
Update
+5V
+5V
+5V
4
SDI
2
A0
3
A1
CLK
CLR
SDI
A0
A1
CLK
CLR
SDI
A0
A1
CLK
CLR
DAC714
DAC714
DAC714
SDO
SDO
SDO
5
5
5
To other DACs
1
16
4
2
3
1
16
4
2
3
1
16
FIGURE 9a. Cascaded Serial Bus Connection with Asynchronous Update.
DAC3 DAC2 DAC1
Data
Update
(1)
FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210
Data Latch
NOTE: (1) Maximum Data Latch Frequency is 5.26MHz.
FIGURE 9b. Timing Diagram For Figure 9a.
13
®
DAC714
Page 14
Data
Data Latch 1
Update
CLK
CLR
Data Latch 2
Data Latch 3
4
SDI
2
A0
3
A1
CLK
CLR
SDI
A0
A1
CLK
CLR
SDI
A0
A1
CLK
CLR
DAC714
DAC714
DAC714
SDO
SDO
SDO
5
5
5
1
16
4
2
3
1
16
4
2
3
1
16
FIGURE 10a. Parallel Bus Connection.
DAC1 DAC2 DAC3
(1)
Clock
FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210
Data
Data Latch 1
Data Latch 2
Data Latch 3
Update
NOTE: (1) Maximum Clock Frequency is 10MHz.
FIGURE 10b. Timing Diagram For Figure 10a.
®
DAC714
14
Loading...