Page 1
D602
3V, 6GHz Divide-by-2 Static Prescaler
Final
Applications
5GHz WLAN, IEEE 802.11a and HIPERLAN
VSAT at 3.6 to 4.2 GHz
Satellite Communications at 4.5 to 4.8 GHz
5 Gbps Clock Generator
Features
Low Phase Noise, -141dBc/Hz at 1kHz offset
Single Supply Voltage, 2.7 - 4.0 V
Low Power Consumption, 42mW
Power Down Mode, 0.2µA
Compatible with common PLL synthesizer ICs
8-Pin Plastic SOIC Package
Ordering Information
Type Package Remark
D602 8-Pin SOIC Plastic
Package
Functional Block Diagram
Product Description
The D602 is a SiGe divide-by-2 low noise static
prescaler capable of operation up to 6.0 GHz. The
D602 operates over a wide range of input frequencies
and levels, and provides differential outputs for low
noise operation with the common PLL style frequency
synthesizer ICs.
The static nature of the prescaler prevents spurious
generation.
The D602 prescaler can operate from either a single
positive or single negative supply with power down
mode for low standby power consumption.
In
In
V
CC
f
In
V
EE
2÷
PWD
Out
f
Out
Out
V
EE
20-DST-01 Rev 5.0 Sept/01 1 of 8
Page 2
Pin Out Diagram
D602
3V, 6GHz Divide-by-2 Static Prescaler
Final
CC
EE
1
2
D602
3
4
V
In
In
V
PWD
8
7
Out
6
Out
V
5
EE
Pin Out Description
Pin No. Name Description
1 VCC Power Supply Voltage Input
2 In Prescaler Input (internally-biased)
3
4 VEE Ground for Input (pins 4 and 5 must be connected to the same potential)
5 VEE Ground for Output (pins 4 and 5 must be connected to the same potential)
6
7 Out Output (open-collector)
8 PWD
In
Out
Prescaler Complementary Input (internally-biased)
Complementary Output (open-collector)
Power Down high impedance CMOS input. When PWD is high, the part is powered
down.
Absolute Maximum Ratings
Operation in excess of any one of above Absolute Maximum Ratings may result in permanent damage. This device is
a high performance RF integrated and is ESD sensitive. The RF inputs on this device are Class 0 ESD rated;
therefore suitable precaution should be taken during handling, assembly and testing.
Symbol Parameter Min. Max. Unit
Supply Voltage -0.3 +4.3 V
Voltage on any pin with respect to VEE -0.3 VCC + 0.3 V
Differential input voltage -2.0 +2.0 V
Storage Temperature -65 +150 °C
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Page 3
D602
3V, 6GHz Divide-by-2 Static Prescaler
Final
Electrical Characteristics
Conditions: VCC = 3.0V, -40°C < TA < 85°C unless otherwise specified
Symbol Parameter Note Min. Typ. Max. Unit
VCC Supply Voltage 2.7 3.0 4.0 V
TA Operating Temperature 1 -40 25 85 °C
ICC Supply Current 14 18 mA
I
CC – PWDN
f
In(U)
f
In(L)
f
Osc
P
In(U)
P
In(L)
P
Out
Power-Down Supply Current
(V
PWD
= High)
0.2 1.0 µA
Upper Limit of Input Frequency 2 5.8 6.4 GHz
Lower Limit of Input Frequency 2 0.6 1.0 GHz
Self Oscillation Output Frequency 3 1.0 GHz
Upper Limit of Input Power 0 3 dBm
Lower Limit of Input Power -20 -10 dBm
Output Power 4 -15.0 0 dBm
VIH High-Level PWD Input Voltage VCC - 0.2 V
VIL Low-Level PWD Input Voltage 0.2 V
IIH High-Level PWD Input Current -100.0 100.0 nA
IIL Low-Level PWD Input Current -100.0 100.0 nA
PN
Residual Phase Noise at 1kHz offset from
a 2.5GHz (f
) carrier
Out
-141 dBc/Hz
Notes: (1) Sample Tested
(2) For a sine-wave input
(3) Since the input signal is AC coupled, in the absence of an RF input, the prescaler may self oscillate and
provide an output at this frequency. Self oscillation can be eliminated by powering down the prescaler,
or applying a differential DC input voltage (a 47kΩ resistor placed between pin 3 and V
CC
).
(4) This power is delivered to a 50Ω load. It excludes the power dissipated in the external pull-up resistors.
Test Circuit
V
Signal
Generator
100p
100n
1n
1p
1
2
3
4
D602
CC
8
7
6
5
51
100p
100n
51
1n
1n
50 Ohm
Measurement
Equipment
20-DST-01 Rev 5.0 Sept/01 3 of 8
Page 4
Typical Performance Characteristics
17
16
15
14
13
12
11
10
Supply Current [mA]
9
8
10
0
-10
-20
-30
Input Power [dBm]
-40
0.0
Output Power [dBm]
Supply Current vs Supply Voltage
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
Supply Voltage [V]
Input Power Limits vs Input Frequency
PIn(U)
P
(L)
In
1.0 2.0 3.0 4.0 5.0 6.0 7.0
Input Frequency [GHz]
Output Power vs I nput Frequency
0
-5
-10
-15
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
Input Frequency [GHz]
D602
3V, 6GHz Divide-by-2 Static Prescaler
Final
Upper Limit of Input Frequency vs Supply Voltage
6.9
6.7
6.5
6.3
6.1
5.9
Input Frequency [GHz]
5.7
5.5
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
-2
-3
-4
-5
-6
-7
-8
-9
Output Power [dBm,]
-10
-11
-12
2.2
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
Upper Limit of Input Frequency vs Temperature
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6
Input Frequency [GHz]
5.9
5.8
5.7
-40 -20
P
= – 10dBm
In
Supply Voltage [V]
Output Power vs Supply Voltage
f
= 5.0 GHz
In
Supply Voltage [V]
2.7V
0 20 40 60 80
Temperature [°C]
3.0V
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Page 5
D602
3V, 6GHz Divide-by-2 Static Prescaler
Final
Minimum Required Supply Voltage vs Temperature
2.2
2.15
2.1
Supply Voltage [V]
2.05
2
-40 -20 0 20 40 60 80
(fIn = 5.0 GHz)
Temperature [°C]
-3
-3.5
-4
-4.5
-5
-5.5
Output Power [dBm]
-6
-6.5
-7
-40
14
13.9
13.8
13.7
13.6
13.5
Supply Current [mA]
13.4
13.3
-40 -20 0 20 40 60 80
Supply Current vs Temperature
Temperature [°C]
Output Power vs Temperature
(fIn = 5.0 GHz)
-20 0 20 40 60 80
Temperature [°C]
Residual Phase Noise
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Page 6
Typical Application Information
D602
3V, 6GHz Divide-by-2 Static Prescaler
Final
+3V
VCO
RF
*
47k
10p
10p
1n
1
2
3
4
D602
50
50
8
7
6
5
10p
10p
PLL
Frequency
Synthesizer
Ref.
* The 47kΩ resistor provides a DC offset that disables self oscillation in the absence of an RF input.
Cascading D602 Prescalers
D602 prescalers can be cascaded to achieve division ratios other than 2. For example two D602 prescalers can be
used as shown in the following diagram to perform frequency division by 4.
+3V
PWD
50
1
In
10p
1n
2
D602
3
10p
4
8
7
6
5
50
1n
10p
10p
1
2
D602
3
4
50
50
8
7
10p
Out
6
5
10p
20-DST-01 Rev 5.0 Sept/01 6 of 8
Page 7
Package Information
Package dimensions in millimeters (inches)
8-Lead Plastic SOIC
SiGe
D602
D602
3V, 6GHz Divide-by-2 Static Prescaler
Final
XXXXXXX
Packing Details
Note : Refer to JEDEC MS-012 for additional information
20-DST-01 Rev 5.0 Sept/01 7 of 8
Page 8
D602
3V, 6GHz Divide-by-2 Static Prescaler
Final
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Product Preview
The datasheet contains information from the product concept specification. SiGe Semiconductor Inc. reserves the right to change
information at any time without notification.
Preliminary Information
The datasheet contains information from the design target specification. SiGe Semiconductor Inc. reserves the right to change
information at any time without notification.
Final
The datasheet contains information from the final product specification. SiGe Semiconductor Inc. reserves the right to change
information at any time without notification. Production testing may not include testing of all parameters.
Information furnished is believed to be accurate and reliable and is provided on an “as is” basis. SiGe Semiconductor Inc. assumes
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patent or other intellectual property rights of SiGe Semiconductor Inc. or third parties. Specifications mentioned in this publication
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20-DST-01 Rev 5.0 Sept/01 8 of 8
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