Page 1
Figure 2. Simplified Block Diagram of CY2309
VCO
REF
CLKA1
CLKA2
CLKA3
CLKA4
CLKOUT
Loop
Filter
Phase
Detector
PLL
MUX
Select Input
Decoding
S2
S1
CLKB1
CLKB2
CLKB3
CLKB4
CY2305 and CY2309 as PCI and SDRAM Buffers
Introduction to Cypress Zero Delay Buffers
What is a Zero Delay Buffer?
A zero delay buffer is a device that can fan out 1 clock signal
into multiple clock signals with zero delay and very low skew
between the outputs. This de vice is well suited as a buffer for
PCI or SDRAM due to its zero input to out put delay and very
low output to output skew.
A simplified diag ram of the CY2308 zero dela y buff er is shown
in Figure 1. The CY2308 is built using a PLL that uses a ref-
erence input and a feedback input. The feedback loop is
closed by driving the feedback input (FBK) from one of the
outputs. The phase detector in the PLL adjusts the output
frequency of the VCO so that the two inputs have no phase
difference. Since an output is one of the inputs to the PLL,
zero phase difference is maintained from REF to the output
driving FBK. Now if all outputs are uniformly loaded, zero
phase difference will be maintained from REF to all outputs.
This is a simple zero delay buffer. Introducing additional devices (e.g., dividers) between the output and FBK can give
rise to some innovative applications for the PLL, and for further information on these refer to the Cypress Application
Note “CY2308 Zero Delay Buffer”. Since many buffering ap-
plications require only a simple closure of the feedback loop,
Cypress has designed zero delay buffers with Internal Feedback Loops: the CY2305 and CY2309.
What are the CY2305 and CY2309?
Cypress ha s desi gned zer o de la y b u ff ers espec iall y sui ted f or
use with PCI or SDRAM buffering. The CY2305 an d CY2309
have been designed with the feedback path integrated for
simpler system design. A simplified block diagram of the
CY2309 zero delay buffer is shown Figure 2. This zero delay
buffer uses a input/output pad on CLKOUT so that the feedback signal can be sensed directly from the out put itself .
Drive Capability
The CY2305 and CY2309 have high drive outputs designed
to meet the JEDEC SDRAM specifications of 30 pF capacitance on each DIMM clock input.
Since the typical CMOS input is 7 pF and the CY2305/09 are
designed to dri ve up to 30 pF; this means that up to 4 CMOS
inputs can be driven from a single output of a CY2305/09.
Howev er t he ou tput loadi ng o n the CY2305/ 09 mu st be equal
on all outputs to maintain zero dela y from the input.
Power Down
The CY2305 and CY2309 ha ve a unique po wer-down mode:
if the input r ef ere nce is stoppe d, the part au tomati call y en ters
a shutdown state , shutting down t he PLL and three-st ating the
outputs. When the part is in shut down mode it dr aws less t han
50 µA, and can come out of shutdown mode with the PLL
locked in less than 1 m s. This power down mode c an also be
entered by three-stating the input reference driver and al lowing the internal pull-down to pull the input LOW (the input
does not have to go LOW, it only has to stop).
5 Volt to 3.3 Volt Level Shifting
The CY2305 and CY2309 can ac t as a 5-volt to 3.3-volt level
shifter. The reference input pad is 5-volt signal-compatible.
Since many system components still operate at 5 volts, this
feature provides the capability to generate multiple 3.3-volt
clocks from a single 5-volt reference clock. This 5-volt signal-compatibility is only available on the reference pad; the
other input pads on the CY2309 are not 5-volt compati ble.
REF
Phase
Detector
Loop
Filter
VCO
PLL
Select Input
Decoding
S2
S1
Figure 1. Simplified Block Diagram of CY2308
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
MUX
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
March 25, 1997 – Revised July 29, 1997
Page 2
CY2305 and CY2309 as PCI and SDRAM Buffers
Lead or Lag Adjustments
To adjust the lead or lag of the outputs on the CY2305 or
CY2309, one must understand the relationships between
REF and CLKOUT, and the relationship between CLKOUT
and the other output s . To understa nd the r elat ionshi p , f irst w e
need to understand a few properties of the CY2305 and
CY2309 Phase Loc ked Loops. The PLL senses the pha se of
the CLKOUT pin at a threshold of V
the REF pin at the same V
/2 threshol d. All the ou tputs s tart
dd
/2 and compares it to
dd
their trans iti on at the same t ime (incl uding CLKOUT). Changing the load on an output changes its rise time and theref ore
how long it takes the output to get to the V
/2 threshold.
dd
Using these properties to our advantage, we can then adjust
the time when the outputs reach the V
to when the REF in put reaches the V
/2 threshold relative
dd
/2 threshold. T he CLK-
dd
OUT output however cannot be adjusted: it will always have
zero delay from the REF input at V
/2. The outputs can be
dd
advanced by loading the CLKOUT out put more heavily than
the other out puts or can be dela yed b y loadi ng CLKO UT more
lightly than the other outputs. Figure 3 shows how many ps
the outputs are moved vs. the difference in the loading between CLKOUT and the other outputs. As a rough guideline,
the adjustment is 50 ps/pF of loading difference. Note: the
zero delay buffer will always adjust itself to keep the V
point of the output at zero delay from the V
reference. If the application requires the outputs of the zero
/2 point of the
dd
dd
delay buffer to have zero delay from another output of the
referenc e clock chip , the output of the cloc k chip t hat is drivi ng
the zero delay buffer must be loaded the same as the other
outputs of t he cloc k chip or the output s of the zero delay buf fer
will be advanced/delayed with reference to those other outputs.
/2
Figure 3. Lead Lag Adjus tments
2
Page 3
CY2305 and CY2309 as PCI and SDRAM Buffers
Output To Output Skew
The skew between CLKOUT and the other outputs is not dynamically adjusted by the loop. All MUST have the same load
on them to achieve zero output to output skew. If the other
outputs are less loaded than CLKOUT, they will lead i t; and if
the other outputs are mor e loaded, they will lag the CLKOUT.
The relationshi p that exi sts between the CLK OUT and the rest
Zero Delay Buffer Timing diagrams with different loading configurations.
REF input and all
outputs loaded equally
REF
CLKOUT
of the outputs is tha t the y all s tart the rising edge at the same
time, but different loads will cause them to have different rise
times and different times crossing the measurement thresholds. Since CLK OUT i s the only output th at is monitor ed, it will
be the output that has the zero dela y fr om the reference and
the other clocks will be relative to CLKOUT and their loading
differences.
CLKA1
CLKA4
CLKB1
CLKB4
REF input and CLKA1-CLKB4 loaded
equally, with CLKOUT loaded more
REF
CLKOUT
CLKA1
CLKA4
CLKB1
CLKB4
Zero Delay
REF input and CLKA1-CLKB4 loaded
equally, with CLKOUT loaded less
REF
CLKOUT
CLKA1
CLKA4
CLKB1
CLKB4
Advanced
Delayed
3
Page 4
CY2305 and CY2309 as PCI and SDRAM Buffers
VCO
EF
CLKA1
CLKA2
CLKA3
CLKA4
CLKOUT
LP
Filter
Phase
Detector
PLL
MUX
Select Input
Decoding
S2
S1
CLKB1
CLKB2
CLKB3
CLKB4
1
2
3
4
13
16
15
14
REF
CLKA1
CLKA2
V
DD
CLKA3
CLKOUT
CLKA4
V
DD
SOIC
Top View
5
6
7
8
GND
CLKB1
CLKB2
S2
9
12
11
10
CLKB3
GND
CLKB4
S1
Product Inf ormat ion
The CY2305 Zero Delay Buffer
The CY2305 is a 3.3-volt, five output zero delay buffer in an
8-pin 150-mil S OIC package. This part is intend ed for buffering one clock into five clocks for PCI buffering or four clocks
for use with 1 SDRAM module. The CY2305 is the simplest
and easiest to use pa rt in the Cypr ess zer o dela y bu ff er f amily.
For a discussion of the special features of the CY2305 see
the special features section of this application note, or for the
complete specifications on the CY2305 please refer to the
CY2305/CY2309 data sheet.
PLL
LP
Filter
VCO
CLKOUT
CLK1
CLK2
CLK3
CLK4
REF
Phase
Detector
SOIC
Top View
REF
CLK2
CLK1
GND
1
2
3
45
8
7
6
CLKOUT
CLK4
V
DD
CLK3
The CY2309 Zero Delay Buffer
The CY2309 is a 3.3-volt, nine output zero delay buffer in a
16-pin 150-mil SOIC package. This part is intended for buffering one clock into 9 clocks for PCI buffering or eight clocks
for use with 2 SDRAM modules. For the complete specifications please refer to the CY2305/CY2309 data sheet.
The CY2309 has se v er al opt ions for shutt ing do wn t he outpu t
banks or completel y shutt ing down the part to conserve po wer. As shown in the table below, the inputs S1 and S2 control
which output banks are driven and the state of the PLL. You
will notice that the CLKOUT output is always driven. This is
because the PL L m ust h av e the CLKOUT pin running in orde r
to maintain phase loc k. The CY2309 wi ll also go i nto a powe r
down state if the input reference stops as described in the
“Special Feat ures of the Cypress Zero Del ay Buff ers” section.
Select Input Decoding for CY2309
S2 S1 CLOCK A1–A4 CLOCK B1–B4 CLKOUT
0 0 Three-State Three-State Driven PLL N
[1]
Output Source PLL Shutdown
0 1 Driven Three-State Driven PLL N
4
1 0 Driven Driven Driven Reference Y
1 1 Driven Driven Driven PLL N
Note:
1. This output is driven and has an internal feedback for the PLL. The load on this output c an be adjusted to change the de lay between the
reference and the CLKA/CLKB outputs.
Page 5
CY2305 and CY2309 as PCI and SDRAM Buffers
Applications
5 and 9 PCI Device/Slot Zero Delay Buffer Soluti on
The CY2305 and CY2309 are an excellent clocking solution
for a system that requires more PCI cl ocks than the currently
popular clock chips provide. The CY2305 comes in a tiny
150-mil 8-pin SOIC package and the CY2309 comes in a
small 150-mil 16-pin SOIC package. The CY2305 and
CY2309 are priced v ery aggressively for the high volume PC
market. There are two solutions for implementing a PCI zero
delay buffer with the Cypress zero delay buffers: a 5 device/slot and a 9 device/slot buffer.
The 5 Device/Slot Solution:
• PCI/Slot 1 (CLKOUT) must always be loaded.
• If PCI Slots represe nt diffe rent loads , they will ha ve earlie r
or later clocks (See Lead or Lag Adjustments section of
“Special Features of Cypress Zero Delay Buffers”.
PCICLK
The 9 Device/Slot Solution:
• PCI/Slot 1 (CLKOUT) must always be loaded.
• Select lines can be used to shut down output banks , see
CY2309 data sheet.
REF
CY2305
Zero Delay
Buffer
CLKOUT
CLK1
CLK2
CLK3
CLK4
PCI Device 1
4 PCI Devices /Slots
1 SDRAM DIMM Zero Delay Buffer Solution
The CY2305 is an excellent clocking solution for a system
using 1 SDRAM DIMM. The CY2305 comes in a very small
150-mil 8-pin SOIC package and is priced very aggressively
for the high volume PC market. There are two solutions for
implementing 1 SDRAM DIMM support with the CY2305: the
first is the ad justab le dela y soluti on, and the s econd is the s elf
adju sting delay solution.
The Adjustabl e Delay Solution:
• C
must be equal to SDRAM module loading for zero
load
delay.
• T o m ake the SDRAM inputs le ad or lag the r ef erence input
see the Lead or Lag Adjustments section of “Special Features of the Cypress Zero Del ay Buff ers”.
CPUCLK
CLKOUTREF
C
load
CY2305
Zero Delay
Buffer
CLK1
CLK2
CLK3
CLK4
SDRAM Module
The Self Adjusting Solution:
• This solution will automatically compen sate for different
SDRAM input loads.
• CLKOUT must drive CK0 on the SDRAM module so that
CLKOUT is always fully loaded (pin 42 on the SDRAM
module).
PCICLK
REF
CY2309
Zero Delay
V
dd
Buffer
S1
S2
CLKOUT PCI Device 1
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
4 PCI Devices/Slots
4 PCI Devices/Slots
CPUCLK
REF CLKOUT
CY2305
Zero Delay
Buffer
CLK1
CLK2
CLK3
CLK4
SDRAM Module
5
Page 6
CY2305 and CY2309 as PCI and SDRAM Buffers
2 SDRAM DIMM Zero Delay Buffer Solution
The CY2309 is an excellent clocking solution for a system
using 2 SDRAM DIMMs. The CY2309 comes in a small
150-mil 16-pin SOIC pac kage and is priced very aggress iv ely
for the high volume PC market. There are two solutions for
implementing 2 SDRAM DIMMs support with the CY2309:
the firs t is the a djust ab le del a y s olu tion, an d t he second i s the
self adjust ing delay solution.
CPUCLK
CY2309
Zero Delay
Buffer
S1
S2
CLKOUTREF
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Decoding
Logic
The Adjustabl e Delay Solution:
• C
must be equal to SDRAM module loading for zero
load
delay.
• T o m ake the SDRAM inputs le ad or lag the r ef erence input
see the Lead or Lag Adjustments section of “Special Features of the Cypress Zero Del ay Buff ers”.
• Clocks are three-stated when that SDRAM module is not
present.
• If only 1 SDRAM module is installed it must be module 1.
C
load
SDRAM Module 1
Module Sense
SDRAM Module 2
Module Sense
The Self Adjusting Solution:
• This solution wil l automatically compensate for dif ferent
SDRAM input loads (only on module 1).
• CLK OUT must driv e CK0 on the SDRAM module 1 so t hat
CLKOUT is always fu lly loaded (pin 42 on the SDRAM
module).
CPUCLK
REF
CY2309
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
Zero Delay
Buffer
S1
S2
CLKB1
CLKB2
CLKB3
CLKB4
Decoding
Logic
• If only one SDRAM module i s installed it mus t be module 1.
• CLKA and CLKB clocks are three-stated when their re-
spective SDRAM module is not pres ent, b ut CLK OUT will
continue to run.
SDRAM Module 1
Module Sense
SDRAM Module 2
Module Sense
6
Page 7
CY2305 and CY2309 as PCI and SDRAM Buffers
3 SDRAM DIMM Zero Delay Buffer Solution
The CY2305 and CY2309 are ex cel lent cloc k ing solu tions f or
a system using 3 SDRAM DIMMs. The CY2305 comes in a
small 150-mil 8-p in SOIC packa ge and t he CY2309 com es in
a small 150-mil 16-pin SOIC. Both buffers are priced very
aggressively for the high volume PC market. There are two
solutions f or implemen ting 3 SDRAM DIMMs support with th e
CY2305 and CY2309: the fir st is the adjustab le delay so lution,
and the second is the self adjusting delay solution.
CPUCLK
CLKOUTREF
CY2305
Zero Delay
Buffer
CLK4
CLK3
CLK2
CLK1
CLKOUTREF
The Adjustabl e Delay Solution:
• C
and C
load1
for zero delay.
must be equal to SDRAM modul e loading
load2
• T o m ake the SDRAM inputs le ad or lag the r ef erence input
see the Lead or Lag Adjustments section of “Special Features of the Cypress Zero Del ay Buff ers”.
• SDRAM modules must be instal led in order (module 1 f irst
and module 3 last).
• Module 2 and 3 clocks are three-stated when those
SDRAM modules are not present, but CLKOUT will
continue to run.
• Module 1 clocks ca n onl y be three- state d b y three- stati ng
CPUCLK which will also three-state modules 2 and 3.
C
load1
SDRAM Module 1
C
load2
Decoding
Logic
CY2309
Zero Delay
Buffer
S1
S2
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
SDRAM Module 2
Module Sense
SDRAM Module 3
Module Sense
7
Page 8
CY2305 and CY2309 as PCI and SDRAM Buffers
The Self Adjusting Solution:
• This solution wil l automatically compensate for dif ferent
SDRAM input loads (only on Module 1 and Module 2).
• CLKOUT must drive CK0 on the SDRAM module 1 and
module 2 so that CLKOUT is always fully loaded (pin 42
on the SDRAM module).
CPUCLK
CLKOUTREF
CY2305
Zero Delay
Buffer
CLKOUTREF
CY2309
Zero Delay
Buffer
S1
S2
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Decoding
Logic
CLK1
CLK2
CLK3
CLK4
• SDRAM modules must be instal led in order (module 1 f irst
and module 3 last).
• Module 2 and 3 clocks are three-stated when those
SDRAM modules are not present, but CLKOUT will continue to run.
• Module 1 clocks ca n onl y be three- state d b y three- stati ng
CPUCLK which will also three-state modules 2 and 3.
SDRAM Module 1
SDRAM Module 2
Module Sense
SDRAM Module 3
Module Sense
8
Page 9
CY2305 and CY2309 as PCI and SDRAM Buffers
4 SDRAM DIMM Zero Delay Buffer Solution
Two CY2309s are an excellent cloc king solution for a system
using 4 SDRAM DIMMs. The CY2309 comes in a small
150-mil 16-pin SOIC pac kage and is priced very aggress iv ely
for the high volume PC market. There are two solutions for
implementing 4 SDRAM DIMMs support with the CY2309:
the firs t is the a djust ab le del a y s olu tion, an d t he second i s the
self adjust ing delay solution.
CPUCLK
REF
CY2309
Zero Delay
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
Buffer
S1
S2
CLKB1
CLKB2
CLKB3
CLKB4
Decoding
Logic
CLKOUTREF
The Adjustabl e Delay Solution:
• C
and C
load1
for zero delay.
must be equal to SDRAM modul e loading
load2
• T o m ake the SDRAM inputs le ad or lag the r ef erence input
see the Lead or Lag Adjustments section of “Special Features of the Cypress Zero Del ay Buff ers”.
• Clocks are three-s tated when that SDRAM module i s not
present.
• SDRAM modules must be instal led in order (module 1 f irst
and module 4 last).
C
load1
SDRAM Module 1
Module Sense
SDRAM Module 2
Module Sense
C
load2
Decoding
Logic
CY2309
Zero Delay
Buffer
S1
S2
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
SDRAM Module 3
Module Sense
SDRAM Module 4
Module Sense
9
Page 10
CY2305 and CY2309 as PCI and SDRAM Buffers
The Self Adjusting Solution:
• This solution wil l automatically compensate for dif ferent
SDRAM input loads (only on Module 1 and Module 3).
• CLKOUT must drive CK0 on the SDRAM module 1 and
module 3 so that CLKOUT is always fully loaded (pin 42
on the SDRAM module).
CPUCLK
REF
CY2309
Zero Delay
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
Buffer
S1
S2
CLKB1
CLKB2
CLKB3
CLKB4
Decoding
Logic
CLKOUTREF
CY2309
Zero Delay
Buffer
S1
S2
Decoding
Logic
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
• SDRAM modules must be instal led in order (module 1 f irst
and module 4 last).
• Clocks are three-stated when that SDRAM module is not
present, but CLKOUT will continue to run.
SDRAM Module 1
Module Sense
SDRAM Module 2
Module Sense
SDRAM Module 3
Module Sense
SDRAM Module 4
Module Sense
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it conv ey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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