Datasheet CY22392ZI-xxx, CY22392ZC-xxx, CY22392FI, CY22392FC Datasheet (Cypress Semiconductor)

5

CY22392

Three-PLL General Purpose

FLASH Programmable Clock Generator

Features Benefits

Three integrated phase-locked loops Generates up to 3 unique frequencies on 6 outputs up to

200 MHz from an external source. Functional upgrade for cur­rent CY2292 family.

Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit
Post Divide)

Improved Linear Crystal Load Capacitors Improves frequency accuracy over temperature, age, process,

Flash programmability Non-Volatile programming enables easy customization,

Field programmable In-house programming of samples and prototype quantities is

Low-jitter, high-accuracy outputs Performance suit able for high -end multimed ia, communicat ions,

Power-management options (Shutdown, OE, Suspend) Supports nume rous l ow- po wer a ppl ic ati on schemes and redu c-

Configurable Crystal Drive Strength Adjust Crystal Drive Strength for compatibility with virtually all

Frequency Select via 3 External LVTTL Inputs 3-Bit External Frequency Select Options for PLL1, CLKA, and

3.3V operation Industry-standard supply voltage.
16-pin TSSOP Packages Industry-standard packaging saves on board space.
CyClocksRT™ Support Easy to use software support for design entry.

Allows for 0 ppm Frequency Generati on and Frequ ency Conver­sion under the most demanding applications.

and initial offset.

ultra-fast turnaround, performance tweaking, design timing mar­gin testing, inventory control, lower part count, and more secure
product supply. In addition, any part in the family can also be
programmed multiple times which reduces programming errors
and provides an easy upgrade path for existing designs.

available using the CY3672 FTG Development Kit. Production

quantities are avail able through Cypress Semic onductor’s value
added Distributio n p artners or by usi ng thi rd p ar ty prog ramme rs
from BP Microsystems, HiLo Systems, and others.

industrial, A/D Converters, and consumer applications.

es EMI by allowing unused outputs to be turned off.

crystals.

CLKB.

Logic Block Diagram

XTALIN

XTALOUT

CONFIGURATION

SHUTDOWN

S2/SUSPEND

CYClocks RT is a trademark of Cypress Semiconductor Corporation

/OE
S0
S1

OSC.

FLASH

PLL1

11 BIT P

8 BIT Q

PLL2

11 BIT P

8 BIT Q

PLL3

11 BIT P

8 BIT Q

4x4

Crosspoint

Switch

Divider
/2,3, or 4

Divider

7 BIT

Divider

7 BIT

Divider

7 BIT

Divider

7 BIT

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07013 Rev. *C Revised December 14, 2002

XBUF

CLKE

CLKD

CLKC

CLKB

CLKA

CY22392

Pin Configuration

CY22392

16-pin TSSOP

CLKC

V

DD

AGND
XTALIN

XTALOUT

XBUF
CLKD
CLKE

1
2
3
4
5
6
7
8

16
15
14
13
12

11
10

9

SHUTDOWN

S2/SUSPEND

AV

DD

S1
S0
GND

CLKA
CLKB

/OE

Selector Guide

Part Number Outputs Input Frequency Range Output Frequency Range Specifics

CY22392FC 6 8 MHz–30 MHz (external crystal)

1 MHz–166 MHz (reference clock)

CY22392FI 6 8 MHz–30 MHz (external crystal)

1 MHz–150 MHz (reference clock)

Up to 200 MHz Commercial Temperature

Up to 166 MHz Industrial Temperature

Pin Summary

Name Pin Number Description

CLKC 1 Configurable clock output C
V

DD

AGND 3 Analog Ground
XTALIN 4 Reference crystal input or external reference clock input
XTALOUT 5 Reference crystal feedback
XBUF 6 Buffered reference clock output
CLKD 7 Configurable clock output D
CLKE 8 Configurable clock output E
CLKB 9 Configurable clock output B
CLKA 10 Configurable clock output A
GND 11 Ground
S0 12 General Purpose Input for Frequency Control; bit 0
S1 13 General Purpose Input for Frequency Control; bit 1
AV

DD

S2/
SUSPEND

SHUTDOWN/OE 16 Places outputs in thr ee-s tat e condit ion and sh ut s down ch ip whe n LOW. Optionally ,

2 Power supply

14 Analog Power Supply
15 General Purpose Input for Fre quency Control; bit 2. Optionally Suspe nd mode control

input.

only places outputs in tristate condition and does not shut down chip when LOW

Document #: 38-07013 Rev. *C Page 2 of 9

CY22392

Operation

The CY22392 is an upgrade to the exis ting CY 2292. The new
device has a wider frequency range, greater flexibility, im­proved performance, and incorporates many features that re­duce PLL sensitivity to external system issues.

The device has three PLLs which, when combined with the
reference, allow up to fou r inde penden t frequ encies t o b e out­put on up to six pi ns. These th ree PLLs are c ompletely pr o­grammable.

Configurable PLLs

PLL1 generates a frequency that is equal to the reference di­vided by an 8-bi t div ider (Q) and m ultipl ied b y an 11-bit divider
in the PLL feedback loop (P). The outp ut of PLL1 is sent to the
crosspoint switch. The output of PLL1 is also sent to a /2, /3,
or /4 synchronous post-divider that is output through CLKE.
The frequency of PLL1 can be changed by external CMOS
inputs, S0, S1, S2. See the following section on General-Pur­pose Inputs for more details.

PLL2 generates a frequency that is equal to the reference di­vided by an 8-bi t div ider (Q) and m ultipl ied b y an 11-bit divider
in the PLL feedback loop (P). The outp ut of PLL2 is sent to the
crosspoint switch.

PLL3 generates a frequency that is equal to the reference di­vided by an 8-bi t div ider (Q) and m ultipl ied b y an 11-bit divider
in the PLL feedback loop (P). The outp ut of PLL3 is sent to the
cross-point switch.

General-Purpose Inputs

S0, S1, and S2 are general-purpose inputs that can be pro­grammed to allow for eight different frequency settings. Op­tions that may be switched with these general purpose inputs
are as follows; the frequency of PLL1, the output divider of
CLKB, and the output divider of CLKA.

CLKA and CLKB both have 7-bit dividers that point to one of
two programmable settings (register 0 and register 1). Both
clocks share a single register control, so both must be set to
register 0, or both must be set to register 1.

For example: the p art may be programm ed to use S0 , S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting , one of the two CLKA
and CLKB divider regis ters can be chosen. A ny divider change
as a result of switching S0, S1, or S2 is guara nteed to be glitch
free.

Crystal Input

The input crystal osci llator is an important feature of thi s device
because of its flexibility and performance features.

The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.

The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate ca­pacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that oc curs when non-linear load
capacitan ce in teract s wit h load , bias , supp ly, and temperature
changes. Non-linea r (FET gate) cryst al load cap acitors should
not be used f or MPEG, POTS dial tone, Comm unicati ons, or
other applications that are sensitive to absolute frequency re­quirements.

The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with
a resolution of 0.375 pF for a total crystal load range of 6 pF
to 30 pF.

For driven clock inpu ts the input load capacitors may be com ­pletely bypassed . This enabl es the clock chip to acce pt driven
frequency inputs up to 166 MHz. If the application requires a
driven input, then XTALOUT must be left floating.

Output Configuration

Under normal operation there are four internal frequency
sources that may be routed via a programmable crosspoint
switch to any of the four programmable 7-bit output dividers.
The four sources are: reference, PLL1, PLL2, and PLL3. In
addition, many outputs have a unique capability for even
greater flexibilit y . The foll owing is a desc ription of each output.

CLKA’s output originates from the crossp oin t s witc h a nd g oes
through a programmable 7-bit post divider. The 7-bit post di­vider derives its value from one of two programmable regis­ters. Each of the eight possible combinations of S0, S1, S2
controls which of the two programmable registers is loaded
into CLKA’s 7-bit post divider. See the section “General-Pur-
pose Inputs” for more information.

CLKB’s output origi nates from the c rossp oin t swit ch and goes
through a programmable 7-bit post divider. The 7-bit post di­vider derives its value from one of two programmable regis­ters. Each of the eight possible combinations of S0, S1, and
S2 controls whic h of the two programmab le registers i s loaded
into CLKA’s 7-bit post divider. See the section “General-Pur-
pose” Inputs for more information.

CLKC’s output or iginat es from the cross point swit ch an d goe s
through a programmable 7-bit post divider. The 7-bit post di­vider derives its value from one programmable register.

CLKD’s output or iginat es from the cross point swit ch an d goe s
through a programmable 7-bit post divider. The 7-bit post di­vider derives its value from one programmable register.

CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4.

XBUF is simply the buffered r efere nc e.
The Clock outputs have been designed to drive a single point

load with a total lumpe d load cap acita nce of 15pF. While driv­ing multiple loads is possible with the proper termination it is
generally not recommended.

Power Saving Features

The SHUTDOWN
pulled LOW . If sy stem shut down is enabl ed, a LOW on t his pin
also shuts of f the PLLs, count ers, the referenc e oscilla tor , an d
all other active components. The resulting current on the V
pins will be less than 5 µA (typical). After leaving shutdown
mode, the PLLs will have to relock.

The S2/SUSPEND
customizable se t of outp uts a nd/or PLLs , when L OW . Al l PLLs
and any of the outputs can be shut off in nearly any combina­tion. The only limitation is that if a PLL is shut off, all outputs
derived from it mus t a ls o b e s hut off. Suspending a PLL shuts
off all associated logic, while suspending an output simply
forces a three-state condition.

/OE input three-states the outputs when

DD

input can be configured to shut down a

Document #: 38-07013 Rev. *C Page 3 of 9

CY22392

Improving Jitter

Jitter Optimization Control is useful in mitigating problems re­lated to simila r cloc ks s witchin g at th e sam e mom ent, c ausin g
excess jitter. If one PLL is driving more than one output, the
negative phase of the PLL can be selected for one of the out­puts (CLKA–CLKD). This prevents the output edges from
aligning, allowing superior jitter performance.

Power Supply Sequencing

For parts with multiple V
sequencing requ irements. Th e part w ill not be f ully operati onal
until all V
fied in the “Operating C onditions” table.

pins have been brought up to the voltages speci-

DD

pins, there are no power supply

DD

All grounds should be connected to the same ground plane.

CyClocks RT™ Software

CyClocks RT i s ou r s ec ond -gen era tion application that allows
users to configure this device. The easy-to-use in terface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations ar e
checked and performance tuning is automatically applied.
CyClocks RT also has a power estimation feature that allows
you to see the power consumption of your specific configura­tion. You can download a copy of CyClocks RT for free on
Cypress’s web site at www.cypress.com.

Operating Conditions

[1]

Junction Temperature Limitations

It is possible to progra m the CY2239 2 suc h tha t the maxim um
Junction Temperature rating is exceeded. The package θ
115 C/W. Use the CyClocks RT power estimation feature to
verify that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum rat­ings.

JA

is

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Supply Voltage ...............................................–0.5V to +7.0V

DC Input Voltage............................–0.5V to + (AV

Storage Temperature ................................. –65°C to +125°C

Junction Temperature...................................................125°C

Data Retention @ Tj = 125°C.................................>10 years

Maximum Programming Cycles .......................................100

Package Power Dissipation......................................350 mW

Static Discharge Voltage

(per MIL-STD-883, Method 3015)..........................................

2000V

Latch up (per JEDEC 17).................................... >

+ 0.5V)

DD

±200 mA

Parameter Description Min. Typ. Max. Unit

VDD/AV
T

A

DD

Supply Voltage 3.135 3.3 3.465 V
Commercial Operating Temperature, Ambient 0 +70 °C
Industrial Operating Temperature, Ambien t –40 +85 °C

C

LOAD_OUT

f

REF

Max. Load Capacitance 15 pF
External Reference Crystal 8 30 MHz
External Reference Clock
External Reference Clock

[2]

, Commercial 1 166 MHz

[2]

, Industrial 1 150 MHz

Power-up time for all VDD's to reac h m in im um spe cif ie d vo lt a ge

t

PU

Notes:

1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.

2. External input reference clock must have a duty cycle between 40% and 60%, measured at V

(power ramps must be monotonic) 0.05 500 ms

/2.

DD

Document #: 38-07013 Rev. *C Page 4 of 9

CY22392

Electrical Characteristics

Parameter Description Conditions Min. Typ. Max. Unit

[3]

[3]

VOH=VDD– 0.5, VDD=3.3V 12 24 mA
VOL= 0.5V, VDD=3.3V 12 24 mA

[3]

Capload at minimum setting 6 pF

[3]

Capload at maximum setting 30 pF

[3]

Except crystal pins 7 pF

DD
DD

70% AV

30% AV

100 mA

166 MHz; 4 outputs @ 83 MHz

3.3V Power Supply; 2 outputs @

50 mA

20 MHz; 4 outputs @ 40 MHz
Shutdown active 5 20 µA

I

OH

I

OL

C

XTAL_MIN

C

XTAL_MAX

C

LOAD_IN

V

IH

V

IL

I

IH

I

IL

I

OZ

I

DD

I

DDS

Output Hi gh Current
Output Low Current
Crystal Load Capacitance
Crystal Load Capacitance
Input Pin Capacitance
HIGH-Level Input Voltage CMOS levels,% of AV
LOW-Level Input Voltage CMOS levels,% of AV
Input HIGH Current VIN=AVDD– 0.3 V <1 10 µA
Input LOW Current VIN=+0.3V <1 10 µA
Output Leakage Curr ent Three-state outputs 10 µA
Total Power Supply Current 3.3V Power Supply; 2 outputs @

Total Power Supply Current
in Shutdown Mode

DD
DD

Switching Characteristics

Parameter Name Description Min. Typ. Max. Unit

[3, 6]

[3, 4]

Clock output limit, Commercial 200 MHz
Clock output limit, Industrial 166 MHz

[3, 5]

Duty cycle for outputs, defined as t2÷ t1,

45% 50% 55%

Fout < 100 MHz, divider >= 2, measured at

/2

V

DD

Duty cycle for outputs, defined as t
Fout > 100 MHz or divider = 1, measured at

/2

V

DD

Output clock rise time, 20% to 80% of V

Output clock fall time, 20% to 80% of V

2

÷ t1,

DD

DD

Time for out put to enter or leave three-stat e mode

40% 50% 60%

0.75 1.4 V/ns

0.75 1.4 V/ns

150 300 ns

after SHUTDOWN/OE switches
Peak-to-peak period jitter, CLK outputs mea-

sured at V

DD

/2

400 ps

PLL Lock Time from Power-up 1.0 3 ms

1/t

1

t

2

t

3

t

4

t

5

t

6

t

7

Notes:

3. Guaranteed by design, not 100% tested.

4. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.

5. Reference Output duty cycle depends on XTALIN duty cycle.

6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.

Output Frequency

Output Duty Cycle

Rising Edge Slew

[3]

Rate
Falling Edge Slew

[3]

Rate
Output three-state Tim-

[3]

ing
Clock Jitter

Lock Time

[3]

Document #: 38-07013 Rev. *C Page 5 of 9

Switching Waveforms

All Outputs, Duty Cycle and Rise/Fall Time

t

2

OUTPUT

t

1

CY22392

t

3

Output Three-State Timing

OE

THREE-STATE

ALL

OUTPUTS

CLK Output Jitter

CLK

OUTPUT

Frequency Change

SELECT

OUTPUT

OLD SELECT NEW SELECT STABLE

F

old

t

4

t

5

t

6

t

7

F

new

t

5

Document #: 38-07013 Rev. *C Page 6 of 9

Test Circuit

AV

DD

CY22392

V

0.1 µF

DD

OUTPUTS

CLK out

C

LOAD

0.1 µF

GND

Ordering Information

Ordering Code Package Name Package Type Operating Range Operating Voltage

CY22392FC Z16 16-TSSOP Commercial (T
CY22392FI Z16 16-TSSOP Industrial (T
CY22392ZC-xxx
CY22392ZI-xxx
CY3672 FTG Development Kit

Notes:

7. The CY22392ZC-xxx and CY22392ZI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of
100 Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative.

[7]

[7]

Z16 16-TSSOP Commercial (TA = 0°C to 70°C) 3.3V
Z16 16-TSSOP Industrial (TA = –40°C to 85°C) 3.3V

= 0°C to 70°C) 3.3V

A

= –40°C to 85°C) 3.3V

A

Document #: 38-07013 Rev. *C Page 7 of 9

ng so indemnifies Cypress Semiconductor against all charges.

Package Diagram

16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16

CY22392

51-85091

Document #: 38-07013 Rev. *C Page 8 of 9

© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other righ ts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi

CY22392

Revision History

Document Title: CY22392 Three PLL General Purpose Flash Programmable Clock Generator
Document Number: 38-07013

REV. ECN NO.

** 106738 07/03/01 TLG New Data Sheet

*A 108515 08/23/01 JWK Updates based on characteriz ation resu lts . Removed “Preliminary” heading.

*B 110052 12/09/01 CKN Preliminary to Final.
*C 121864 12/14/02 RBI Power up requirements added to Operating Conditions Information

Issue
Date

Orig. of
Change Description of Change

Added paragraph on Junction Temperature limitations and part configura­tions. Removed solderi ng temperature rating. Split cryst al load into two typical
specs representing digital settings range. Ch anged t
Changed t

typical to 1.0 ms.

7

max to 300 ns.

5

Document #: 38-07013 Rev. *C Page 9 of 9