Datasheet CXP858P56A Datasheet (Sony)

CXP858P56A

CMOS 8-bit Single Chip Microcomputer

Description

The CXP858P56A is a CMOS 8-bit microcomputer
which consists of A/D converter, serial interface,
timer/counter, time-base timer, closed caption decoder,
data slicer, on-screen display function, I2C bus
interface, PWM output, remote control reception
circuit, HSYNC counter and watchdog timer as well
as basic configuration like 8-bit CPU, PROM, RAM
and I/O port.

Also this IC provides a power-on reset function
and sleep function that enables to lower power
consumption.

The CXP858P56A is the PROM-incorporated version
of the CXP85856A with built-in mask ROM. This
provides the additional feature of being able to write
directly into the program (also into the OSD
character ROM or caption character ROM possible).
Thus,
system development and for small-quantity production.

Features

• A wide instruction set (213 instructions) which covers various types of data

• Minimum instruction cycle 333ns at 12MHz operation

• Incorporated PROM 56K bytes (Programming)

• Incorporated RAM 2176 bytes (Excludes the closed caption decoder and on-screen display VRAM)

• Peripheral functions

• Interruption 15 factors, 15 vectors, multi-interruption possible

• Standby mode Sleep

• Package 64-pin plastic SDIP/QFP

it is most suitable for evaluation use during

– 16-bit operation/multiplication and division/Boolean bit operation instructions

4.5K bytes (OSD)
3K bytes (Caption)

– A/D converter 8-bit 6-channel successive approximation method

(Conversion time of 26.7µs at 12MHz)
– Serial interface 8-bit clock sync type, 1 channel
– Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer
– Closed caption decoder

Incorporated data slicer,

conforming to FCC (EDS supported), 8 × 13 dots, 192 character types,

15 character colors, 4 lines × 34 characters, italic, underline, vertical scrolling,

15 frame background colors/half blanking
– On-screen display (OSD) function

12 × 16 dots, 192 character types, 15 character colors, 2 lines × 24 characters,

8 frame background colors/half blanking,

15 background colors on full screen/half blanking,

edging and vertical scrolling for every line,

jitter elimination circuit,

sprite OSD, 12 × 16 dots, 1 screen, 8 colors for every dot
– I2C bus interface
– PWM output 8 bits, 8 channels
– Remote control reception circuit

8-bit pulse measurement counter, 6-stage FIFO
– HSYNC counter 2 channels
– Watchdog timer

64 pin SDIP (PIastic) 64 pin QFP (PIastic)

Structure

Silicon gate CMOS IC

urchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conform to the I2C Standard Specifications as defined by Philips.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E97738-PS

CXP858P56A

DD

Vpp
Vss
V
MP

RST
XTAL
EXTAL

INT2
INT1
INT0

CLOCK G ENERATOR^

PA0‘PA7

8

SYSTEM CO NTROL

SPC700 CPU CORE

PB0‘PB6

7

PO R T A

PO R T B

PC0‘PC7

8

PO R T C

PD0‘PD7

8

PO R T D

PE0‘PE2

3

PF0‘PF7

8

PO R T E

PO R T F

RAM

2176 BYTES

8

PW M 0‘PW M 7

8BIT PW M

PROM

56K BYTES

PRESC ALER^

TIME BASE TIMER

W ATCHDOG TIMER

SCL1
SCL0

C BUS

2

I

SDA1

SDA0

INTERFACE UNIT

INTERRUPT CONTROLLER

CVss
CV

DD

Cap
LFC 2

DATA SLICER

LFC 1

Block Diagram

3

2

FIFO

2

8BIT TIM ER^COUNTER 0

EC

8BIT TIMER 1

TO

A^D CO NVERTER

REMO CON

RM C

HSYNC COUNTER 0

HSC0

HSYNC COUNTER 1

6

HSC1

CC DECODER

ON SCR EEN DISPLAY

I

B

R

VIN

XLC

G

EXLC

YS

YM

HSYN C

SERIAL INTERFACE UNIT

SI

SO

SCK

VSYNC

AN0‘AN5

– 2 –

Pin Assignment (Top View) 64-pin SDIP

CXP858P56A

PC3
PC2

PC1
PC0

EC/PD7

RMC/PD6

HS1/PD5
HS0/PD4

SI/PD3

SO/PD2

SCK/PD1

INT2/PD0

HSYNC/PA7

VSYNC/PA6

RST

Vss

XTAL

EXTAL
PA5/AN5
PA4/AN4
PA3/AN3

PA2/AN2
PA1/AN1
PA0/AN0

CVss
LFC2
LFC1

VIN

CV

Cap

INT1/PB6

PB5

DD

10
11
12

14
15

26

29
30

32

13

16
17
18
19
20
21
22
23
24
25

27
28

31

1

2
3
4

5
6
7
8
9

64
63
62
61
60

59

58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

43

42

41
40
39

38
37
36
35

34
33

PC4
PC5

PC6
PC7
PF0/PWM0
PF1/PWM1
PF2/PWM2
PF3/PWM3
PF4/SCL0/PWM4
PF5/SCL1/PWM5
PF6/SDA0/PWM6
PF7/SDA1/PWM7
PE0/TO
PE1
PE2/INT0
MP
Vss

DD

V
Vpp
EXLC
XLC

YM
YS
I
B
G

R
PB0
PB1
PB2

PB3
PB4

Note) 1. Vpp (Pin 46) must be connected to VDD.

2. Vss (Pins 16 and 48) must be connected to GND.

3. MP (Pin 49) must be connected to GND.

– 3 –

Pin Assignment (Top View) 64-pin QFP

CXP858P56A

HS1/PD5
HS0/PD4

SI/PD3

SO/PD2

SCK/PD1

INT2/PD0

HSYNC/PA7
VSYNC/PA6

RST

Vss

XTAL

EXTAL

PA5/AN5

PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0

CVss

12
13
14
15
16
17
18
19

10
11

PD6/RMC

PC0

62

64

63

61

60

1

2
3
4

5
6
7
8
9

PC2

59

PC3

58

PC4

57

PC1

PD7/EC

PC5

56

PC6

55

PC7

54

PF2/PWM2

PF1/PWM1

PF0/PWM0

52

53

51
50
49
48
47
46
45
44

42

40
39

37
36
35

33

43

41

38

34

PF3/PWM3
PF4/SCL0/PWM4
PF5/SCL1/PWM5
PF6/SDA0/PWM6
PF7/SDA1/PWM7
PE0//TO
PE1
PE2/INT0

MP
Vss

V

DD

Vpp
EXLC
XLC

YM
YS
I
B
G

20

21

LFC2

22

LFC1

VIN

23

DD

CV

24

Cap

25

26

INT1/PB6

27

PB5

28

PB4

29

PB3

PB2

Note) 1. Vpp (Pin 40) must be connected to VDD.

2. Vss (Pins 10 and 42) must be connected to GND.

3. MP (Pin 43) must be connected to GND.

30

PB1

31

32

R

PB0

– 4 –

Pin Description

CXP858P56A

Symbol

PA0/AN0

to

PA5/AN5
PA6/VSYNC
PA7/HSYNC

PB0 to PB5

PB6/INT1

PC0 to PC7

PD0/INT2
PD1/SCK

PD2/SO
PD3/SI
PD4/HS0
PD5/HS1
PD6/RMC

I/O

I/O/Analog input

I/O/Input
I/O/Input

I/O

I/O/Input

I/O

I/O/Input
I/O/I/O

I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input

Description

(Port A)
8-bit I/O port. I/O

Analog inputs to A/D converter. (6 pins)

can be set in a unit
of single bits.
(8 pins)

OSD display vertical sync signal input.
OSD display horizontal sync signal input.

(Port B)
7-bit I/O port. I/O can be set in a unit of single bits.
(7 pins)

External interruption request input.
Active at the falling edge.

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

External interruption request input.
Active at the falling edge.

(Port D)
8-bit I/O port. I/O
can be set in a unit
of single bits.
Can drive 12mA
synk current.
(8 pins)

Serial clock I/O.
Serial data output.
Serial data input.
HSYNC counter (CH0) input.
HSYNC counter (CH1) input.

Remote control reception circuit input.
PD7/EC
PE0/TO
PE1

PE2/INT0
PF0/PWM0

to

PF3/PWM3
PF4/SCL0/PWM4

PF5/SCL1/PWM5
PF6/SDA0/PWM6

PF7/SDA1/PWM7
R, G, B, I, YS, YM

I/O/Input
I/O/Output
I/O

I/O/Input

Output/Output

Output/I/O

Output/I/O

Output

External event input for timer/counter.

(Port E)

Rectangular wave output for timer/counter.

3-bit I/O port. I/O
can be set in a unit
of single bits.
(3 pins)

(Port F)
8-bit output port
and large current

Input for external interruption request.

Active at the falling edge.

8-bit PWM outputs.

(8 pins)

(12mA) N-ch open
drain output.
Lower 4 bits are

Transfer clock I/O for I2C bus interface.

(2 pins)

medium drive voltage
(12V);upper 4 bits are

5V drive. (8 pins)

Transfer data I/O for I2C bus interface.

(2 pins)

6-bit OSD display outputs. (6 pins)

– 5 –

CXP858P56A

Symbol
EXLC
XLC

VIN
Cap

LFC1, LFC2
CVDD
CVSS
EXTAL
XTAL

RST

MP
Vpp
VDD

I/O Description
Input
Output

Input

—

—

OSD display clock oscillation I/O.
Oscillator frequency is determined by the external L and C.

External composite video signal input.
Input a 2Vp-p signal via a capacitor.

Connects a capacitor for the data slicer between Cap and CVSS.
Connects a capacitor for the PLL circuit LPF between LFC1 and LFC2.
Positive power supply for data slicer.

GND for data slicer.
Input
Output

Connects a crystal for system clock oscillation. When an external

clock is supplied, input it to EXTAL and leave XTAL open.

System reset; active at Low level. I/O pin.
I/O

Outputs a Low level when the power is turned on and the power-on

reset function operates.
Input

Test mode input. Must be connected to GND.

Positive power supply for internal PROM writing.

Under normal conditions, connect to VDD.

Positive power supply.

Vss

GND. Connect two VSS pins to GND.

– 6 –

Input/Output Circuit Format for Pins

Pin When resetCircuit format

Port A

CXP858P56A

Port A data

PA0/AN0

to

PA5/AN5

6 pins

PA6/VSYNC
PA7/HSYNC

Data bus

Port A function selection

“0” when reset

A/D converter

Port A

Data bus

Port A direction
“0” when reset

RD (Port A)

RD (Port A)

Input multiplexer

Port A data

Port A direction

“0” when reset

Schmitt input

IP

IP

Input
protection
circuit

Hi-Z

Hi-Z

2 pins

PB0 to PB5
PB6/INT1
PC0 to PC7

15 pins

VSYNC, HSYNC

Port B

Port C

Data bus

Ports B, C data

Ports B, C direction

“0” when reset

RD (Ports B, C)

INT1

Input polarity

“0” when reset

IP

Hi-Z

Schmitt input

– 7 –

Pin When resetCircuit format

Port D

Port D data

PD0/INT2
PD3/SI
PD4/HS0
PD5/HS1

Port D direction

“0” when reset

PD6/RMC
PD7/EC

6 pins

Data bus

RD (Port D)

INT2, SI, HS0, HS1, RMC, EC

Port D

SCK, SO

Serial output enable

Schmitt input

∗

∗

IP

Large current 12mA

CXP858P56A

Hi-Z

PD1/SCK
PD2/SO

2 pins

PE0/TO
PE1
PE2/INT0

Port E

Port D data

Port D direction

“0” when reset

Data bus

RD (Port D)

SCK only

TO

Port E function selection

“1” when reset

Port E data

“1” when reset for PE0, 1

Port E direction

“1” when reset for PE0, 1
“0” when reset for PE2

Data bus

Schmitt input

∗

Large current 12mA

Schmitt input
only for PE2

∗

IP

Hi-Z

PE0, PE1:

IP

High level

PE2: Hi-Z

3 pins

RD (Port E)

INT0

– 8 –

Pin When resetCircuit format

Port F

PWM0 to PWM3

PF0/PWM0

to

PF3/PWM3

Port F data

“1” when reset

CXP858P56A

∗

Hi-Z

4 pins

PF4/SCL0/PWM4
PF5/SCL1/PWM5
PF6/SDA0/PWM6
PF7/SDA1/PWM7

4 pins

R
G
B

I

YS

YM

6 pins

Port F function selection

“0” when reset

Port F

SCL, SDA

I2C output enable

PWM4 to PWM7

Port F data

“1” when reset

Port F function selection

“0” when reset

SCL, SDA

(I2C circuit)

R, G, B, I, YS, YM

Output polarity
“0” when reset

Schmitt input

Output becomes active
by data writing to output
polarity register.

∗

12V drive

Large current 12mA

∗

IP

BUS SW

To internal I

(SCL1 for SCL0)

∗

Large current 12mA

2

Hi-Z

C pins

Hi-Z

EXLC
XLC

2 pins

EXLC

XLC

IP

Oscillator control

Oscillation
halted

IP

OSD display clock

– 9 –

Pin When resetCircuit format

A

EXTAL

EXTAL

IP

XTAL

XTAL

2 pins

Pull-up resistor

RST

Schmitt input

1 pin

• Diagram shows the circuit
composition during oscillation.

• Feedback resistor is removed
during stop mode.
(This device does not enter the
stop mode.)

From power-on reset circuit

CXP858P56A

Oscillation

Low level

– 10 –

CXP858P56A

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Ratings Unit Remarks

VDD

–0.3 to +7.0

V

Supply voltage

Input voltage
Output voltage
Medium drive output voltage
High level output current
High level total output current

Vpp
VIN
VOUT
VOUTP
IOH
ΣIOH

IOL

–0.3 to +13.0
–0.3 to +7.0
–0.3 to +7.0

–0.3 to +15.0

–5

–50

15

∗1
∗1

V

Incorporated PROM
V
V
V

PF0 to PF3 pins

mA
mA

Total of all output pins

Ports excluding large current

mA

outputs (value per pin)

Low level output current

IOLC

Low level total output current
Operating temperature
Storage temperature

Allowable power dissipation

∗1

VIN and VOUT should not exceed VDD + 0.3V.

∗2

The large current output port is Port D (PD) and Port F (PF).

ΣIOL
Topr
Tstg

PD

20

100

–10 to +75

–55 to +150

1000

600

mW
mW

Large current output port

mA

(value per pin)

mA

Total of all output pins

°C
°C

SDIP-64P-01

QFP-64P-L01

∗2

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding those conditions may adversely
affect the reliability of the LSI.

Recommended Operating Conditions

(Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

Guaranteed operation range for 1/2 and 1/4

4.5

Supply voltage

VDD

3.5

2.5

Vpp

Data slicer supply
voltage

CVDD
VIH

High level
input voltage

VIHS
VIHEX
VIL

Low level
input voltage

VILS
VILEX

Operating temperature

∗1

This device does not enter the stop mode.

∗2

PA, PB, PC, PE0 to PE1, SCL0 to SCL1, SDA0 to SDA1 pins.

∗3

INT2, SCK, SO, SI, HS0, HS1, RMC, EC, INT1, HSYNC, VSYNC, RST pins.

∗4

Specifies only during external clock input.

∗5

CVDD and VDD should be set to the same voltage.

∗6

Vpp and VDD should be set to the same voltage.

Topr

Vpp = VDD

4.5

0.7VDD

0.8VDD

VDD – 0.4

0
0

–0.3

–10

5.5

5.5

5.5

5.5

VDD
VDD

VDD + 0.3

0.3VDD

0.2VDD

0.4

+75

V

frequency dividing clocks
Guaranteed operation range for 1/16

V

frequency dividing clock or sleep mode

V

Guaranteed data hold range for stop mode

∗6

V

∗5

V

∗2

V

∗3

V
V

EXTAL pin

∗2

V

∗3

V
V

EXTAL pin

°C

– 11 –

∗1

∗4

∗4

CXP858P56A

DC Characteristics (Ta = –10 to +75°C, Vss = 0V reference)

Item

High level
output voltage

Low level
output voltage

Input current

I/O leakage current

Open drain output
leakage current
(in N-ch Tr OFF state)

Symbol

VOH

VOL

IIHE
IIHL
IILR

IIZ

ILOH

Pin Condition Min. Typ. Max. Unit

PA to PD, PE, R, G,
B, I, YS, YM

PA to PD, PE, R, G,
B, I, YS, YM,
PF0 to PF3, RST

PD, PF
PF4 to PF7

(SCL0, SCL1,
SDA0, SDA1)

EXTAL

∗2

RST
PA to PE, HSYNC,

VSYNC, R, G, B, I,
YS, YM, RST

∗2

PF0 to PF3
PF4 to PF7

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA

VDD = 4.5V, IOL = 1.8mA

∗1

VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 4.5V, IOL = 3.0mA

VDD = 4.5V, IOL = 4.0mA
VDD = 5.5V, VIH = 5.5V

VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 0.4V

VDD = 5.5V,
VI = 0, 5.5V

VDD = 5.5V, VOH = 12.0V
VDD = 5.5V, VOH = 5.5V

4.0

3.5

0.5
–0.5
–1.5

0.4

0.6

1.5

0.4

0.6
40

–40

–400

±10

50
10

V
V

V
V

V
V

V

µA
µA
µA

µA

µA
µA

I2C bus switch
connection impedance
(in output Tr OFF state)

RBS

SCL0: SCL1
SDA0: SDA1

VDD = 4.5V
VSCL0 = VSCL1 = 2.25V
VSDA0 = VSDA1 = 2.25V

120

1/2 frequency dividing

IDD

clock operation VDD = 5.5V
12MHz crystal oscillation

43

55

(C1 = C2 = 15pF)
Sleep mode

VDD = 5.5V
12MHz crystal oscillation

2.5

5.5

Supply current

IDDSL

VDD

∗3

(C1 = C2 = 15pF)

∗4

—

—

—

IDDST

Stop mode
VDD = 5.5V
Termination of 12MHz
crystal oscillation

ICVDD

Input capacitance

∗1

Specifies RST pin only when the power-on reset circuit is selected with mask option.

∗2

For RST pin, specifies the input current when pull-up resistance is selected, and specifies the leakage

CIN

CVDD
PA to PE, SCL, SDA,

EXLC, EXTAL, VIN,
RST

VDD = 5.5V

1MHz clock
0V for no-measured pins

—

5.0

10

10.0

20

current when non-resistance is selected.

∗3

When all output pins are left open. Specifies only when the OSD oscillation is halted.

∗4

This device does not enter the stop mode.

Ω

mA

mA

µA

mA

pF

– 12 –

AC Characteristics

A

A

(1) Clock timing

CXP858P56A

(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Max. Unit

System clock frequency

System clock input
pulse width

System clock input
rise and fall times

Event counter input
clock pulse widtth

Event counter input clock
rise and fall times

∗

1

Indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits
(CPU clock selection).

fC

tXL,
tXH

tCR,
tCF

tEH,
tEL

tER,
tEF

XTAL
EXTAL

EXTAL

EXTAL

EC

EC

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig 1, Fig 2
External clock drive

Fig. 3

Fig. 3

tsys

37.5

∗1

+ 50

Typ.

12.0

200

20

tsys (ns) = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

Fig. 1. Clock timing

1/fc

MHz

ns

ns

ns

ms

EXTAL

Fig. 2. Clock applied condition

Crystal oscillation
Ceramic oscillation

EXTAL

AA

C

1 C2

Fig. 3. Event count clock timing

EC

t

XH tXLtCF tCR

External clock

XTAL

EH tELtEF tER

t

EXTAL

AA

OPEN

XTAL

DD – 0.4V

V

0.4V

0.8VDD

0.2VDD

– 13 –

CXP858P56A

(2) Serial transfer (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

SCK cycle time

SCK
High and Low level widths

SI input setup time
(for SCK ↑)

SI hold time
(for SCK ↑)

Symbol Pin Condition Min. Max. Unit

tKCY

tKH
tKL

tSIK

tKSI

SCK

Input mode
Output mode
SCK input mode

SCK

SCK output mode
SCK input mode

SI

SCK output mode
SCK input mode

SI

SCK output mode

1000

8000/fc

400

4000/fc – 50

100
200
200
100

SCK input mode

SCK ↓ → SO delay time

tKSO

SO

SCK output mode

Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

Fig. 4. Serial transfer timing

tKCY

200
100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

SCK

SI

SO

tKL tKH

tSIK

Input data

tKSO

0.8VDD

0.2VDD

0.8VDD

0.2VDD

tKSI

0.8VDD

0.2VDD

Output data

– 14 –

CXP858P56A

(3) A/D converter characteristics (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Typ. Max. Unit
Resolution
Linearity error
Zero transition

voltage
Full-scale transition

voltage
Conversion time
Sampling time
Analog input voltage

∗1

VZT

∗2

VFT

tCONV
tSAMP

VIAN

AN0 to AN5

Fig. 5. Definitions of A/D converter terms

FF

h

FEh

Digital conversion value

01h
00h

VZT VFT

Linearity error

Analog input

8

±3

Ta = 25°C
VDD = 5.0V

–10

10

70

Vss = 0V

4910

160/fADC

12/fADC

∗3

∗3

0

∗1

Value at which the digital conversion value changes from

4970

5030

VDD

00h to 01h and vice versa.

∗2

Value at which the digital conversion value changes from
FEh to FFh and vice versa.

∗3

fADC indicates the below values due to the contents of bit 6
(CKS) of the A/D control register (ADC: 00F9h) and bits 7
(PCK1) and 6 (PCK0) of the clock control register (CLC:
00FEh).

Bits

LSB

mV

mV

µs
µs

V

PCK1, 0

00 (φ = fEX/2)
01 (φ = fEX/4)
11 (φ = fEX/16)

– 15 –

CKS

0 (φ/2 selection) 1 (φ selection)

fADC = fC/2
fADC = fC/4

fADC = fC/16

fADC = fC
fADC = fC/2
fADC = fC/8

(4) Interruption, reset input (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Max. Unit

CXP858P56A

External interruption
High and Low level widths

Reset input Low level width

Fig. 6. Interruption input timing

INT0
INT1
INT2
(falling edge)

Fig. 7. RST input timing

RST

tIH
tIL

tRSL

INT0
INT1
INT2

RST

tIH tIL

0.8VDD

tRSL

0.2VDD

1

32/fc

µs

µs

0.2VDD

(5) Power-on reset (Ta = –10 to +75°C, Vss = 0V reference)

Item Symbol Pin Condition Min. Max. Unit

Power supply rise time

tR

Power-on reset

0.05

50 ms

VDD

Power supply cutt-off time

tOFF

Repeated power-on reset

1

ms

Fig. 8. Power-on reset

DD

V

4.5V

0.2V

tR tOFF

Take care when turning the power on.

0.2V

– 16 –

CXP858P56A

(6) I2C bus timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item
SCL clock frequency
Bus-free time before starting transfer
Hold time for starting transfer
Clock Low level width
Clock High level width
Setup time for repeated transfers
Data hold time
Data setup time
SDA, SCL rise time
SDA, SCL fall time
Setup time for transfer completion

∗1

The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it.

Symbol Pin Condition Min. Max. Unit

fSLC

tBUF
tHD; STA
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tR
tF
tSU; STO

SCL
SDA, SCL
SDA, SCL
SCL
SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL

0

4.7

4.0

4.7

4.0

4.7

∗1

0

250

4.7

100

1

300

Fig. 9. I2C bus transfer timing

kHz

µs
µs
µs
µs
µs
µs
ns
µs
ns
µs

SDA

t

BUF

SCL

tHD; STA

SP

tLOW

Fig. 10. I2C device recommended circuit

I2C

device

RS RS RS RS RP RP

SDA0
(or SDA1)

SCL0
(or SCL1)

I2C

device

tFtR

tSU; DATtHIGHtHD; DAT

tHD; STA

tSU; STA

t

SU; STO

PSt

• A pull-up resistor (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).

• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce spike

noise caused by CRT flashover.

– 17 –

(7) OSD timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

CXP858P56A

Item

OSD clock frequency

HSYNC pulse width
HSYNC after-write

rise and fall times
VSYNC before-write

rise and fall times

Fig. 11. OSD timing

For OSD I/O polarity register

HSYNC

(OPOL: 01FDh)

bit 7 at “0”

Symbol

fOSC

tHWD
tHCG

tVCG

Pin Condiiton

EXLC
XLC

HSYNC
HSYNC

VSYNC

tVCG

Fig. 12

Fig. 11
Fig. 11

Fig. 11

tHWD

Min. Max.

4

16.5

1.2
200

1.0

tHCG

0.8VDD

0.2VDD

Unit

MHz

µs
ns

µs

For OSD I/O polarity register

VSYNC

(OPOL: 01FDh)

bit 6 at “0”

0.8VDD

0.2VDD

Fig. 12. LC oscillation circuit connection

EXLC XLC

∗

1

L

∗1

The XLC series resistor can reduce the frequency of occurrence of the undersired radiation.

R

2C1

C

– 18 –

CXP858P56A

(8) Data slicer external circuit (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

VIN pin coupling capacitance

Cap pin capacitance

PLL low-pass filter capacitance

Composite video signal input

Symbol Pin Min. Unit

CVIN

Ccap

CLPF

Video In

VIN

Cap

LFC1,
LFC2

VIN

Fig. 13. Data slicer external recommeded circuit

Typ. Max.

0.1

4700

0.47

2.0

5.0V

CLPF

CVDD
LFC2

LFC1

µF

pF

µF

Vp-p

Remarks

The B characteristic or more
of temperature characteristics
is recommended.

The B characteristic or more
of temperature characteristics
is recommended.

The B characteristic or more
of temperature characteristics
is recommended.

C

VINR1

IN

V

Video In

C1 R2

Cap

Ccap

CVss

[Recommended Constant]

R1 = 220Ω (error: 5%; allowable power dissipation: 1/8W or more)
R2 = 1MΩ (error: 5%; allowable power dissipation: 1/8W or more)
C1 = 1200pF (ceramic), the B characteristic or more of temperature characteristics is recommended.

– 19 –

Appendix

A

A

Fig. 14. SPC700 Series recommended oscillation circuit

(i)

EXTAL

EXTAL

AA

AA

XTAL

XTAL

Rd

Rd

C2C1

CXP858P56A

Manufacturer

RIVER ELETEC
CO., LTD.

KINSEKI LTD.

∗1

The XTAL series resistor can reduce the effect of electrostatic discharge noise.

Products List

Option item

Package
Program ROM capacity

Reset-pin pull-up resistor
Power-on reset circuit
Font data

Model fc (MHz)

HC-49/U03
HC-19/U (-S)

64-pin plastic

SDIP/QFP

40/48/56K bytes
Existent/Non-existent
Existent/Non-existent

User specified

Mask

12.0

12.0

C1 (pF) C2 (pF)

5

15

CXP858P56AS-1­CXP858P56AQ-1-

64-pin plastic

SDIP/QFP

PROM 56K bytes

User specified (PROM)

5

15

Existent
Existent

Rd (Ω)

0
0

∗2

∗1
∗1

Circuit

example

(i)
(i)

∗2

The font data for the one-time PROM version can be written in the same way as for the program.

– 20 –

Fig. 15. Characteristics curves

CXP858P56A

(fc = 12MHz, Ta = 25°C, Typical)

100

10

Supply current [mA]

DD –

I

1

IDD vs. VDD

1/2 frequency
dividing mode

1/4 frequency
dividing mode

1/16 frequency
dividing mode

Sleep mode

50

45

40

35

30

25

Supply current [mA]

20

DD –

I

15

10

5

(VDD = 5V, Ta = 25°C, Typical)

IDD vs. fc

1/2 frequency
dividing mode

1/4 frequency
dividing mode

1/16 frequency
dividing mode

Sleep mode

0.1
3456

V

DD – Supply voltage [V]

Parameter curve for OSD oscillation L vs. C

(Theoretically calculated value)

100

10

Inductance [µH]

–

L

fOSC =

0

1

2π LC

C = C

50 100

1, C2 – Capacitance [pF]

C

0

– System clock [MHz]

fc

161284

10MHz
12MHz
14MHz

16MHz

1//C2

– 21 –

Package Outline Unit: mm

CXP858P56A

64PIN SDIP (PLASTIC) 750mil

+ 0.4

57.6 – 0.1

64

33

+ 0.3

19.05

17.1 – 0.1

+ 0.1

132

1.778
+ 0.4

4.75 – 0.1

0.5 MIN

0.5 ± 0.1

3 MIN

0.9 ± 0.15

PACKAGE STRUCTURE

EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY

8.6g

SONY CODE
EIAJ CODE
JEDEC CODE

SDIP-64P-01

SDIP064-P-0750-A

MOLDING COMPOUND
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT

0.25 – 0.05

0° to 15°

52

64

SONY CODE
EIAJ CODE
JEDEC CODE

64PIN QFP(PLASTIC)

23.9 ± 0.4
+ 0.4

20.0 – 0.1

51

1

1.0

+ 0.15

0.4 – 0.1

33

32

+ 0.4

14.0 – 0.1

17.9 ± 0.4

20

19

± 0.12

+ 0.35

2.75 – 0.15

M

PACKAGE STRUCTURE

QFP–64P–L01
QFP064–P–1420

PACKAGE MATERIAL

LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS

EPOXY RESIN
SOLDER/PALLADIUM

42/COPPER ALLOY

1.5g

0.15 – 0.05

+ 0.2

0.1 – 0.05

PLATING

+ 0.1

0.15

16.3

0.8 ± 0.2

– 22 –