Datasheet CXP845F60 Datasheet (Sony)

Description

The CXP845F60 is a CMOS 8-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, timer/counter, time-base timer, capture
timer/counter, PWM output and the like besides the
basic configurations of 8-bit CPU, flash EEPROM,
RAM and I/O port.

The CXP845F60 also provides a sleep/stop functions
that enable to execute the power-on reset function or
lower the power consumption.

The CXP845F60 is the flash EEPROM-incorporated
version of the CXP84540/84548 with a built-in mask
ROM. This enables program writing and erasing.
Thus, it is most suitable for evaluation use during
system development and for small-quantity production.

Features

• A wide instruction set (213 instructions) which covers various types of data

— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle 143ns at 28MHz operation (4.5 to 5.5V)

• Incorporated flash EEPROM 60K bytes

Rewrite time 100 times

• Incorporated RAM 1472 bytes

• Peripheral functions

— A/D converter 8 bits, 8 channels, successive approximation method

(Conversion time of 1.93µs at 28MHz)

— Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes,

latch output function, MSB/LSB first selectable), 1 channel
8-bit clock sync type, 1 channel

— Timer 8-bit timer

8-bit timer/counter
19-bit time-base timer
16-bit capture time/counter

— PWM output 8 bits, 2 channels

• Interruption 14 factors, 14 vectors, multi-interruption possible

• Standby mode Sleep/stop

• Package 80-pin plastic QFP
Structure

Silicon gate CMOS IC

CMOS 8-bit Single Chip Microcomputer

– 1 –

E96906-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXP845F60

80 pin QFP (Plastic)

– 2 –

CXP845F60

Block Diagram

8

AN0 to AN7

PWM0

PWM1

CS0

SI0

SO0

SCK0

SI1

SO1

SCK1

TO

CINT

EC1

EC0

A/D CONVERTER

AVss

AV

REF

8 BIT PWM GENERATOR 0

SERIAL

INTERFACE

UNIT 0

FIFO

SERIAL INTERFACE UNIT 1

8 BIT TIMER/COUNTER 0

8 BIT TIMER 1

16 BIT CAPTURE

TIMER/COUNTER 2

INTERRUPT CONTROLLER

INT0

INT1

INT2

INT3

NMI

SPC700

CPU CORE

Flash EEPROM

60K BYTES

CLOCK

GENERATOR/

SYSTEM CONTROL

RAM

1472 BYTES

PRESCALER/
TIME-BASE TIMER

EXTAL

XTAL

V

DD

Vss

PORT A

8

8

8

4
4

8

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE3
PE4 to PE7

PF0 to PF7

PG0 to PG7

PI0 to PI7

RST

8

8

8

PORT B

PORT C

PORT D

PORT E

PORT F

PORT G

PORT I

PH0 to PH7

8

PORT H

2

2

LAT0

8 BIT PWM GENERATOR 1

PWE

TETA

TETB

TETC

– 3 –

CXP845F60

Pin Assignment 1 (Top View)

2
3
4

5
6
7
8
9

10
11
12
13
14
15
16
17
18
19

20
21
22
23

24

25

26

27 28

29

30

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70

69

68

67

63

64

65

66

61

62

71

72

73

74

75

76

77

78

79

80

1

PE1/EC1

PI4
PI3/INT3
PI2/INT2
PI1/INT1
PI0/INT0
PE5/TO/PWM1/(TETA)
PE4/PWM0/(TETB)
PE3/NMI/(TETC)
PE2/CINT

PE0/EC0
PB7/SO1

PB6/SI1
PB5/SCK1

PB4/SO0
PB3/SI0
PB2/SCK0
PB1/CS0
PB0/LAT0
PA7/AN7

PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3

PH3

PH4

PH5

PH6

PH7

RST

EXTAL

XTAL

V

SS

PE6

PE7

AV

SS

AV

REF

PA0/AN0

PA1/AN1

PA2/AN2

PF3
PF4
PF5
PF6

PF7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PH0
PH1
PH2

PF2

PF1

PF0

PG7

PG6

PG5

PG4

PWE

V

DD

PG3

PG2

PG1

PG0

PI7

PI6

PI5

Notes) 1.PWE (Pin 73) is left open during normal operation.

2.See the Appendix concerning the Pins 57 to 59 (TETA, TETB and TETC).

– 4 –

CXP845F60

Pin Description

Symbol I/O Description

I/O/Analog input

PA0/AN0

to

PA7/AN7

(Port A)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of the
pull-up resistor can be set
through the software in a
unit of 4 bits.
(8 pins)

Analog inputs to A/D converter.
(8 pins)

I/OPC0 to PC7

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink
current. Incorporation of pull-up resistor can be set through the software
in a unit of 4 bits.
(8 pins)

I/OPD0 to PD7

(Port D)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull­up resistor can be set through the software in a unit of 4 bits.
(8 pins)

I/OPF0 to PF7

(Port F)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of
pull-up resistor can be set through the software in a unit of 4 bits.
(8 pins)

Input/Input
Input/Input
Input/Input
Input/Input/

(Input)
Output/Output/

(Input)
Output/Output/

Output/(Input)
Output
Output

PE0/EC0
PE1/EC1
PE2/CINT
PE3/NMI/

(TETC)
PE4/PWM0/

(TETB)
PE5/TO/

PWM1/(TETA)
PE6
PE7

(Port E)
8-bit port. Lower 4 bits
are for inputs; upper
4 bits are for outputs.
(8 pins)

External event inputs for timer/counter.
(2 pins)

Capture trigger input.

I/O/Output
I/O/Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/Input
I/O/Output

PB0/LAT0
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1

(Port B)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of pull-up
resistor can be set
through the software in a
unit of 4 bits.
(8 pins)

Latch output for serial interface (CH0).
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).

Control pins
for flash
EEPROM
write.
(3 pins)

Non-maskable interruption
request input.

8-bit PWM0 output.
Rectangular wave output for 16-bit

timer/counter and 8-bit PWM1 output.

– 5 –

CXP845F60

Symbol I/O Description

I/OPG0 to PG7

(Port G)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull­up resistor can be set through the software in a unit of 4 bits.
(8 pins)

I/OPH0 to PH7

(Port H)
8-bit I/O port. I/O and standby release input function can be set in a unit
of single bits. Incorporation of pull-up resistor can be set through the
software in a unit of 4 bits.
(8 pins)

I/O/Input

PI0/INT0

to

PI3/INT3

I/O

PI4 to PI7

Input

Connects a crystal for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.

EXTAL

OutputXTAL
I/O

System reset for active at Low level. This pin is I/O pin, and outputs Low
level at the power on with the power-on reset function executed.

RST

Flash EEPROM write enable pin.
Write is enabled at Low level; write is prohibited at High level.
Leave this pin open for normally operation.

PWE

Input

Reference voltage input for A/D converter.

AVREF

A/D converter GND.

AVss

Positive power supply.

VDD

GND

Vss

(Port I)
8-bit I/O port. I/O can be set in a unit of single
bits. Incorporation of pull-up resistor can be set
through the software in a unit of 4 bits.
(8 pins)

External interruption
request inputs.
(4 pins)

Input

– 6 –

CXP845F60

Data bus

RD (Port B)

Port B direction

IP

Port B data

Pull-up resistor

"0" when reset

"0" when reset

LAT0

Latch output enable

∗

Pull-up transistor

Approx. 100kΩ (VDD = 4.5 to 5.5V)

∗

Data bus

RD (Port B)

Port B direction

IP

Port B data

Pull-up resistor

"0" when reset

"0" when reset

Schmitt input

CS0
SI0
SI1

∗

Pull-up transistor

Approx. 100kΩ (VDD = 4.5 to 5.5V)

∗

Port B

8 pins

Hi-Z

Hi-Z

When reset

PA0/AN0

to

PA7/AN7

PB0/LAT0

Port B

1 pin

Hi-Z

PB1/CS0
PB3/SI0
PB6/SI1

Data bus

RD (Port A)

Port A direction

IP

Port A data

Pull-up resistor

Port A function
selection

Input protection
circuit

"0" when reset

"0" when reset

"0" when reset

Input multiplexer

A/D converter

∗

Pull-up transistor

Approx. 100kΩ (VDD = 4.5 to 5.5V)

∗

Input/Output Circuit Formats for Pins

Port A

Pin

Circuit format

3 pins

– 7 –

CXP845F60

Port B

2 pins

Hi-Z

Hi-Z

PB2/SCK0
PB5/SCK1

PB4/SO0
PB7/SO1

Port C

2 pins

8 pins

Hi-Z

PC0 to PC7

Data bus

RD (Port B)

IP

Port B function
selection

"0" when reset

Schmitt input

SCK0, SCK1 in

Port B data

Port B direction

"0" when reset

Pull-up resistor
"0" when reset

SCK OUT

Serial clock output enable

∗

Pull-up transistor

Approx. 100kΩ (VDD = 4.5 to 5.5V)

∗

Port B

When resetPin

Circuit format

Pull-up resistor

Serial data output enable

Port B function
selection

"0" when reset

Port B data

Port B direction

"0" when reset

SO

∗

IP

Data bus

Data bus

RD (Port B)

Pull-up resistor

"0" when reset

Port C data

Port C direction

"0" when reset

RD (Port C)

∗

Pull-up transistor

Approx. 100kΩ (V

∗

1

Large current drive

DD = 4.5 to 5.5V)

*

1

IP

∗

2

12mA (VDD = 4.5 to 5.5V)

∗

2

Pull-up transistor

Approx. 100kΩ (VDD = 4.5 to 5.5V)

– 8 –

CXP845F60

A

A

A

High level
High level

at ON

resistance

of pull-up
transistor

during

a reset.

4 pins

1 pin

PE0/EC0
PE1/EC1
PE2/CINT
PE3/NMI/
(TETC)

PE4/PWM0/
(TETB)

PE5/TO/
PWM1/
(TETA)

1 pin

Low level

PE6, PE7

2 pins

Data bus

RD (Port E)

Port E data

"0" when reset

IP

Schmitt input

RD (Port E)

Data bus

EC0, EC1
CINT, NMI

(to flash EEPROM circuit)

Data bus

Port E function
selection

PWM0

Port E data

"0" when reset

"1" when reset

RD (Port E)

(to flash EEPROM circuit)

Port E

Port E

Port E

Port E

Hi-Z

High level

When resetPin

Circuit format

Port E data

"1" when reset

TO

PWM1

Port E function selection

(upper)

AAA

Port E function selection

(lower)

"00" when reset

TO output enable

Internal reset signal

00

AA

MPX
01
1x

AA

(to flash EEPROM circuit)

∗

Pull-up transistor

Approx. 150kΩ (VDD = 4.5 to 5.5V)

∗

– 9 –

CXP845F60

28 pins

PD0 to PD7
PF0 to PF7
PG0 to PG7
PI4 to PI7

IP

Ports D, F, G, I data

"0" when reset

Ports D, F, G, I direction

Pull-up resistor

"0" when reset

RD

Data bus

∗

Pull-up transistor

Approx. 100kΩ (V

DD = 4.5 to 5.5V)

∗

Port I

8 pins

Hi-Z

PH0 to PH7

Data bus

RD (Port H)

Port H direction

IP

Port H data

Pull-up resistor

"0" when reset

"0" when reset

Standby release

Edge detection

∗

Pull-up transistor

Approx. 100kΩ (VDD = 4.5 to 5.5V)

∗

Port H

4 pins

Hi-Z

PI0/INT0

to

PI3/INT3

Port D

Port F

Port G

Port I

Hi-Z

Data bus

IP

Port I data

"0" when reset

∗

Pull-up transistor

Approx. 100kΩ (VDD = 4.5 to 5.5V)

∗

Port I direction

Pull-up resistor

"0" when reset

INT0
INT1
INT2
INT3

RD

Schmitt input

When resetPin

Circuit format

– 10 –

CXP845F60

2 pins

Oscillation

EXTAL
XTAL

1 pin

RST

Low level

IP

EXTAL

XTAL

• Diagram shows the circuit
composition during oscillation.

• Feedback resistor is removed
during stop mode and XTAL

becomes High level.

IP

Schmitt input

Pull-up resistor

IP

from power-on reset circuit

When resetPin

Circuit format

1 pin

PWE

High level

Pull-up resistor

IP

to flash EEPROM circuit

– 11 –

CXP845F60

∗1

VIN and VOUT must not exceed VDD + 0.3V.

∗2

The large current drive transistor is the N-ch transistor of Port C (PC).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.

Input voltage
Output voltage
High level output current
High level total output current

Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation

VDD
AVSS
VIN
VOUT
IOH
∑IOH

IOL
IOLC

∑IOL
Topr
Tstg
PD

Supply voltage

Low level output current

–0.3 to +7.0
–0.3 to +0.3

–0.3 to +7.0

∗1

–0.3 to +7.0

∗1

–5

–50

15
20

100

–20 to +75

–55 to +150

600

V
V
V

V
mA
mA

mA
mA

mA

°C
°C

mW

Output (value per pin)
Total for all output pins
All pins excluding large current outputs

(value per pin)
Large current outputs (value per pin∗2)
Total for all output pins

Item Symbol Ratings Unit Remarks

Absolute Maximum Ratings (Vss = 0V reference)

High level input
voltage

Low level input
voltage

Operating temperature

Supply voltage

5.5

5.5

5.5
VDD
VDD

VDD + 0.3

0.3VDD

0.2VDD
+0.4

+75

V
V
V
V
V
V

°C

V

Item Symbol Min. Max. Unit Remarks

4.5

3.5

2.0

0.7VDD

0.8VDD

VDD – 0.4

0
0

–0.3

–20

VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr

Guaranteed operation range for 1/2 and 1/4
frequency dividing modes

Guaranteed operation range for 1/16 frequency
dividing and sleep modes

Guaranteed data hold range during stop mode

∗1

Hysteresis input

∗2

EXTAL

∗3

∗1

Hysteresis input

∗2

EXTAL

∗3

VDD

∗1

Normal input ports (PA, PB0, PB4, PB7, PC, PE0 to PE3, PD, PF to PH, PI4 to PI7)

∗2

RST, CINT, CS0, SCK0, SCK1, EC0, EC1, SI0, SI1, NMI, INT0, INT1, INT2, INT3

∗3

Specifies only during external clock input.

Recommended Operating Conditions (Vss = 0V reference)

– 12 –

CXP845F60

Electrical Characteristics

DC Characteristics (VDD = 4.5 to 5.5V)

(Ta = –20 to +75°C, Vss = 0V reference)

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V

VDD = 5.5V, VIL = 4.0V

High level
output voltage

4.0

3.5

0.1
–0.1
–1.5

–2.78

V
V
V
V

V
µA
µA
µA
µA
µA

µA

PC

PA to PD,
PE4 to PE7,
PF to PI,
RST (only VOL)

EXTAL

RST
PA to PD

∗1

PF to PI

∗1

Item Symbol Pin Conditions

Min.

Clock 1MHz
0V for all pins excluding measured
pins

VDD

IDD1

IIZ

IDD2
IDDS1

IDDS2

IDDS3

CIN

VOH

VOL

IIHE
IILE
IILR

IIL

Low level
output voltage

Input current

Typ.

0.4

0.6

1.5
25

–25

–400

–50

±10

Max. Unit

∗1

For PA to PD and PF to PI pins, specifies the input current when pull-up resistance is selected; leakage
current when no resistance is selected.

∗2

When all output pins are left open.

VDD = 5.5V, 28MHz crystal oscillation
(C1 = C2 = 1pF)

Sleep mode

Supply
current

∗2

Input
capacity

VDD = 4.5V, VIL = 4.0V
VDD = 5.5V,

VI = 0, 5.5V
For 1/2 frequency dividing mode

I/O leakage
current

PA to PD

∗1

PF to PI

∗1

PE0 to PE3

38

2.5

10

66

10

30

20

mA

mA

µA

pF

VDD = 5.5V, 28MHz crystal oscillation
(C1 = C2 = 1pF)

Stop mode

VDD = 5.5V, termination of 28MHz
crystal oscillation

PA to PD,
PE0 to PE3,
PF to PI,
EXTAL,
RST

– 13 –

CXP845F60

∗1

tsys indicates the three values according to the contents of the clock control register (CLC: 00FEh) upper

2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

EXTAL

t

XH tXLtCF tCR

0.4V

V

DD – 0.4V

1/fc

A

A

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

External clock

EXTAL

XTAL

74HC04

C

1

C2

AC Characteristics

(1) Clock timing

System clock frequency

System clock input pulse width
System clock input

rise time, fall time
Event count input clock

pulse width
Event count input clock

rise time, fall time

fC

tXL,
tXH

tCR,
tCF

tEH,
tEL

tER,
tEF

XTAL
EXTAL

EXTAL

EXTAL
EC0

EC1
EC0

EC1

MHz

ns

ns

ns

ms

Item Symbol Pin Conditions Min. Unit

Fig. 1, Fig. 2
Fig. 1, Fig. 2

External clock drive
Fig. 1, Fig. 2

External clock drive
Fig. 3

Fig. 3

1

15.6

tsys + 50

∗1

Typ. Max.

28

100

20

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Fig. 2. Clock applied conditions

Fig. 1. Clock timing

tEH tELtEF tER

0.2VDD

0.8VDD

tTH tTLtTF tTR

EC0
EC1

Fig. 3. Event count clock timing

AAA

AA

– 14 –

CXP845F60

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode

Chip select transfer mode
Chip select transfer mode

Note 1) tsys indicates the three values according to the contents of the clock control register (CLC: 00FEh)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

CS0 ↓ → SCK0
delay time

CS0 ↑ → SCK0
float delay time

CS0 ↓ → SO0
delay time

CS0 ↑ → SO0
float delay time

CS0 High level width

SCK0 cycle time

SCK0
High, Low level width

SI0 input setup time
(for SCK0 ↑)

SI0 input hold time
(for SCK0 ↑)

SCK0 ↓ → SO0
delay time

tDCSK

tDCSKF

tDCSO

tDCSOF
tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

tLADLY

tLAPLS

SCK0

SCK0

SO0

SO0
CS0

SCK0

SCK0

SI0

SI0

SO0

LAT0

LAT0

Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
Latch output mode

(SCK0 = output mode)
Latch output mode

(SCK0 = output mode)

ns

ns

ns

ns
ns

Symbol Pin Min.

1.5tsys + 100

1.5tsys + 100

1.5tsys + 100

1.5tsys + 100

tsys + 150

2tsys + 200

8000/fc

tsys + 90

4000/fc – 25

50

100

tsys + 100

50

tKCY

tKCY – 10

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns

ns

tsys + 100

50

tKCY + 50

tKCY + 50

Max. UnitConditions

SCK0 ↑ → LAT0
output delay time

LAT0 data pulse width

– 15 –

CXP845F60

SCK0

0.2V

DD

0.8VDD

tWHCS

tDCSK

tDCSKF

0.8VDD

0.2VDD

0.8VDD

tKCY

tKL tKH

0.8VDD

0.2VDD

SI0

t

SIK

Input

data

t

DCSO tKSO tDCSOF

Output

data

0.8V

DD

0.2VDD

SO0

CS0

tKSI

tLAPLS

LAT0

tLADLY

0.8VDD

0.8VDD

0.8VDD

Fig. 4. Serial transfer CH0 timing

– 16 –

CXP845F60

(3) Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)

Item

SCK1 cycle time

tKCY

SCK1

Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode

500

8000/fc

200

4000/fc – 25

50
100
100

50

100

50

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

SCK1

SI1

SI1

SO1

tKH
tKL

tSIK

tKSI

tKSO

SCK1 High, Low level
width

SI1 input setup time
(for SCK1 ↑)

SI1 input hold time
(for SCK1 ↑)

SCK1 ↓ → SO1 delay time

Symbol Pin Conditions Min. Max. Unit

Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.

0.2VDD

0.8VDD

tKL tKH

SO1

tKCY

tSIK

tKSI

0.2VDD

0.8VDD

tKSO

0.2VDD

0.8VDD
Output data

Input data

SI1

SCK1

Fig. 5. Serial transfer CH1 timing

– 17 –

CXP845F60

Conversion time
Sampling time
Reference input voltage
Analog input voltage

tCONV
tSAMP

VREF
VIAN

VZT

∗1

VFT

∗2

IREF

AVREF
AN0 to AN7

Ta = 25°C
VDD = AVREF = 5.0V
VSS = AVSS = 0V

Operation mode
Sleep mode

Stop mode

Linearity error
Zero transition voltage
Full-scale transition

voltage

Resolution

AVREF current

AVREF

IREFS

µs
µs

V
V

VDD

AVREF

1.0

mA

10 µA

0.6

27/fADC

∗3

6/fADC

∗3

VDD – 0.5

0

Item Symbol Pin Conditions Min. Typ. Max. Unit

Bits

(4) A/D converter characteristics

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference)

8

LSB

70 mV

5030

10

4970

–10

4910 mV

±4

Analog input

Linearity error

V

FTVZT

00h

01h

FEh

FFh

Digital conversion value

∗1

VZT: Value at which the digital conversion value changes

from 00H to 01H and vice versa.

∗2

VFT: Value at which the digital conversion value changes

from FEH to FFH and vice versa.

∗3

fADC indicates the values below due to the contents of bit 6
(CKS) of the A/D control register (ADC: 00F9H).

fADC = fc (CKS = "0"), fc/2 (CKS = "1")
However, the selection for fADC = fc (CKS = "0") is limited in
the clock range of fc = 1 to 14MHz (VDD = 4.5 to 5.5V).

Fig. 6. Definition of A/D converter terms

– 18 –

CXP845F60

External interruption
High, Low level width

Reset input Low level width

INT0
INT1
INT2
INT3
NMI

RST

1

32/fc

µs

µs

Item Symbol Pin Conditions Min. Max. Unit

tIH
tIL

tRSL

(5) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

0.2VDD

0.8VDD

tIH tIL

INT0
INT1
INT2
INT3
NMI
(Specifies NMI only for
the falling edge.)

tIL tIH

0.2VDD

0.8VDD

Fig 7. Interruption input timing

tRSL

0.2VDD

RST

Fig. 8. RST input timing

Power supply rise time
Power supply cut-off time

VDD

0.05
1

50

ms
ms

Item Symbol Pin Conditions Min. Max. Unit

tR
tOFF

Power-on reset
Repetitive power-on reset

(6) Power-on reset

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)

VDD

tR tOFF

0.2V

0.2V

4.5V

Turn the power on smoothly.

Fig. 9. Power-on reset

– 19 –

CXP845F60

Appendix

C1

A

EXTAL

XTAL

C2

Rd

A

EXTAL

XTAL

(i) Main clock

A

EXTAL

XTAL

C1 C2

Rd

(ii) Main clock

∗

1

Models with the built-in ground capacitance (C1, C2).

Manufacturer

MURATA
MFG
CO., LTD.

TDK
CORPORATION.

KINSEKI LTD.

Model

CSA8.00MTZ
CSA10.0MTZ
CSA12.00MTZ
CST8.00MTW

∗

1

CST10.0MT

∗

1

CST12.0MTW

∗

1

CSA16.00MXZ040
CST16.00MXZ0C1

∗

1

CSA20.00MXZ040
CSA24.00MXZ040
CSA28.00MXZ040
CCR20.0MC6

∗

1

CCR24.0MC6

∗

1

HC49/U-S
CX-11F

fc (MHz)

8.00

10.00

12.00

8.00

10.00

12.00

16.00

16.00

20.00

24.00

28.00

20.00

24.00

28.00

28.00

30

5
5

OPEN

3

3
16
16

1

1

30

5
5

OPEN

3

3
16
16

1

1

0

0
0
0
0
0
0

0
220
220

C1 (pF) C2 (pF)

Rd (Ω)

Circuit
example

(i)

(ii)

(i)

(ii)

(i)

(ii)

(i)

Selection Guide

CXP845F60Q-1-

Fig. 10. SPC700 Series recommended oscillation circuit

Mask
Package
ROM capacitance
Reset pin pull-up resistor
Power-on reset circuit

Existent/Non-existent

100-pin plastic QFP

40K bytes

48K bytes

Flash EEPROM 60K bytes

Existent/Non-existent

Existent
Existent

Option item

100-pin plastic QFP

AA

AA

AA

– 20 –

CXP845F60

Characteristics Curves

1

0.01

(10µA)

2 3 4 5 6 7 8 9

0.1

(100µA)

0.5

(500µA)

1

10

20

30

40

IDD vs. VDD

I

DD

– Supply current [mA]

(fc = 28MHz, Ta = 25˚C, Typical)

IDD vs. fc

(VDD = 5V, Ta = 25˚C, Typical)

40

0 10 20 30

50

20

30

10

0

fc – System clock [MHz]V

DD – Supply voltage [v]

I

DD

– Supply current [mA]

Stop mode

Sleep mode

1/2 dividing mode
1/4 dividing mode

1/16 dividing mode

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

Sleep mode

– 21 –

CXP845F60

Writing to Flash EEPROM

The CXP845F60 contains the 60K bytes of flash EEPROM. There are two methods to write to the flash
EEPROM; off-board write and on-board write.
The on-board write supports boot mode and user programming mode. Rewriting at the room temperature is
recommended.

1. Off-board write

In order to execute the off-board write, the microcomputer is attached on a conversion adaptor and the adaptor
is inserted in the socket of the SFP-1 (flash memory programmer) or NICE-SPC700R. (See Fig. 11.)
See the operation manuals for the operation methods of the SFP-1 and NICE-SPC700R. (Mitec SYSTEMS,
Inc. manufactures and sells the SFP-1 and NICE-SPC700R.)

Conversion adaptor

Flash memory programmer SFP-1

Fig. 11. Off-board write (when writing by using SFP-1)

2. On-board write

This is performed with the microcomputer mounted on the board. The CXP845F60 supports boot mode and
user programming mode.
In boot mode, write is performed through the communication with the SFP-1 as shown in Fig. 12.

User board

CXP845F60

SIO communication cable (8 pins)

Flash memory programmer SFP-1

In user programming mode, write is performed in microcomputer mode (normal operation mode) by the
communication method (SIO, I/O, etc.) according to the user's application. See the guide of the CXP845F60
write for actual use.

Fig. 12. On-board write boot mode

– 22 –

CXP845F60

When the on-board write is performed, the pins and flash mode register (FMOD: 01F4h, 0FF0h) should be set
as follows.

RST

Pins

Mode

Boot mode

TETA

Low fixed

TETB

High output

TETC

High fixed

PWE

Low fixed

SO1
SI1
SCK1

RST

V

SS

VDD

TETC
TETB
TETA

When normal
operation

Switching circuit

In boot mode

Reset
circuit

User circuit

When normal
operation

Switching circuit

In boot mode

Switched to boot
mode for low level

Switched to boot
mode for low level

Cut off the connection to other circuits
during the flash EEPROM rewrite.

∗1

AMP CT connector
175489-8

AMP CT receptacle
173977-8

VSS

SO1

SI1

SCK1

RST

V

DD

VSS
SEL

GND

SI

SO
SCK
RES

VIN

GND

Vpp

Flash MCU

PWE

Fig. 13. Connection example for boot mode

1
2
3
4
5
6
7
8

4.7kΩ pull-up
Open drain, 4.7kΩ pull-up
Open drain, 4.7kΩ pull-up
Open drain, 4.7kΩ pull-up

4.7kΩ pull-up

GND
SI
SO
SCK
RST
VIN
GND
Vpp

Connector for SFP-1
(AMP CT receptacle 173977-8)

Symbol

Remarks

Connector for user board
(AMP CT connector 175489-8)

←
→

←→

→
←

→

GND
SO1
SI1
SCK1
RST
VDD
GND
PWE

Remarks

Pull-up in the microcomputer (mask option)

Pull-up in the microcomputer

Pin
No.

Signal
direction

Symbol

∗1

The Vpp signal for the SFP-1 is pulled down with 4.7kΩ. Connecting cable permits writing when PWE pin is
fixed at low level. Also, it can be used as select signal of the switching circuit.

∗1

FLMOD bit is set to "1" automatically in boot mode.

FMOD resister

FLMOD bit

1

∗1

1

User programming
mode

On­board
write

High level X X X

X: don't care

– 23 –

CXP845F60

Package Outline Unit: mm

PACKAGE STRUCTURE

SONY CODE

EIAJ CODE

JEDEC CODE

QFP-80P-L01

∗QFP080-P-1420-A

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN
SOLDER PLATING
COPPER / 42 ALLOY

1.6g

23.9 ± 0.4

20.0 – 0.1

+ 0.4

1

80

65

64

41

40

25

24

0.8

0.35 – 0.1

+ 0.15

14.0 – 0.1

+ 0.4

17.9 ± 0.4

16.3

0.1 – 0.05

+ 0.2

2.75 – 0.15

+ 0.35

0.8 ± 0.2

0.15 – 0.05

+ 0.1

80PIN QFP (PLASTIC)

M

0.12

0.15

0° to 10°

DETAIL A

A