Page 1
CMOS 8-bit Single-chip Microcomputer
Description
The CXP853P40A are a highly integrated microcomputers composed of a 8-bit CPU, PROM, RAM,
and I/O ports. These chips feature many other highperformance circuits in a single-chip CMOS design,
including an A/D converter, serial interface,
timer/counter, time-base timer, vector interrupt, onscreen display function, I2C bus interface, PWM
generator, remote control receiver, HSYNC counter,
power supply frequency counter, and watchdog timer.
Also, this IC provides power-on reset and sleep
functions. The designers have ensured low power
consumption for these powerful microcomputers.
The CXP853P40A is the one-chip PROM version
of the CXP85340A with on-chip mask ROM,
providing the function of being able to write directly
into the program. Furthermore, because of the OSD
character ROM can also be written directly into, it is
suitable for evaluation use during system
development and for small quantity production.
Features
• A wide instruction set (213 instructions) which covers various of data
— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction
• Minimum instruction cycle 1µs/4MHz (4MHz verison)
0.5µs/8MHz (8MHz verison)
• Incorporated PROM capacity 40K bytes (For program)
6.75K bytes (For OSD)
• Incorporated RAM capacity 576 bytes
• Peripheral funcitons
— On-screen display function 12 × 18 dots, 256 types, 15 colors, 12 lines of 21 characters
Black frame output half blanking, shadow, background color on full
screen/half blanking
Double scanning mode supported, jitter elimination circuit
— I2C bus interface
— PWM output 14 bits, 1 channel
8 bits, 8 channels
— Remote control receiver circuit 8-bit pulse measuring counter, 6-stage FIFO
— A/D converter 8-bit, 4 channels, successive approximation system
(conversion time of 40µs/4MHz, 8MHz)
— HSYNC counter
— Power supply frequency counter
— Watchdog timer
— Serial I/O 8-bit synchronized
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer
• Interruption 14 factors, 14 vectors, multiple interrupt possible
• Standby mode Sleep
• Package 64-pin plastic SDIP/QFP
Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components
– 1 –
E93Z19A7Z-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP853P40A
64 pin SDIP (PIastic) 64 pin QFP (PIastic)
in an I2C system, provided that the system conforms
to the I2C Standard Specifications as defined by
Philips.
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CXP853P40A
ON SCREEN DISPLAY
SERIAL I/O
TIMER/COUNTER
REMOCON FIFO
A/D CONVERTER
I
2
C
INTERFACE UNIT
WATCHDOG TIMER
14BIT PWM
8 BIT PWM
8CH
CLOCK GEN./
SYSTEM CONTROL
RAM
576 BYTES
SPC700
CPU CORE
PROM
40K BYTES
PRESCALER/
TIME BASE TIMER
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F
2
2
V
SS
V
DD
MP
RST
XTAL
EXTAL
PD0/INT2
PE1/INT1
PE0/INT0
PF0/PWM0
to
PF7/PWM7
INTERRUPT CONTROLLER
PE6/PWM
PA0 to PA7
PB0 to PB7
PC0 to PC7
PD0 to PD7
PE0 to PE5
PE6 to PE7
PF0 to PF7
XLC
EXLC
R
G
B
I
YS
YM
PA7/HSYNC
PA6/VSYNC
PD3/SI
PD2/SO
PD1/SCK
PD7/EC
PE7/TO
PD6/RMC
PD4/HSI
PD5/ACI
PE2/AN0
to
PE5/AN3
PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1
HSYNC COUNTER
AC TIMER
Vpp
Block Diagram
Page 3
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CXP853P40A
VDD
Vpp
V
SS
MP
PF0/PWM0
PF1/PWM1
PF2/PWM2
PF3/PWM3
BLK
R
G
B
VSYNC
HSYNC
EXLC
XLC
PE0/INT0
PE1/INT1
PE2/AN0
PE3/AN1
PE4/AN2
PE5/AN3
PE6/PWM
PE7/TO
RST
EXTAL
XTAL
PD0/INT2
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
61
63
64
62
53
54
55
56
57
58
59
60
PF4/PWM4/SCL0
PF5/PWM5/SCL1
PF6/PWM6/SDA0
PF7/PWM7/SDA1
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7/EC
PD6/RMC
PD5/ACI
PD4/HSI
PD3/SI
PD2/SO
PD1/SCK
V
SS
4
5
6
7
8
9
10
2
3
1
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin Assignment 1 (Top View) 64 pin SDIP Package
Note) 1. Vpp (Pin 63) is always connected to VDD.
2. Vss (Pins 32 and 62) are both connected to GND.
3. MP (Pin 61) is always connected to GND.
Page 4
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CXP853P40A
PF3/PWM3
BLK
R
G
B
VSYNC
HSYNC
EXLC
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
61
6364
62
53
54
55
56
57
58
59
60
PF4/PWM4/SCL0
PF5/PWM5/SCL1
PF6/PWM6/SDA0
PF7/PWM7/SDA1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7/EC
4
5
6
7
8
9
10
2
3
1
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PA2
PA3
PA4
PA5
PA7
V
SS
PA6
V
DD
Vpp
MP
PF0/PWM0
PF2/PWM2
PF1/PWM1
PA1
PA0
PD6/RMC
PD5/ACI
PD4/HSI
PD3/SI
PD1/SCK
V
SS
PD2/SO
PD0/INT2
XTAL
EXTAL
RST
PE6/PWM
PE7/TO
31
32
XLC
PE0/INT0
PE1/INT1
PE2/AN0
PE3/AN1
PE4/AN2
PE5/AN3
Pin Assignment 2 (Top View) 64 pin QFP Package
Note) 1. Vpp (Pin 56) is always connected to VDD.
2. Vss (Pins 26 and 58) are both connected to GND.
3. MP (Pin 55) is always connected to GND.
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CXP853P40A
(Port A)
Single bit selectable 8-bit I/O port.
(8 pins)
(Port B)
Single bit selectable 8-bit I/O port.
(8 pins)
(Port C)
Single bit selectable 8-bit I/O port.
(8 pins)
(Port D)
Single bit selectable
8-bit I/Oport.
12mA sink current
drive possible.
(8 pins)
(Port E)
8-bit port, lower
6 bits for input,
upper 2 bits for
output.
(8 pins)
(Port F)
8-bit output port
with large current
(12mA) N-ch open
drain output.
Lower 4 bits middle
voltage tolerance
(12V), upper 4 bits
5V suppression.
(8 pins)
CRT display 6-bit output pin.
Pin Description
Symbol
PA0 to PA5
PA6/VSYNC
PA7/HSYNC
PB0 to PB7
PC0 to PC7
PD0/INT2
PD1/SCK
PD2/SO
PD3/SI
PD4/HSI
PD5/ACI
PD6/RMC
PD7/EC
PE0/INT0
PE1/INT1
PE2/AN0
to
PE5/AN3
PE6/PWM
PE7/TO
PF0/PWM0
to
PF3/PWM3
PF4/PWM4/
SCL0
PF5/PWM5/
SCL1
PF6/PWM6/
SDA0
PF7/PWM7/
SDA1
R, G, B, I, YS, YM
I/O
I/O/Input
I/O/Input
I/O
I/O
I/O/Input
I/O/I/O
I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input
Input/Input
Input/Input
Output/Output
Output/Output
Output/Output
Output/Output/
I/O
Output/Output/
I/O
Output
I/O Description
CRT display vertical synchronization signal input pin.
CRT display horizontal synchronization signal input pin.
Input pin for external interrupt request.
Active on falling edge.
Serial clock I/O pin.
Serial data output pin.
Serial data input pin.
HSYNC counter input pin.
Power supply frequency counter input pin.
Remote control receiver circuit input pin.
External event timer/counter input pin.
Input pin for external interrupt request.
Active on falling edge.
(2 pins)
Analog input pin for A/D converter.
(4 pins)
14-bit PWM output pin.
(CMOS output)
Square wave output for timer 1.
(50% duty cycle)
8-bit PWM output pin.
(8 pins)
I2C bus interface transfer clock I/O pin.
I2C bus interface transfer data I/O pin.
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CXP853P40A
Symbol
EXLC
XLC
EXTAL
XTAL
RST
MP
VDD
Vpp
Vss
Input
Output
Input
Output
I/O
Input
CRT display clock oscillator I/O pin.
Oscillator frequency is determined by external L, C circuit.
System clock oscillator crystal connection pin. When using an external
clock, input to EXTAL pin and leave XTAL pin open.
"L" level active system reset. This pin also acts as an I/O pin during
power up. While internal power-on reset function is talking place a
"L" level is output. (Mask option)
Test mode input pin. Must be connected to GND.
Positive supply voltage pin.
Positive power supply pin for incorporated PROM writing.
Connect to VDD for normal operation.
GND. Both Vss pins should be connected to common GND.
I/O Description
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CXP853P40A
A
Input/Output Circuit Formats for Pins
Port A
Port B
Port C
Port A
Port D
22 pins
2 pins
6 pins
Hi-Z
Hi-Z
Hi-Z
Pin
When reset
Circuit format
PA0 to PA5
PB0 to PB7
PC0 to PC7
PA6/VSYNC
PA7/HSYNC
PD0/INT2
PD3/SI
PD4/HSI
PD5/ACI
PD6/RMC
PD7/EC
Data bus
Data bus
Port A data
Port B data
Port C data
AA
Port A I/O direction
Port B I/O direction
Port C I/O direction
RD
(Port A, B, C)
Port A data
Port A I/O direction
RD (Port A)
Input protection
IP
circuit
Input protection
IP
circuit
VSYNC
HSYNC
Port D I/O direction
Data bus
RD (Port D)
INT2, SI, HSI, ACI, RMC, EC
Port D data
Schmitt input
Input polarity
Schmitt input
Large current
source 12mA
IP
Page 8
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CXP853P40A
Port D
Port E
2 pins
2 pins
4 pins
2 pins
Pin
When reset
Circuit format
PE0/INT0
PE1/INT1
Port E
Port E
Hi-Z
Hi-Z
Hi-Z
High level
PE2/AN0
to
PE5/AN3
PD1/SCK
PD2/SO
PE6/PWM
PE7/TO
Data bus
SCK or SO
Output enable
Port D I/O direction
RD (Port D)
SCK only
Port D data
Schmitt input
IP
Schmitt input
RD (Port E)
Large current
source 12mA
IP
(To interrupt circuit)
Data bus
TO, PWM
Port E data
Port E selection
Input multiplexer
IP
RD (Port E)
To A/D converter
Data bus
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CXP853P40A
Port F
Port F
4 pins
4 pins
6 pins
2 pins
Pin
When reset
Circuit format
PF4/PWM4/
SCL0
PF5/PWM5/
SCL1
PF6/PWM6/
SDA0
PF7/PWM7/
SDA1
Hi-Z
Hi-Z
Hi-Z
Oscillation
halted
R
G
B
I
YS
YM
PF0/PWM0
to
PF3/PWM3
EXLC
XLC
R, G, B, I, YS, YM
To output polarity register
Writing data to port register brings output
from high impedance to active
Output polarity
Oscillator control
EXLC
IP
CRT display clock
IP
XLC
PWM
Port F data
Port F selection
SCL, SDA
I2C output enable
Port F data
Port F selection
SCL, SDA
2
(To I
C circuit)
PWM
Schmitt input
12V voltage torelance
Large current
source 12mA
Large current
source 12mA
IP
BUS SW
2
To other I
C pins
Page 10
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CXP853P40A
2 pins
1 pin
Pin
When reset
Circuit format
RST
Oscillation
Low level
EXTAL
XTAL
IP
EXTAL
XTAL
• Diagram indicates circuit
composition during oscillation
• Feedback resistor is disconnected
during stop
Schmitt input
Pull-up resistor
From power-on reset circuit
(Mask option)
Mask option
OP
Page 11
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CXP853P40A
∗1
VIN and VOUT should not exceed VDD + 0.3V.
∗2
The large current drivetransistor for the PD and PF ports is a N-ch transistor.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
Supply voltage
Input voltage
Output voltage
Medium voltage tolerance output voltage
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
VDD
Vpp
VIN
VOUT
VOUTP
IOH
∑IOH
IOL
IOLC
∑IOL
Topr
Tstg
PD
–0.3 to +7.0
–0.3 to +13.0
–0.3 to +7.0
∗1
–0.3 to +7.0
∗1
–0.3 to +15.0
–5
–50
15
20
130
–10 to +75
–55 to +150
1000
600
V
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
mW
Incorporated PROM
Pins PF0 to PF3
Total of all output pins
Excludes large current output
Large current output
∗2
Total of all output pins
SDIP
QFP
Item Symbol Ratings Unit Remarks
Absolute Maximum Ratings (Vss = 0V reference)
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CXP853P40A
Supply voltage
High level
input voltage
Low level
input voltage
Operating temperature
5.5
5.5
5.5
VDD
VDD
VDD + 0.3
0.3VDD
0.2VDD
0.4
+75
V
V
V
V
V
V
V
V
V
V
°C
Item Symbol Min. Max. Unit Remarks
4.5
3.5
2.5
0.7VDD
0.8VDD
VDD – 0.4
0
0
–0.3
–10
Vpp
VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr
Guaranteed range during operation
Guaranteed range for low speed data
∗1
Guaranteed data hold operation range during stop
∗5
I2C Schmitt input included
∗2
CMOS Schmitt input
∗3
EXTAL pin
∗4
I2C Schmitt input included
∗2
CMOS Schmitt input
∗3
EXTAL pin
∗4
VDD
∗1
Rating for 1/16 frequency mode and sleep mode.
∗2
Normal input port (All pins of PA, PB, PC, PE2 to PE5), PF4 to PF7 pins.
∗3
Includes PD0/INT2, PD1/SCK, PD2, PD3/SI, PD4/HSI, PD5/ACI, PD6/RMC, PD7/EC, PE0/INT0, PE1/INT1,
HSYNC, VSYNC, RST pins.
∗4
It specifies only when the external clock is input.
∗5
Vpp and VDD should be set to the same voltage.
Recommended Operating Conditions (Vss = 0V reference)
Vpp = VDD
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CXP853P40A
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 3.0mA
VDD = 4.5V, IOL = 4.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, IOL = 12.0mA
High level
output voltage
Low level
output voltage
Input current
I/O leakage current
Open drain output
leakage current
(N-ch Tr off case)
I2C bus switch
connection impedance
(output Tr off case)
Supply current
Input capacitance
4.0
3.5
11
∗2
0.6
∗2
0.8
∗3
—
10
—
3
∗2
3
∗3
—
20
µA
pF
50
10
120
30
∗2
17
∗3
40
∗3
mA
mA
µA
µA
Ω
0.4
0.6
1.5
0.4
0.6
40
–40
–400
±10
V
V
V
V
V
µA
µA
µA
µA
0.5
–0.5
–1.5
V
V
PA to PD, PE6, PE7,
R, G, B, I, YS, YM
PA to PD, PE6, PE7,
R, G, B, I, YS, YM,
PF0 to PF3, RST
PD, PF
PF4 to PF7
(SCL0, SCL1,
SDA0, SDA1)
EXTAL
RST
PA to PE, HSYNC,
VSYNC, R, G, B, I,
YS, YM
PF0 to PF3
PF4 to PF7
SCL0: SCL1
SDA0: SDA1
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V,
VI = 0, 5.5V
VDD = 5.5V, VOH = 12.0V
VDD = 5.5V, VOH = 5.5V
VDD = 4.5V
VSCL0 = VSCL1 = 2.25V
VSDA0 = VSDA1 = 2.25V
VDD
∗1
Operating mode
(1/2, 1/4 clock rate)
4MHz, 8MHz crystal
oscillator
(C1 = C2 = 22pF)
All output pins open
Stop mode
∗4
Sleep mode
Pins other than
VDD and Vss
1MHz clock
0V other than the measure pins
Item
Symbol
Pin Condition Min. Typ. Max. Unit
VOH
VOL
IIZ
ILOH
RBS
IDD
IDDSL
IDDST
CIN
IIHE
IIHL
IILR
Electrical Characteristics
DC Characteristics (Ta = –10 to +75°C, Vss = 0V reference)
∗1
Rating applies only if OSD oscillator is halted.
∗2
Oscillator clock 4MHz version
∗3
Oscillator clock 8MHz version
∗4
This device does not enter the stop mode.
Page 14
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CXP853P40A
AC Characteristics
(1) Clock timing
∗1
tsys indicates one of three values according to the contents of the clock control register (address : 00FEH)
upper 2 bits (CPU clock selection)
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
∗2
Oscillator clock 4MHz version
∗3
Oscillator clock 8MHz version
System clock frequency
System clock input
pulse width
System clock
rise and fall times
Event counter input
clock pulse widtth
Event counter input clock
rise and fall times
fC
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
XTAL
EXTAL
EXTAL
EXTAL
EC
EC
MHz
ns
ns
ns
ms
Item Symbol Pin Condition Min. Max. Unit
Fig. 1, Fig. 2
Fig. 1, Fig. 2
External clock drive
Fig 1, Fig 2
External clock drive
Fig. 3
Fig. 3
3.5
∗2
7
∗3
100
∗2
50
∗3
tsys + 50
∗1
4.5
9
200
20
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Fig. 1. Clock timing
EXTAL
t
XH tXLtCF tCR
0.4V
V
DD – 0.4V
1/fc
Fig. 2. Clock applied condition
A
A
Crystal oscillator
Ceramic oscillator
EXTAL
XTAL
External clock
EXTAL
XTAL
OPEN
C
1 C2
Fig. 3. Event count clock timing
EC
t
EH tELtEF tER
0.2VDD
0.8VDD
AAA
AAA
Page 15
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CXP853P40A
(2) Serial transfer (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
SCK cycle time
tKCY
SCK
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
1000
8000/fc'
∗1
400
4000/fc' – 50
∗1
100
200
200
100 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK
SI
SI
SO
tKH
tKL
tSIK
tKSI
tKSO
SCK
High and Low level widths
SI input setup time
(referenced to SCK ↑)
SI input hold time
(referenced to SCK ↑)
SCK ↓ → SO delay time
Symbol Pin Condition Min. Max. Unit
Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
∗1
The value of fc' varies as shown below depending on the specification of oscillation clock option.
4MHz version ... fc' = fc
8MHz version ... fc' = fc/2
Fig. 4. Serial transfer timing
0.2VDD
0.8VDD
tKL tKH
SO
tKCY
tSIK
tKSI
0.2VDD
0.8VDD
tKSO
0.2VDD
0.8VDD
Output data
Input data
SI
SCK
Page 16
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CXP853P40A
External interrupt
High and Low level widths
Reset input low level width
INT0 to INT2
RST
1
8/fc'
∗1
µs
µs
Item Symbol Pin
Condition Min. Max. Unit
tIH
tIL
tRSL
Power supply rise time
Power supply cutt-off time
tR
tOFF
VDD
Power-on reset
Repeated power-on reset
0.05
1
50 ms
ms
Item Symbol Pin Condition Min. Max. Unit
(3) Interrupt, Reset input (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
(4) Power-on reset
Power-on reset (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
0.2VDD
0.8VDD
tIH tIL
INT0 to INT2
(falling edge)
0.2V
0.2V
4.5V
VDD
tR tOFF
The power supply should rise smoothly.
Fig. 5. Interrupt input timing
tRSL
0.2VDD
RST
Fig. 6. RST input timing
Fig. 7. Power-on reset
∗1
The value of fc' varies as shown below depending on the specification of oscillation clock option.
4MHz version ... fc' = fc
8MHz version ... fc' = fc/2
Page 17
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CXP853P40A
Resolution
Linearity error
Zero transition
voltage
Full-scale transition
voltage
Conversion time
Sampling time
Analog input voltage
VZT
∗1
VFT
∗2
tCONV
tSAMP
VIAN
AN0 to AN3
Ta = 25°C
VDD = 5.0V
Vss = 0V
–10
4930
160/fc'
∗3
12/fc'
∗3
0
70
5050
8
±3
150
5120
VDD
Bits
LSB
mV
mV
µs
µs
V
Item Symbol Pin Condition Min. Typ. Max. Unit
(5) A/D converter characteristics (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Linearity error
VZT VFT
Analog input
FF
H
FEH
01H
00H
Digital conversion value
Fig. 8. Definitions for A/D converter terms
∗1
VZT: Digital conversion values change between 00H←→01H.
∗2
VFT: Digital conversion values change between
FEH←→FFH.
∗3
The value of fc' varies as shown below depending on the
specification of oscillation clock option.
4MHz version ... fc' = fc
8MHz version ... fc' = fc/2
Page 18
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CXP853P40A
(6) I2C bus timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
SCL clock frequency
Bus free time before starting transfer
Hold time for starting transfer
Clock Low level width
Clock High level width
Setup time for repetitive transfers
Data hold time
Data setup time
SDA, SCL rise time
SDA, SCL fall time
Setup time for transfer completion
fSLC
tBUF
tHD; STA
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tR
tF
tSU; STO
SCL
SDA, SCL
SDA, SCL
SCL
SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
0
4.7
4.0
4.7
4.0
4.7
0
∗1
250
4.7
100
1
300
kHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
Symbol Pin Condition Min. Max. Unit
∗1
Since for part of data hold time SCL rise time (max: 300ns) is not considered , allow at least 300ns.
Fig. 9. I2C bus transfer data timing
PSt
t
SU; STO
tSU; STA
tHD; STA
tSU; DATtHIGHtHD; DAT
tFtR
tLOW
tHD; STA
SP
t
BUF
SDA
SCL
Fig. 10. I2C device recommended circuit
I2C
device
I2C
device
RS RS RS RS RP RP
SDA0
(or SDA1)
SCL0
(or SCL1)
• A pull-up resistor (RP) must be connected to SDA0 (or SDA1), and SCL0 (or SCL1).
• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce spike
noise caused by CRT flashover.
Page 19
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CXP853P40A
(7) OSD (On Screen Display) timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
OSD clock frequency
HSYNC pulse width
HSYNC afterwrite
rise and fall times
VSYNC afterwrite
rise and fall times
fOSC
tHWD
tHCG
tVCG
EXLC
XLC
HSYNC
HSYNC
VSYNC
Fig. 12
Fig. 11
Fig. 11
Fig. 11
4
1.2
7
∗1
14
∗2
200
1.0
4
1.2
MHz
µs
ns
µs
11
∗1
16
∗2
200
1.0
Symbol Pin Condiiton Unit
Shadow Existent
Min. Max. Min. Max.
Shadow Non-existent
∗1
Oscillator clock 4MHz version
∗2
Oscillator clock 8MHz version
Fig. 11. OSD timing
0.8VDD
0.2VDD
tHCG
tHWD
HSYNC
For OPOL register (01FAH)
bit 7 at “0”
0.8VDD
0.2VDD
tVCG
VSYNC
For OPOL register (01FAH)
bit 6 at “0”
Fig. 12. LC oscillator circuit connection
L
C
2
C1
EXLC XLC
Page 20
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CXP853P40A
Supplement
A
EXTAL
XTAL
C
1 C2
Rd
(i)
A
EXTAL
XTAL
C
1 C2
Rd
(ii)
Manufacturer
MURATA MFG
CO., LTD.
KINSEKI LTD.
Model
CSA4.00MG
CSA4.19MG
CSA8.00MTZ
CST4.00MGW
∗
CST4.19MGW
∗
CST8.00MTW
∗
HC-49/U03
HC-49/U(-S)
fc (MHz)
4.00
4.19
8.00
4.00
4.19
8.00
4.00
4.19
8.00
4.00
4.19
8.00
30
12
30
12
0
0
C1 (pF) C2 (pF) Rd (Ω)
Circuit
Example
(i)
(ii)
(i)
27
27 0 (i)
∗
Indicates types with on-chip grounding capacitors (C1 and C2).
Product List
RIVER ELETEC
CORPORATION
Option item
Package
PROM capacitance
Reset pin pull-up resistor
Power-on reset circuit
Font data
Oscillator clock
64-pin plastic
SDIP/QFP
24K/32K/40K bytes
Existent/Non-existent
Existent/Non-existent
User specified
4MHz/8MHz
64-pin plastic
SDIP/QFP
PROM 40K bytes
Existent
Existent
User specified (PROM)
∗1
4MHz
64-pin plastic
SDIP/QFP
PROM 40K bytes
Existent
Existent
User specified (PROM)
∗1
8MHz
Mask
CXP853P40AS-2CXP853P40AQ-2-
∗1
The font data for the one-time PROM version is operated in the same way as the program writing.
CXP853P40AS-3CXP853P40AQ-3-
Fig. 13. Recommended oscillation circuit
AAA
AAA
Page 21
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CXP853P40A
Fig. 14. Characteristic curves
Parameter curve for OSD oscillator L vs. C
(Analytically calculated value)
C1, C2 – Capacitance [pF]
L – Inductance
[µH]
IDD vs. VDD
(fC = 4MHz, Ta = 25°C, Typical)
V
DD – Supply voltage [V]
I
DD
– Supply current
[mA]
IDD vs. VDD
(fC = 8MHz, Ta = 25°C, Typical)
V
DD – Supply voltage [V]
I
DD
– Supply current
[mA]
IDD vs. fC
(VDD = 5V, Ta = 25°C, Typical)
f
C – System clock [MHz]
I
DD
– Supply current
[mA]
100
0 50 100
5.0MHz
10
1
6.5MHz
13.0MHz
15
10
1
0.1
2 3 4 5 6
20
10
1
0.1
2 3 4 5 6
20
15
5 101
10
5
0
fOSC = C = C1//C2
1
2π √ LC
Sleep mode
Sleep mode
1/4 frequency mode
1/2 frequency mode
1/16 frequency mode
1/2 frequency mode
1/4 frequency mode
1/16 frequency mode
1/2 frequency mode
1/4 frequency mode
1/16 frequency mode
Sleep mode
Page 22
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CXP853P40A
Package Outline Unit: mm
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
JEDEC CODE
SDIP-64P-01
42 ALLOY
SOLDER PLATING
EPOXY RESIN
64PIN SDIP (PLASTIC)
SDIP064-P-0750
57.6 – 0.1
+ 0.4
64
33
1 32
1.778
19.05
17.1 – 0.1
+ 0.3
0° to 15°
0.25 – 0.05
+ 0.1
0.5 MIN
4.75 – 0.1
+ 0.4
3.0 MIN
0.5 ± 0.1
0.9 ± 0.15
8.6g
SONY CODE
EIAJ CODE
JEDEC CODE
23.9 ± 0.4
20.0 – 0.1
0.4 – 0.1
+ 0.15
14.0 – 0.1
1
19
20
32
33
51
52
64
0.15 – 0.05
+ 0.1
2.75 – 0.15
16.3
0.1 – 0.05
+ 0.2
0.8 ± 0.2
M
0.2
0.15
+ 0.4
17.9 ± 0.4
+ 0.4
+ 0.35
64PIN QFP(PLASTIC)
QFP-64P-L01
QFP064-P-1420
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER/PALLADIUM
42/COPPER ALLOY
PACKAGE STRUCTURE
PLATING
1.5g
1.0
0° to10°
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