Datasheet CXP85340A, CXP85332A, CXP85324A Datasheet (Sony)

Description

The CXP85324A/85332A/85340A are a highly
integrated microcomputers composed of a 8-bit
CPU, ROM, RAM, and I/O ports. These chips feature
many other high-performance circuits in a single-chip
CMOS design, including an A/D converter, serial
interface, timer/counter, time-base timer, on-screen
display function, I2C bus interface, PWM output,
remote control reception circuit, HSYNC counter,
power supply frequency counter, and watchdog
timer.

Futhermore, the CXP85324A/85332A/85340A
series provides power-on reset and sleep functions
which enable to lower power consumption.

Features

• A wide instruction set (213 instructions) which covers various types of data

– 16-bit operation/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle 1µs at 4MHz (4MHz version)

0.5µs at 8MHz (8MHz version)

• Incorporated ROM capacity 24K bytes (CXP85324A)

32K bytes (CXP85332A)
40K bytes (CXP85340A)

• Incorporated RAM capacity 576 bytes

• Peripheral functions

– A/D converter 8-bit, 4-channel successive approximation method

(Conversion time of 40µs at 4MHz and 8MHz)
– Serial interface 8-bit clock sync type, 1 channel
– Timer 8-bit timer

8-bit timer/counter

19-bit time-base timer
– On screen display (OSD) function 12 × 18 dots, 256 character types, 15 character colors,

12lines of 21 characters,

black frame output/half blanking, shadow, background

color on full screen/half blanking,

double scanning, jitter elimination circuit
– I2C bus interface
– PWM output 14 bits, 1 channel

8 bits, 8 channels
– Remote control reception circuit 8-bit pulse measurement circuit, 6-state FIFO
– HSYNC counter
– Power supply frequency counter
– Watchdog timer

• Interruption 14 factors, 14 vectors, multi-interruption possible

• Standby mode SLEEP

• Package 64-pin plastic SDIP/QFP

• Piggyback/evaluator CXP85300A 64-pin ceramic PSDIP/PQFP

CXP85390 64-pin ceramic PSDIP (accommodates custom font)

Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.

– 1 –

CXP85324A/85332A/85340A

E93X37B86

CMOS 8-bit Single Chip Microcomputer

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

64 pin SDIP (PIastic) 64 pin QFP (PIastic)

Structure

Silicon gate CMOS IC

– 2 –

CXP85324A/85332A/85340A

ON SCREEN DISPLAY

SERIAL INTERFACE UNIT

8BIT TIMER/COUNTER 0

REMOCON FIFO

HSYNC COUNTER

AC TIMER

A/D CONVERTER

I

2

C BUS

INTERFACE UNIT

WATCH DOG TIMER

14BIT PWM

8 BIT PWM

8CH

CLOCK GENERATOR/

SYSTEM CONTROL

RAM

576 BYTES

SPC700

CPU CORE

ROM

24K/32K/40K

PRESCALER/

TIME BASE TIMER

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

2

2

V

SS

V

DD

MP

XTAL
EXTAL

RST

INT2
INT1
INT0

PWM0

to

PWM7

INTERRUPT

CONTROLLER

PWM

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE5

PE6 to PE7

PF0 to PF7

XLC

EXLC

R

G

B

I

YS

YM

HSYNC

VSYNC

SI

SO

SCK

EC

TO

RMC

HSI

ACI

AN0

to

AN3

SCL0

SCL1

SDA0

SDA1

8BIT TIMER 1

Block Diagram

– 3 –

CXP85324A/85332A/85340A

2
3
4

5
6
7
8
9

10

11

12

13

14
15
16
17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

1

40
39
38
37
36
35

34

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

63

64

61

62

HSYNC/PA7
VSYNC/PA6

PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4

PC3
PC2
PC1
PC0

EC/PD7

RMC/PD6

ACI/PD5
HSI/PD4

SI/PD3

SO/PD2

SCK/PD1

V

SS

VDD
NC
V

SS

MP
PF0/PWM0
PF1/PWM1
PF2/PWM2
PF3/PWM3
PF4/PWM4/SCL0
PF5/PWM5/SCL1
PF6/PWM6/SDA0
PF7/PWM7/SDA1
YM
YS
I
B
G
R
EXLC
XLC
PE0/INT0
PE1/INT1
AN0/PE2
AN1/PE3
AN2/PE4
AN3/PE5
PE6/PWM
PE7/TO
RST
EXTAL
XTAL
PD0/INT2

Pin Assignment (Top View) 64-pin SDIP

Note) 1. NC (Pin 63) is always connected to VDD.

2. Vss (Pins 32 and 62) are both connected to GND.

3. MP (Pin 61) is always connected to GND.

– 4 –

CXP85324A/85332A/85340A

Note) 1. NC (Pin 56) is always connected to VDD.

2. Vss (Pins 26 and 58) are both connected to GND.

3. MP (Pin 55) is always connected to GND.

Pin Assignment (Top View) 64-pin QFP

PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2

PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0

EC/PD7

2
3
4

5
6
7
8
9

10
11
12
13
14
15
16
17
18
19

1

PF3/PWM3
PF4/PWM4/SCL0
PF5/PWM5/SCL1
PF6/PWM6/SDA0
PF7/PWM7/SDA1
YM
YS
I
B

G
R
EXLC
XLC
PE0/INT0
PE1/INT1
AN0/PE2
AN1/PE3
AN2/PE4
AN3/PE5

40
39
38
37
36
35
34
33

41

42

43

44

45

46

47

48

49

50

51

PA2

PA3

PA4

PA5

PA6/VSYNC

PA7/HSYNC

V

SS

V

DD

NC

MP

PF0/PWM0

PF1/PWM1

PF2/PWM2

52

53

54

55

56

57

58

59

60

63

64

61

62

RMC/PD6

ACI/PD5

HSI/PD4

SI/PD3

SO/PD2

SCK/PD1

V

SS

INT2/PD0

XTAL

EXTAL

RST

TO/PE7

PWM/PE6

20

21

22

23

24

25

26

27

28

29

30

31

32

(Port A)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port D)
8-bit I/O port. I/O
can be set in a unit
of single bits.
12mA sink current
drive possible.
(8 pins)

(Port E)
8-bit port. Lower
6 bits are for inputs;
upper 2 bits are for
outputs.
(8 pins)

(Port F)
8-bit output port.
Large current
(12mA) N-ch open
drain output.
Lower 4 bits are
mid-voltage drive
(12V); upper 4 bits
are 5V drive.
(8 pins)

OSD display 6-bit output pin. (6 pins)

– 5 –

CXP85324A/85332A/85340A

Pin Description

Symbol
PA0 to PA5
PA6/VSYNC

PA7/HSYNC

PB0 to PB7

PC0 to PC7

PD0/INT2
PD1/SCK

PD2/SO
PD3/SI
PD4/HSI
PD5/ACI
PD6/RMC
PD7/EC

PE0/INT0
PE1/INT1

PE2/AN0

to
PE5/AN3

PE6/PWM
PE7/TO

PF0/PWM0

to
PF3/PWM3

PF4/PWM4/
SCL0
PF5/PWM5/
SCL1

PF6/PWM6/
SDA0
PF7/PWM7/
SDA1

R, G, B, I, YS, YM

I/O
I/O/Input

I/O/Input

I/O

I/O

I/O/Input
I/O/I/O

I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input

Input/Input

Input/Input

Output/Output
Output/Output

Output/Output

Output/Output/
I/O

Output/Output/
I/O

Output

I/O Description

OSD display vertical synchronization signal input pin.
OSD display horizontal synchronization signal input pin.

Input pin for external interruption request.
Active when falling edge.

Serial clock I/O pin.
Serial data output pin.
Serial data input pin.
HSYNC counter input pin.
Power supply frequency counter input pin.
Remote control reception circuit input pin.
External event input pin timer/counter.
Input pin for external interruption request.

Active when falling edge.
(2 pins)

Analog input pin for A/D converter.
(4 pins)

14-bit PWM output pin.
(CMOS output)

Timer/counter rectangular wave output pin.
8-bit PWM output pin.

(8 pins)

I2C bus interface transfer clock I/O pin.
(2 pins)

I2C bus interface transfer data I/O pin.
(2 pins)

– 6 –

CXP85324A/85332A/85340A

Symbol
EXLC
XLC
EXTAL
XTAL

RST

MP
NC
VDD
Vss

Input
Output
Input
Output

I/O

Input

OSD display clock oscillation I/O pin.
Oscillation frequency is determined by the external L and C.

Crystal connection pin for system clock oscillation. When using an external
clock, input to EXTAL pin and leave XTAL pin open.

System reset pin for active at low level. This pin becomes I/O pin, and
outputs low level at the power on with power-on reset function executed.
(Mask option)

Test mode input pin. Always connect to GND.
NC. Under normal operation, connect to VDD.
Positive supply voltage pin.
GND. Both Vss pins should be connected to common GND.

I/O Description

– 7 –

CXP85324A/85332A/85340A

Input/Output Circuit Formats for Pins

Port A
Port B
Port C

Port A

Port D

22 pins

2 pins

6 pins

Hi-Z

Hi-Z

Hi-Z

Pin When resetCircuit format

PA0 to PA5
PB0 to PB7
PC0 to PC7

PA6/VSYNC
PA7/HSYNC

PD0/INT2
PD3/SI
PD4/HSI
PD5/ACI

PD6/RMC
PD7/EC

Ports A, B, C data

Ports A, B, C direction

“0” when reset

Data bus

RD
(Ports A, B, C)

Port A data

Input protection

IP

circuit

Data bus

Data bus

Port A direction

RD (Port A)

VSYNC
HSYNC

“0” when reset

Port D data

Port D direction

“0” when reset

Schmitt input

Input multiplexer

“0” when reset

Schmitt input

IP

∗

IP

RD (Port D)

INT2, SI, HSI, ACI, RMC, EC

∗

Large current 12mA

– 8 –

CXP85324A/85332A/85340A

Port D

Port E

2 pins

2 pins

4 pins

2 pins

Pin When resetCircuit format

PE0/INT0
PE1/INT1

Port E

Port E

Hi-Z

Hi-Z

Hi-Z

High level

PE2/AN0

to

PE5/AN3

PD1/SCK
PD2/SO

PE6/PWM
PE7/TO

SCK or SO

Output enable

Data bus

Port D data

Port D direction

“0” when reset

RD (Port D)

SCK only

Port E function selection

Schmitt input

IP

“0” when reset

IP

Schmitt input

RD (Port E)

Input multiplexer

RD (Port E)

∗

∗

Large current 12mA

(Interrupt circuit)

Data bus

To A/D converter

Large current
source 12mA

IP

Data bus

TO, PWM

Port E data

“1” when reset

Port E function selection

“1” when reset

– 9 –

CXP85324A/85332A/85340A

Port F

Port F

4 pins

4 pins

6 pins

2 pins

Pin When resetCircuit format

PF4/PWM4/
SCL0
PF5/PWM5/
SCL1
PF6/PWM6/
SDA0
PF7/PWM7/
SDA1

Hi-Z

Hi-Z

Hi-Z

Oscillation

halted

R
G
B

I

YS

YM

PF0/PWM0

to

PF3/PWM3

EXLC
XLC

R, G, B, I, YS, YM

Writing data to output polarity
register brings output to active

Output polarity
“0” when reset

Oscillator control

EXLC

IP

OSD display clock

IP

XLC

PWM

Port F data

“1” when reset

Port F selection

“0” when reset

SCL, SDA

I2C output enable

PWM

Port F data

“1” when reset

Port F function selection

“0” when reset

SCL, SDA

2

(I

C circuit)

Schmitt input

∗

∗

12V voltage drive

Large current 12mA

∗

IP

BUS SW

To internal I

∗

Large current 12mA

2

C pins

– 10 –

CXP85324A/85332A/85340A

2 pins

1 pins

Pin When resetCircuit format

RST

Oscillation

Low level

EXTAL
XTAL

IP

EXTAL

XTAL

• Shows the circuit composition
during oscillation.

• Feedback resistor is removed
during STOP.
(This device does not enter
the STOP mode.)

Schmitt input

Pull-up resistor

From power-on reset circuit
(Mask option)

Mask option

OP

– 11 –

CXP85324A/85332A/85340A

∗1

VIN and VOUT should not exceed VDD + 0.3V.

∗2

The large current output port is Port D (PD) and Port F (PF).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.

Supply voltage
Input voltage
Output voltage
Mid-voltage drive output voltage
High level output current
High level total output current

Low level output current

Low level total output current
Operating temperature
Storage temperature

Allowable power dissipation

VDD
VIN
VOUT
VOUTP
IOH
∑IOH

IOL

IOLC
∑IOL

Topr
Tstg

PD

–0.3 to +7.0

–0.3 to +7.0

∗1

–0.3 to +7.0

∗1

–0.3 to +15.0

–5

–50

15

20

130

–20 to +75

–55 to +150

1000

600

V
V
V

V
mA
mA

mA

mA
mA

°C

°C
mW
mW

PF0 to PF3 pins

Total of all output pins
Ports excluding large current

output (value per pin)
Large current output port

(value per pin)

∗2

Total of all output pins

SDIP
QFP

Item Symbol Ratings Unit Remarks

Absolute Maximum Ratings (Vss = 0V reference)

Supply voltage

High level
input voltage

Low level
input voltage

Operating temperature

5.5

5.5

5.5
VDD
VDD

VDD + 0.3

0.3VDD

0.2VDD

0.4
+75

V

V
V

V
V
V
V
V
V

°C

Item Symbol Min. Max. Unit Remarks

4.5

3.5

2.5

0.7VDD

0.8VDD

VDD – 0.4

0
0

–0.3

–20

VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr

Guaranteed operation range for 1/2 and 1/4
frequency dividing modes.

Guaranteed operation range for 1/16 frequency
dividing mode or SLEEP mode.

Guaranteed data hold range for STOP mode.

∗1
∗2
∗3

EXTAL pin

∗4
∗2
∗3

EXTAL pin

∗4

VDD

∗1

This device does not enter the STOP mode.

∗2

PA, PB, PC, PE2 to PE5, SCL0, SCL1, SDA0, SDA1 pins

∗3

INT2, SCK, SI, HSI, ACI, RMC, EC, INT0, INT1, HSYNC, VSYNC, RST pins.

∗4

Specifies only during external clock input.

Recommended Operating Conditions (Vss = 0V reference)

– 12 –

CXP85324A/85332A/85340A

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA

VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA

VDD = 4.5V, IOL = 3.0mA
VDD = 4.5V, IOL = 4.0mA

VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V

VDD = 4.5V, IOL = 12.0mA

High level
output voltage

Low level
output voltage

Input current

I/O leakage current

Open drain output
leakage current
(N-ch Tr off)

I2C bus switch
connection impedance
(Output Tr off)

Supply current

Input capacitance

4.0

3.5

7

∗4

13

∗5

0.6

∗4

0.8

∗5

—

10

—

3

∗4

3

∗5

—

20

µA

pF

20

∗4

50
10

120

30

∗5

mA

mA

µA
µA

Ω

0.4

0.6

1.5

0.4

0.6
40

–40

–400

±10

V
V

V
V

V

µA
µA
µA

µA

0.5
–0.5
–1.5

V
V

PA to PD, PE6, PE7,
R, G, B, I, YS, YM

PA to PD, PE6, PE7,
R, G, B, I, YS, YM,
PF0 to PF3, RST

∗1

PD, PF
PF4 to PF7

(SCL0, SCL1,
SDA0, SDA1)

EXTAL

RST

∗2

PA to PE, HSYNC,
VSYNC, R, G, B, I,
YS, YM, RST

∗2

PF0 to PF3
PF4 to PF7

SCL0: SCL1
SDA0: SDA1

VDD = 5.5V, VIL = 0.4V
VDD = 5.5V,

VI = 0, 5.5V

VDD = 5.5V, VOH = 12.0V
VDD = 5.5V, VOH = 5.5V

VDD = 4.5V
VSCL0 = VSCL1 = 2.25V
VSDA0 = VSDA1 = 2.25V

VDD

∗3

1/2 frequency dividing
operation mode
VDD = 5.5V
4MHz, 8MHz
crystal oscillation
(C1 = C2 = 22pF)

STOP mode

∗6

VDD = 5.5V
termination of 4MHz, 8MHz
crystal oscillation

SLEEP mode
VDD = 5.5V
4MHz, 8MHz crystal oscillation
(C1 = C2 = 22pF)

PA to PD,
PE0 to PE5, SCL,
SDA, EXLC,
EXTAL, RST

1MHz clock
0V for non-measurement pins

Item Symbol Pin Condition Min. Typ. Max. Unit

VOH

VOL

IIZ

ILOH

RBS

IDD

IDDSL

IDDST

CIN

IIHE
IIHL
IILR

DC Characteristics (Ta = –20 to +75°C, Vss = 0V reference)

∗1

Specifies RST pin only when the power-on reset circuit is selected with mask option.

∗2

For RST pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current
when non-resistor is selected.

∗3

When all output pins open. Specifies only when the OSD oscillation is halted.

∗4

Oscillation clock 4MHz version

∗5

Oscillation clock 8MHz version

∗6

This device does not enter the stop mode.

– 13 –

CXP85324A/85332A/85340A

AC Characteristics

(1) Clock timing

∗1

tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits

(CPU clock selection).

tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

∗2

Oscillation clock 4MHz version

∗3

Oscillation clock 8MHz version

System clock frequency

System clock input
pulse width

System clock
rise and fall times

Event count input
clock pulse widtth

Event count input clock
rise and fall times

fC

tXL,
tXH

tCR,
tCF

tEH,
tEL

tER,
tEF

XTAL
EXTAL

EXTAL

EXTAL

EC

EC

MHz

ns

ns

ns

ms

Item System Pin Condition Min. Max. Unit

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig 1, Fig 2
External clock drive

Fig. 3

Fig. 3

3.5

∗2

7

∗3

100

∗2

50

∗3

tsys + 50

∗1

4.5
9

200

20

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Fig. 1. Clock timing

EXTAL

t

XH tXLtCF tCR

0.4V

V

DD – 0.4V

1/fc

Fig. 2. Clock applied condition

A

A

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

External clock

EXTAL

XTAL

OPEN

C

1 C2

Fig. 3. Event count clock timing

EC

t

EH tELtEF tER

0.2VDD

0.8VDD

AAA

AAA

– 14 –

CXP85324A/85332A/85340A

(2) Serial transfer (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

SCK cycle time

tKCY

SCK

Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

1000

8000/fc

∗

400

4000/fc' – 50

∗

100
200
200
100

200
100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

SCK

SI

SI

SO

tKH
tKL

tSIK

tKSI

tKSO

SCK
high and low level widths

SI input set-up time
(for SCK ↑)

SI hold time
(for SCK ↑)

SCK ↓ → SO delay time

System Pin Condition Min. Max. Unit

Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

∗

The value of fc' varies as shown below depending on the specification of oscillation clock option.
4MHz version: fc' = fc
8MHz version: fc' = fc/2

Fig. 4. Serial transfer timing

0.2VDD

0.8VDD

tKL tKH

SO

tKCY

tSIK

tKSI

0.2VDD

0.8VDD

tKSO

0.2VDD

0.8VDD
Output data

Input data

SI

SCK

– 15 –

CXP85324A/85332A/85340A

Resolution
Linearity error
Zero transition

voltage
Full-scale transition

voltage
Conversion time
Sampling time
Analog input voltage

VZT

∗1

VFT

∗2

tCONV
tSAMP

VIAN

AN0 to AN3

Ta = 25°C
VDD = 5.0V
Vss = 0V

–50

4910

160/fc'

∗3

12/fc'

∗3

0

10

4970

8

±1
70

5030

VDD

Bits
LSB

mV

mV

µs
µs

V

Item Symbol Pin Condition Min. Typ. Max. Unit

(3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Linearity error

VZT VFT

Analog input

FF

H

FEH

01H
00H

Digital conversion value

Fig. 5. Definitions for A/D converter terms

∗1

VZT: Digital conversion values change between 00H ←→ 01H.

∗2

VFT: Digital conversion values change between 0EH ←→ 0FH.

∗3

The value of fc' varies as follows depending on the
specification of oscillation clock option.
4MHz version: fc' = fc
8MHz version: fc' = fc/2

– 16 –

CXP85324A/85332A/85340A

External interruption
high and low level widths

Reset input low level width

INT0 to
INT2

RST

1

8/fc'

∗

µs
µs

Item Symbol Pin Condition Min. Max. Unit

tIH
tIL

tRSL

Power supply rise time
Power supply cutt-off time

tR
tOFF

VDD

Power-on reset
Repeated power-on reset

0.05
1

50 ms

ms

Item Symbol Pin Condition Min. Max. Unit

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

(5) Power-on reset
Power-on reset

∗

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

0.2VDD

0.8VDD

tIH tIL

INT0 to INT2
(falling edge)

∗

Specifies only when power-on reset function is selected.

0.2V

0.2V

4.5V

V

DD

tR

tOFF

Take care when turning on power.

Fig. 6. Interruption input timing

tRSL

0.2VDD

RST

Fig. 7. RST input timing

Fig. 8. Power-on reset

∗

The value of fc' varies as shown below depending on the specification of oscillation clock option.
4MHz version: fc' = fc
8MHz version: fc' = fc/2

– 17 –

CXP85324A/85332A/85340A

(6) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item
SCL clock frequency
Bus-free time before starting transfer
Hold time for starting transfer
Clock low level width
Clock high level width
Set-up time for repeated transfers
Data hold time
Data set-up time
SDA, SCL rise time
SDA, SCL fall time
Set-up time for transfer completion

fSLC

tBUF
tHD; STA
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tR
tF
tSU; STO

SCL
SDA, SCL
SDA, SCL
SCL
SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL

0

4.7

4.0

4.7

4.0

4.7
0

∗

250

4.7

100

1

300

kHz

µs
µs
µs
µs
µs
µs
ns
µs
ns
µs

Symbol Pin Condition Min. Max. Unit

∗

For the data hold time, the SCL rise time (300ns Max.) is not considered so that 300ns should be exceeded.

Fig. 9. I2C bus transfer data timing

PSt

t

SU; STO

tSU; STA

tHD; STA

tSU; DATtHIGHtHD; DAT

tFtR

tLOW

tHD; STA

SP

t

BUF

SDA

SCL

Fig. 10. I2C device recommended circuit

I2C

device

I2C

device

RS RS RS RS RP RP

SDA0
(or SDA1)

SCL0
(or SCL1)

• A pull-up resistor (Rp) must be connected to SDA0 (or SDA1), and SCL0 (or SCL1).

• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce spike

noise caused by CRT flashover.

– 18 –

CXP85324A/85332A/85340A

(7) OSD timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

OSD clock frequency

HSYNC pulse width
VSYNC pulse width
HSYNC afterwrite

rise and fall times
VSYNC beforewrite

rise and fall times

fOSC

tHWD
tVWD

tHCG

tVCG

EXLC
XLC

HSYNC
VSYNC

HSYNC

VSYNC

Fig. 12

Fig. 11
Fig. 11

Fig. 11

Fig. 11

4

1.2
1

7

∗1

14

∗2

200

1.0

MHz

µs

H

∗3

ns

µs

Symbol

Pin

Condiiton Unit

Min. Max.

∗1

Oscillation clock 4MHz version

∗2

Oscillation clock 8MHz version

∗3

H indicates 1HSYNC period.

Fig. 11. OSD timing

0.8VDD

0.2VDD

tHCG

tHWD

HSYNC

For OSD I/O polarity register

(OPOL: 01FAH)

bit 7 at “0”

0.8VDD

0.2VDD

tVCG

VSYNC

For OSD I/O polarity register

(OPOL: 01FAH)

bit 6 at “0”

tVWD

Fig. 12. LC oscillation circuit connection

L

C

2C1

EXLC XLC

R

∗

1

∗

1

The series resistor for XLC is used to reduce the frequency of occurrence of the undesired radiation.

– 19 –

CXP85324A/85332A/85340A

Appendix

Fig. 13. SPC700 Series recommended oscillation circuit

A

EXTAL

XTAL

C

1 C2

Rd

A

EXTAL

XTAL

(i)

A

EXTAL

XTAL

C

1 C2

Rd

XTAL

(ii)

Manufacturer

MURATA MFG
CO., LTD.

KINSEKI LTD.

Model

CSA4.00MG
CSA4.19MG
CSA8.00MTZ
CST4.00MGW

∗1

CST4.19MGW

∗1

CST8.00MTW

∗1

HC-49/U03

HC-49/U(-S)

fc (MHz)

4.00

4.19

8.00

4.00

4.19

8.00

4.00

4.19

8.00

4.00

4.19

8.00

30

12

30

12

0

∗2

0

∗2

C1 (pF) C2 (pF) Rd (Ω)

Circuit

Example

(i)

(ii)

(i)

27

27

0

∗2

(i)

∗1

These models have the on-chip grounding capacitors (C1 and C2).

∗2

The series resistor for XTAL can reduce the effect of the noise caused by the electrostatic discharge.

Item

Content
Reset pin pull-up resistor
Power-on reset circuit
Oscillation clock

Non-existent
Non-existent

4MHz

Existent
Existent

8MHz

Mask Option Table

RIVER ELETEC
CO., LTD.

AAA

AAA

AAA

– 20 –

CXP85324A/85332A/85340A

Fig. 14. Characteristics curves

1 5 10

fc – System clock [MHz]

16

14

12

10

8

6

4

2

0

I

DD

– Supply current [mA]

IDD vs. fc (VDD = 5V, Ta = 25°C, Typical)

100

10

0

L – Inductance [µH]

Parameter curve for OSD oscillator L vs. C

(Analytically calculated value)

50 100

C

1, C2 – Capacitance [pF]

frequency
mode

1
2

frequency
mode

1
4

frequency
mode

1

16

SLEEP mode

5.0MHz

6.5MHz

13.0MHz

2 3

V

DD – Supply voltage [V]

1

I

DD

– Supply current [mA]

IDD vs. VDD (fc = 4MHz, Ta = 25°C, Typical)

frequency
mode

1

16

SLEEP mode

4 5 6

0.1

10

15

frequency
mode

1
4

frequency
mode

1
2

2 3

V

DD – Supply voltage [V]

1

I

DD

– Supply current [mA]

IDD vs. VDD (fc = 8MHz, Ta = 25°C, Typical)

frequency mode

1

16

SLEEP mode

4 5 6

0.1

10

15

frequency mode

1
4

frequency mode

1
2

fOSC = C = C1 // C2

1

2π√ LC

– 21 –

CXP85324A/85332A/85340A

Package Outline Unit: mm

PACKAGE STRUCTURE

MOLDING COMPOUND
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT

SONY CODE
EIAJ CODE
JEDEC CODE

SDIP-64P-01

42 ALLOY

SOLDER PLATING

EPOXY / PHENOL RESIN

64PIN SDIP (PLASTIC) 750mil

SDIP064-P-0750-A

57.6 – 0.1

+ 0.4

64

33

1 32

1.778

19.05

17.1 – 0.1

+ 0.3

0° to 15°

0.25 – 0.05

+ 0.1

0.5 MIN

4.75 – 0.1

+ 0.4

3 MIN

0.5 ± 0.1

0.9 ± 0.15

8.6g

SONY CODE

EIAJ CODE

JEDEC CODE

23.9 ±0.4

20.0 – 0.1

1.0

0.4 – 0.1

+ 0.15

14.0 – 0.1

1

19

20

32

33

51

52

64

0.15 – 0.05

+ 0.1

2.75 – 0.15

16.3

0.1 – 0.05

+ 0.2

0.8 ± 0.2

M

± 0.12

0.15

+ 0.4

17.9 ± 0.4

+ 0.4

+ 0.35

64PIN QFP(PLASTIC)

QFP–64P–L01

∗

QFP064–P–1420

PACKAGE MATERIAL

LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT

EPOXY RESIN
SOLDER/PALLADIUM

COPPER /42 ALLOY

PACKAGE STRUCTURE

PLATING

1.5g