Page 1
CMOS 8-bit Single Chip Microcomputer
Description
The CXP842P24 is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer/counter, and remote control
reception circuit besides the basic configurations of
8-bit CPU, ROM, RAM, and I/O port.
The CXP842P24 also provides a power-on reset
function and a sleep/stop function that enables lower
power consumption.
This IC is the PROM-incorporated version of the
CXP84224 with built-in mask ROM. This provides the
additional feature of being able to write directly into
the program. Thus, it is most suitable for evaluation
use during system development and for small-quantity
production.
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle 400ns at 10MHz operation
• Incorporated PROM capacity 24K bytes
• Incorporated RAM capacity 624 bytes
• Peripheral functions
— A/D converter 8 bits, 8 channels, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface Incorporated 8-bit, 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock synchronization, 1 channel
— Timer 8-bit timer
8-bit timer/counter
19-bit time base timer
16-bit capture timer/counter
— Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO
— PWM output 14 bits, 1 channel
• Interruption 14 factors, 14 vectors, multi-interruption possible
• Standby mode Sleep/stop
• Package 64-pin plastic SDIP
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E93839A7X-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP842P24
64 pin SDIP (Plastic)
Structure
Silicon gate CMOS IC
Page 2
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CXP842P24
8
2
2
2
2
PA0/AN0
to
PA7/AN7
PE4/PWM
PE2/RMC
PB1/CS0
PB3/SI0
PB4/SO0
PB2/SCK0
PB6/SI1
PB7/SO1
PB5/SCK1
PE5/TO
PB0/CINT
PE1/EC1
PE0/EC0
A/D CONVERTER
AVss
AV
REF
14 BIT PWM GENERATOR
REMOCON
FIFO
SERIAL
INTERFACE
UNIT 0
FIFO
SERIAL INTERFACE UNIT 1
8 BIT TIMER/COUNTER 0
8 BIT TIMER 1
16 BIT CAPTURE
TIMER/COUNTER 2
INTERRUPT CONTROLLER
PI0/INT0
PI1/INT1
PI2/INT2
PI3/INT3
PE3/NMI
SPC700
CPU CORE
PROM
24K BYTES
CLOCK GEN./
SYSTEM CONTROL
RAM
624 BYTES
PRESCALER/
TIME BASE TIMER
EXTAL
XTAL
V
DD
Vss
PORT A
7
8
8
4
2
7
PA0 to PA7
PB0 to PB6
PB7
PC0 to PC7
PD0 to PD7
PE0 to PE3
PE4 to PE5
PF0 to PF7
PG0 to PG2
PI0 to PI6
RST
8
8
3
PORT B
PORT C
PORT D
PORT E
PORT F
PORT G
PORT I
Vpp
Block Diagram
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CXP842P24
Pin Assignment (Top View)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
40
39
38
37
36
35
34
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
Vpp
PG0
PG1
PG2
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
RST
XTAL
EXTAL
Vss
VDD
PI6
PI5
PI4
PI3/INT3
AV
REF
AVss
PI2/INT2
PI1/INT1
PI0/INT0
PE5/TO
PE4/PWM
PE3/NMI
PE2/RMC
PE1/EC1
PE0/EC0
PB7/SO1
PB6/SI1
PB5/SCK1
PB4/SO0
PB3/SI0
PB2/SCK0
PB1/CS0
PB0/CINT
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
Note) Vpp (Pin 1) is always connected to VDD.
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CXP842P24
Pin Description
Symbol I/O Description
I/O/Analog input
PA0/AN0
to
PA7/AN7
(Port A)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of the
pull-up resistance can be
set through the software
in a unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
I/OPC0 to PC7
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving
12mA sink current. Incorporation of pull-up resistor can be set through
the software in a unit of 4 bits.
(8 pins)
I/OPD0 to PD7
(Port D)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
I/OPF0 to PF7
(Port F)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of
pull-up resistor can be set through the software in a unit of 4 bits.
(8 pins)
Input/Input
Input/Input
Input/Input
Input/Input
Output/Output
Output/Output
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
PE4/PWM
PE5/TO
(Port E)
6-bit port. Lower 4 bits
are for inputs; upper
2 bits are for outputs.
Incorporation of pull-up
resistor can be set
through the software.
(6 pins)
External event inputs for timer/counter.
(2 pins)
Remote control reception circuit input.
Non-maskable interruption request input.
14-bit PWM output.
Rectangular wave output for 16-bit
timer/counter (duty output 50%).
I/O/Input
I/O/Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/Input
Output/Output
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
(Port B)
Lower 7-bit I/O port in
which I/O can be set in a
unit of single bits. Also,
an uppermost bit (PB7)
exclusively for output.
Incorporation of pull-up
resistor can be set
through the software in a
unit of 4 bits.
(8 pins)
External capture input to 16-bit timer/counter.
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
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CXP842P24
Symbol I/O Description
I/OPG0 to PG2
(Port G)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(3 pins)
I/O/Input
PI0/INT0
to
PI3/INT3
I/O
PI4 to PI6
Input
Crystal connectors for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.
EXTAL
Output
XTAL
I/O Low-level active, system reset.
RST
Input Reference voltage input for A/D converter.
AVREF
A/D converter GND.
AVss
Positive power supply.
VDD
Positive power supply for incorporated PROM writing.
Connect to VDD during normal operation.
Vpp
GND
Vss
(Port I)
7-bit I/O ports. I/O can be set in a unit of single
bits. Incorporation of pull-up resistor can be set
through the software in a unit of 4 bits.
(7 pins)
External interruption
request inputs.
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CXP842P24
Port B
Data bus
RD (Port B)
Port B direction
IP
Port B data
Pull-up resistance
"0" when reset
"0" when reset
∗
Pull-up transistors
approx. 10kΩ
∗
Schmitt input
CINT
CS0
SI0
SI1
8 pins
Hi-Z
Hi-Z
When reset
PA0/AN0
to
PA7/AN7
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Port B
4 pins
2 pins
Hi-Z
PB2/SCK0
PB5/SCK1
Data bus
RD (Port A)
Port A direction
IP
Port A data
Pull-up resistance
Port A input
selection
Input protection
circuit
"0" when reset
"0" when reset
"0" when reset
Input multiplexer
A/D converter
∗
Pull-up transistors
approx. 10kΩ
∗
Input/Output Circuit Formats for Pins
Port A
Pin
Circuit format
Data bus
RD (Port B)
IP
Port B output
selection
"0" when reset
∗
Pull-up transistors
approx. 10kΩ
∗
Schmitt input
SCK in
Port B data
Port B direction
"0" when reset
Pull-up resistance
"0" when reset
SCK OUT
Output enable
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CXP842P24
1 pin
Hi-Z
Hi-Z
Pin
When reset
Circuit format
PB4/SO0
PC0 to PC7
8 pins
4 pins
Hi-Z
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
IP
Schmitt input
RD (Port E)
Data bus
EC0
EC1
RMC/NMI
Data bus
RD (Port C)
Port C direction
IP
Port C data
Pull-up resistance
"0" when reset
"0" when reset
∗
1
High current drive
of 12mA possible
∗
2
Pull-up transistors
approx. 10kΩ
∗
2
∗
1
Data bus
RD (Port B)
IP
Port B output
selection
"0" when reset
∗
Pull-up transistors
approx. 10kΩ
∗
Port B data
Port B direction
"0" when reset
Pull-up resistance
SO
Output enable
Port E
Port C
Port B
1 pin
High level
PB7/SO1
Data bus
RD (Port B)
"1" when reset
∗
Pull-up transistors
approx. 200kΩ
Port B output
selection
Port B data
Output enable
SO
Internal reset signal
∗
Port B
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CXP842P24
1 pin
High level
Pin
When reset
Circuit format
PE5/TO
Data bus
Port E output
selection
"0" when reset
Port E data
"1" when reset
RD (Port E)
Port E output
selection
"00" when reset
Port E output
selection
Ouput enable
TO
Port E
1 pin
High level
PE4/PWM
Data bus
RD (Port E)
Port E output
selection
PWM
Port E data
"0" when reset
"1" when reset
Port E
22 pins
Hi-Z
PD0 to PD7
PF0 to PF7
PG0 to PG2
PI4 to PI6
Data bus
RD
IP
A
Port data
"0" when reset
∗
Pull-up transistors
approx. 10kΩ
∗
Port direction
Pull-up resistance
"0" when reset
Port D
Port F
Port G
Port I
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CXP842P24
2 pins
Oscillation
Pin
When reset
Circuit format
EXTAL
XTAL
IP
EXTAL
XTAL
• Diagram shows circuit
composition during oscillation.
• Feedback resistor is removed
during stop.
IP
Schmitt input
Pull-up resistor
Mask option
OP
IP
Power-on reset function
(mask option)
1 pin
Low level
RST
4 pins
Hi-Z
Data bus
RD
IP
A
Port data
"0" when reset
∗
Pull-up transistors
approx. 10kΩ
∗
Port direction
Pull-up resistance
"0" when reset
INT0
INT1
INT2
INT3
Port I
PI0/INT0
to
PI3/INT3
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CXP842P24
Input voltage
Output voltage
High level output current
High level total output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
∗1
VIN and VOUT must not exceed VDD + 0.3V.
∗2
The high current drive transistor is the N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
VDD
Vpp
AVSS
VIN
VOUT
IOH
∑IOH
IOL
IOLC
∑IOL
Topr
Tstg
PD
Low level output current
Supply voltage
–0.3 to +7.0
–0.3 to +13.0
–0.3 to +0.3
–0.3 to +7.0
∗1
–0.3 to +7.0
∗1
–5
–50
15
20
100
–10 to +75
–55 to +150
1000
V
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
Incorporated PROM
Output per pin
Total for all output pins
Value per pin, excluding large current outputs
Value per pin∗2for large current outputs
Total for all output pins
Item Symbol Ratings Unit Remarks
Absolute Maximum Ratings (Vss = 0V reference)
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CXP842P24
High level input
voltage
Low level input
voltage
Operating temperature
Supply voltage
5.5
5.5
5.5
VDD
VDD
VDD + 0.3
0.3VDD
0.2VDD
0.4
+75
V
V
V
V
V
V
°C
V
V
Item
Symbol Min. Max. Unit Remarks
4.5
3.5
2.5
0.7VDD
0.8VDD
VDD – 0.4
0
0
–0.3
–10
VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr
High-speed mode guaranteed operation
range
∗1
Low-speed mode guaranteed operation
range
∗1
Guaranteed data hold range during stop
∗5
∗2
Hysteresis input
∗3
EXTAL
∗4
∗2
Hysteresis input
∗3
EXTAL
∗4
VDD
Vpp
Recommended Operating Conditions (Vss = 0V reference)
∗1
High-speed mode is 1/2 frequency demultiplication clock selection; low-speed mode is 1/16 frequency
demultiplication clock selection.
∗2
Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF, PG, PI4 to PI6).
∗3
Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2,
INT3.
∗4
Specifies only during external clock input.
∗5
Vpp and VDD should be set to the same voltage.
Vpp = VDD
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CXP842P24
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
High level
output voltage
4.0
3.5
0.5
–0.5
–1.5
–10
V
V
V
V
V
µA
µA
µA
mA
µA
µA
PC
PA to PD,
PE4, PE5,
PF, PG, PI
EXTAL
RST
Item Symbol Pins Conditions Min.
Clock 1MHz
0V for no-measured pins
VDD
IDD1
IIL
IIZ
IDDS1
IDDS3
CIN
VOH
VOL
IIHE
IILE
IILR
Low level
output voltage
Input current
Typ.
0.4
0.6
1.5
40
–40
–400
–2.0
±10
Max.
Unit
DC Characteristics
Electrical Characteristics
(Ta = –10 to +75°C, Vss = 0V reference)
∗1
Pins PA to PD, and PF, PG, PI specify the input current when pull-up resistance has been selected;
leakage current when no resistance has been selected. (Excludes output PB7)
∗2
When all pins are open.
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 5.5V, termination of 10MHz
crystal oscillation .
Power supply
current
∗2
Input capacity
VDD = 5.5V,
VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
VDD = 5.5V,
VI = 0, 5.5V
High-speed mode operation
(1/2 frequency demultiplier clock)
Sleep mode
Stop mode
I/O leakage
current
PA to PD∗1,
PF, PG, PI
∗1
PE0 to PE3
40
8
30
18
1.1
mA
mA
µA
pF2010
Pins other
than PB7,
PE4, PE5,
AVREF, VDD,
VSS
Page 13
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CXP842P24
EXTAL
t
XH tXLtCF tCR
0.4V
V
DD – 0.4V
1/fc
A
A
Crystal oscillation
Ceramic oscillation
EXTAL
XTAL
External clock
EXTAL
XTAL
74HC04
C
1 C2
Fig. 2. Clock applied condition
Fig. 1. Clock timing
AC Characteristics
(1) Clock timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
∗1
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
System clock frequency
System clock input pulse
width
System clock input
rise time, fall time
Event count input clock
pulse width
Event count input clock
rise time, fall time
fC
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
XTAL
EXTAL
EXTAL
EXTAL
EC0
EC1
EC0
EC1
MHz
ns
ns
ns
ms
Item Symbol Pin Conditions Min. Unit
Fig. 1, Fig. 2
Fig. 1, Fig. 2
External clock drive
Fig. 1, Fig. 2
External clock drive
Fig. 3
Fig. 3
1
37.5
tsys + 50
∗1
Typ. Max.
10
200
20
EC0
EC1
t
EH tELtEF tER
0.2VDD
0.8VDD
Fig. 3. Event count clock timing
AAA
AA
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CXP842P24
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
(2) Serial transfer (CH0) (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
CS0 ↓ → SCK0
delay time
CS0 ↑ → SCK0
float delay time
CS0 ↓ → SO0
delay time
CS0 ↑ → SO0
float delay time
CS0 High level width
SCK0 cycle time
SCK0
High and Low level widths
SI0 input setup time
(for SCK0 ↑)
SI0 input hold time
(for SCK0 ↑)
SCK0 ↓ → SO0
delay time
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK0
SCK0
SO0
SO0
CS0
SCK0
SCK0
SI0
SI0
SO0
Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
ns
ns
ns
ns
ns
Symbol Pin Min.
tsys + 200
tsys + 200
tsys + 200
tsys + 200
tsys + 200
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
200
tsys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsys + 200
100
Max. UnitCondition
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
Page 15
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CXP842P24
Fig. 4. Serial transfer CH0 timing
CS0
SCK0
0.2V
DD
0.8VDD
tWHCS
tDCSK tDCSKF
0.8VDD
0.2VDD
0.8VDD
tKCY
tKL tKH
0.8VDD
0.2VDD
SI0
t
SIK
Input
data
tDCSO tKSO tDCSOF
Output data
0.8V
DD
0.2VDD
SO0
tKSI
Page 16
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CXP842P24
Fig. 5. Serial transfer CH1 timing
SCK1
SI1
SO1
t
KCY
tKL tKH
0.2VDD
0.8VDD
tSIK tKSI
tKSO
Input data
Output data
0.2V
DD
0.8VDD
0.2VDD
0.8VDD
Serial transfer (CH1) (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pin Min. Max. UnitCondition
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK1
SCK1
SI1
SI1
SO1
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
1000
16000/fc
400
8000/fc – 50
100
200
200
100
200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
SCK1 cycle time
SCK1 High and Low level
widths
SI1 input setup time
(for SCK1 ↑)
SI1 input hold time
(for SCK1 ↑)
SCK1 ↓ → SO1 delay time
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CXP842P24
Fig. 6. Definition of A/D converter terms
Analog input
Linearity error
V
FTVZT
00H
01H
FEH
FFH
Digital conversion value
∗
1
VZT : Value at which the digital conversion value changes
from 00H to 01H and vice versa.
∗
2
VFT : Value at which the digital conversion value changes
from FEH to FFH and vice versa.
∗
3
fADC indicates the below values due to ADC operation
clock selection.
During PS2 selection, fADC = fc/2
During PS1 selection, fADC = fc
Conversion time
Sampling time
Reference input voltage
Analog input voltage
tCONV
tSAMP
VREF
VIAN
VZT
∗1
VFT
∗2
IREF
AVREF
AN0 to AN7
Ta = 25°C
VDD = 5.0V
VSS = AVSS = 0V
Operation mode
Sleep mode
Stop mode
Linearity error
Zero transition voltage
Full-scale transition
voltage
Resolution
AVREF current
AVREF
IREFS
µs
µs
V
V
VDD
AVREF
1.0
mA
10 µA
0.6
160/fADC
∗3
12/fADC
∗3
VDD – 0.5
0
Item Symbol Pin Condition Min. Typ. Max. Unit
Bits
(3) A/D converter characteristics
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
8
LSB
150 mV
5120
70
5050
–10
4930 mV
±3
Page 18
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CXP842P24
(4) Interruption, reset input (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
0.2VDD
0.8VDD
tIH tIL
INT0
INT1
INT2
INT3
NMI
(NMI specifies only for
the falling edge.)
tIL tIH
Fig 7. Interruption input timing
tRSL
0.2VDD
RST
External interruption
High and Low level widths
Reset input Low level width
INT0
INT1
INT2
INT3
NMI
RST
1
32/fc
µs
µs
Item Symbol Pin Condition Min. Max. Unit
tIH
tIL
tRSL
Fig. 8. RST input timing
Power supply rising time
Power supply cut-off time
tR
tOFF
VDD
Power-on reset
Repetitive power-on reset
0.05
1
50 ms
ms
Item Symbol Pin Condition Min. Max. Unit
(5) Power-on reset (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Fig. 9. Power-on reset
0.2V0.2V
4.5V
V
DD
tR tOFF
The power supply shoule rise smoothly.
Page 19
– 19 –
CXP842P24
Appendix
C1
A
EXTAL
XTAL
C
2
A
EXTAL
XTAL
(i) Main clock
A
EXTAL
XTAL
C1 C2
XTAL
(ii) Main clock
Rd
Rd
Manufacturer
MURATA
MFG
CO., LTD.
RIVER
ELETEC
CORPORATION
KINSEKI
LTD.
Model
CSA4.19MG
CSA8.00MTZ
CST4.19MGW
∗
CST8.00MTW
∗
HC-49/U03
HC-49/U (-S)
fc (MHz)
4.19
8.00
10.00
4.19
8.00
10.00
4.19
8.00
10.00
4.19
8.00
10.00
30
12
27
30
12
27
20 20
0
0
0
C1 (pF) C2 (pF)
Rd (Ω)
Circuit
example
(i)
CSA10.0MTZ
(ii)
CST10.0MTW
∗
(i)
Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).
Product List
Optional item
Package
ROM capacity
Reset pin pull-up resistor
Power-on reset circuit
64-pin plastic SDIP
20K bytes/24K bytes
Existent/non existent
Existent/non existent
64-pin plastic SDIP
PROM 24K bytes
Existent
Existent
Mask CXP842P24Q-1-
Fig. 10. SPC700 series recommended oscillation circuit
AA
AA
AA
Page 20
– 20 –
CXP842P24
Package Outline Unit: mm
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
JEDEC CODE
SDIP-64P-01
42 ALLOY
SOLDER PLATING
EPOXY RESIN
64PIN SDIP (PLASTIC)
SDIP064-P-0750
57.6 – 0.1
+ 0.4
64
33
1 32
1.778
19.05
17.1 – 0.1
+ 0.3
0° to 15°
0.25 – 0.05
+ 0.1
0.5 MIN
4.75 – 0.1
+ 0.4
3.0 MIN
0.5 ± 0.1
0.9 ± 0.15
8.6g
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