Datasheet CXP827P16 Datasheet (Sony)

CXP827P16

CMOS 8-bit Single Chip Microcomputer

Description

The CXP827P16 microcomputer is composed of a
CPU, ROM, RAM, and I/O ports. These chips feature
many other high-performance circuits in a single-chip
CMOS design, including an A/D converter, serial
interface, timer/counter, time-base timer, fluorescent
display panel controller/driver, remote control receiver,
PWM output circuit and 32kHz timer/counter.

This IC also includes sleep/stop functions which
can be used to achieve low power consumption.

CXP827P16 is the PROM-incorporated version of
the CXP82716 with built-in mask ROM, and it is able to
write directly into the program. Thus, it is most suitable
for evaluation use during system development and for
small-quantity production.

Features

• Instruction set which supports a wide array of data types

— 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic,

and Boolean bit operations.

• Minimum instruction cycle 400ns at 10MHz

122µs at 32kHz

• On-chip PROM 16 Kbytes

• On-chip RAM 448 bytes (Including fluorescent display data area)

• Peripheral functions

— A/D converter 8-bit, 8-channel, successive approximation system

(conversion rate 32µs/10MHz)

— Serial interface On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer),

2 channels for 1 circuit

— Timers 8-bit timer

8-bit timer/counter
19-bit time-base timer
32kHz timer/counter

— Fluorescent display panel controller/driver

High voltage drive output port of 24 pins (40V)
Maximum of 144 segments display available
1 to 16-digit dynamic display
Dimmer function
On-chip pull-down resistor

Hardware key scan function (Maximum of 8 × 8 key matrix available)
— Remote control receiver circuit On-chip 6-stage FIFO 8-bit pulse measurement counter
— PWM output 8-bit, 1-channel

• Interrupts 13 factors, 13 vectors multi-interruption possible

• Standby mode SLEEP/STOP

• Package 64-pin plastic SDIP

Structure

Silicon gate CMOS IC

64 pin SDIP (Plastic)

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E93Z22-ST

CXP827P16

PP

V
Vss

DD

V
RST

XTAL

EXTAL

TX

TEX

PA0 to PA7

8

PORT A

CLOCK

GENERATOR /

SYSTEM CONTROL

SPC700

CPU CORE

PB0 to PB7

8

PORT B

PC0 to PC7

8

PORT C

RAM

448 BYTES

PROM

16KBYTES

PE0 to PE4

PE5 to PE6

5

2

PORT E

PF5 to PF7

3
F

PORT

32kHz

TIMER/COUNTER

PRESCALER/

TIME BASE TIMER

PH0 to PH1

2

PORT H

Block Diagram

2
INT3/NMI
INT2

INT1

INT0

RAM

A/D CONVERTER

FDP

DRIVER

CONTROLLER/

8

8

8

8

T0 to T7

AN0 to AN7

S13 to S20

T8/S28 to T15/S21

RAM

KEY SCAN

8

FDP

V

KR0 to KR7

INTERRUPT CONTROLLER

2

SI0

SO0

FIFO

UNIT

SERIAL

INTERFACE

SI1

CS1

SCK0

FIFO

REMOCON

CS0

RMC

SO1

SCK1

8 BIT PWM

8 BIT TIMER 1

8 BIT TIMER/COUNTER 0

EC

TO

PWM

2

ADJ

– 2 –

Pin Configuration (Top View)

CXP827P16

PH0/TX

PH1/TEX

VPP

PE6/ADJ/TO

PB0/CS1
PB1/CS0

PB2/SCK0

PB3/SI0

PB4/SO0

PB5/SCK1

PB6/SI1
PB7/SO1
PC0/KR0
PC1/KR1
PC2/KR2
PC3/KR3
PC4/KR4
PC5/KR5
PC6/KR6
PC7/KR7
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7

RST

EXTAL

XTAL

Vss

10
11
12
13
14
15
16
17
18
19
20

21
22

23

24

25
26
27
28
29
30

31
32

1
2
3
4
5
6
7
8
9

64
63
62
61
60

59

58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

DD

V
PE5/PWM
PE4/RMC
PE3/INT3/NMI
PE2/INT2
PE1/INT1
PE0/EC/INT0
VFDP
T0
T1
T2
T3
T4
T5
T6
T7
T8/S28
T9/S27
T10/S26
T11/S25
T12/S24
T13/S23
T14/S22
T15/S21
S20
S19
S18
S17
S16
PF7/S15
PF6/S14
PF5/S13

Note) 1. Vpp (Pin 3) is always connected to VDD.

2. PH0/TX (Pin 1) is input port during port selection;
oscillation output during oscillation selection

– 3 –

Pin Description

CXP827P16

Symbol

PA0/AN0

to

PA7/AN7

PB0/CS1
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1

PC0/KR0

to

PC7/KR7

I/O

I/O/Analog Input

I/O/Input
I/O/Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/Input
I/O/Output

I/O/Input

(Port A)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

(Port B)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

(Port C)
8-bit I/O port. I/O can
be set in a bit unit.
Capable of driving
12mA sync current.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

Functions

Analog inputs to A/D converter.
(8 pins)

Chip select input for serial interface (CH1).
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).

Key return input for fluorescent display panel
(FDP) segment signal which performs key
scanning.
(8 pins)

PE0/INT0/
EC

PE1/INT1
PE2/INT2
PE3/INT3/

NMI
PE4/RMC
PE5

PE6/ADJ/TO

Input/Input/
Input

Input/Input
Input/Input
Input/Input/

Input
Input/Input
Output

Output

(Port E)
7-bit port.
Lower 5 bits are for
inputs; upper 2 bits are
for outputs.
(7 pins)

External event input to

External interrupt

timer/counter.

requests.
(4 pins)

Non-maskable interruption request input.
Input for remote control receiving circuit.
8-bit PWM output.
Output for timer/counter rectangular waveform

and 32kHz oscillation frequency division.

– 4 –

Symbol I/O Functions

PF5/S13

to

PF7/S15
S16 to S20

Output/Output

Output

(Port F)
3-bit output port.
(3 pins)

Segment signal output for FDP. (5 pins)

T8/S28

to

Output/Output

Output for FDP timing and segment signals. (8 pins)

T15/S21

CXP827P16

Segment signal output for FDP.
(3 pins)

T0 to T7
VFDP
EXTAL

XTAL
PH1/TEX

PH0/TX

Vpp

VDD
Vss

Output

Input
Output

Input/Input

Input/Output
Input System reset. Low-level active. RST is input pin.RST

Timing signal output for FDP. (8 pins)

FDP voltage supply when on-chip resistor is selected by mask option.

Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.

(Port H)
2-bit input
port.
(2 pins)

Crystal connectors for 32kHz timer/counter clock
oscillation circuit. Connect a 32kHz crystal oscillator
between TEX and TX. For usage as event input, connect
clock oscillation source to TEX, and leave TX open.

Positive power supply pin for writing of built-in PROM.
Under normal operating conditions, connect to VDD.

Positive power supply.
GND

– 5 –

Data bus

RD (Port B)

Port B direction

IP

Port B data

Pull-up resistor

"0" when reset

"0" when reset

∗ Pull-up transistors
approx. 100kΩ

∗

Schmitt input

CS0
CS1
SI0
SI1

SI0 and SI1 are not schmitt input.

Data bus

RD (Port B)

IP

Port B output
selection

"0" when reset

∗ Pull-up transistors
approx. 100kΩ

∗

Schmitt input

SCK IN

Port B data

Port B direction

"0" when reset

Pull-up resistor

"0" when reset

SCK OUT

Serial clock output enable

I/O Circuit Format for Pins

CXP827P16

Pin

PA0/AN0

to

PA7/AN7

8 pins

Port A

Port B

Data bus

Pull-up resistor

"0" when reset

Port A data

Port A direction

"0" when reset

RD (Port A)

Port A input
selection

"0" when reset

Circuit format

A/D converter

Input multiplexer

∗ Pull-up transistors
approx. 100kΩ

*

IP

Input protection
circuit

When reset

Hi-Z

PB0/CS1
PB1/CS0
PB3/SI0
PB6/SI1

4 pins

PB2/SCK0
PB5/SCK1

2 pins

Port B

Hi-Z

Hi-Z

– 6 –

CXP827P16

Pin

PB4/SO0
PB7/SO1

2 pins

Port B

Serial data output enable

Data bus

RD (Port B)

Port C

Pull-up resistor

"0" when reset

Pull-up resistor

"0" when reset

Port B output
selection

"0" when reset

Port B data

Port B direction

"0" when reset

SO

Circuit format

IP

∗ Pull-up transistors
approx. 100kΩ

2

∗

When reset

∗

Hi-Z

PC0/KR0

to

PC7/KR7

8 pins

PE0/EC/INT0
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC

5 pins

Data bus

Port E

Port C data

Port C direction

"0" when reset

RD (Port C)

Key input signal

IP

Schmitt input

1

∗

IP

∗1 Large current drive of 12mA possible
∗2 Pull-up transistors approx. 100kΩ

EC/INT0
INT1
INT2
INT3/NMI
RMC

Data bus

RD (Port E)

Hi-Z

Hi-Z

– 7 –

CXP827P16

PE5/PWM

1 pin

PE6/TO/ADJ

1 pin

Port E

PWM

Port E output
selection

"0" when reset

Port E data

"1" when reset

Data bus

RD (Port E)

Port E

Port E data

"1" when reset

ADJ16K∗

ADJ2K∗

Port E output selection(upper)

Port E output selection(lower)

"00" when reset

00
01

TO

1

10

1

11

TO output enable

Circuit format

Output enable

Internal reset signal

MPX

2

∗

∗1 ADJ signal is a frequency dividing output

for 32kHz oscillation frequency adjustment.
ADJ2K can be used for buzzer output.
∗2 Pull-up transistor approx. 150kΩ .

When resetPin

High level

High level

with approx.

150kΩ

resistor

(

when reset

)

PF5/S13

to

PF7/S15

3 pin

Port F

Segment output data

Output selection control signal

("0" when reset)

Port F data

Data bus

RD (Port F)

∗ High voltage drive transistor

∗

Hi-Z

– 8 –

CXP827P16

Pin

S16 to S20
T15/S21

to
T8/S28
T0 to T7

21 pins

EXTAL
XTAL

2 pins

PH1/TEX
PH0/TX

Segment output data

Output selection control signal

("0" when reset)

EXTAL

XTAL

PH1/TEX

Circuit format

Pull-down
resistor

IP

IP

When reset

∗ High voltage drive transistor

∗

Low level

VFDP

• Diagram shows circuit

IP

construction for oscillation.

• During STOP feedback
resistor is disconnected,
and XTAL becomes "H"
level.

32kHz oscillation
circuit control

"1" when reset

Data
bus

RD (Port H)

Data
bus

IP

RD (Port H)

Clock
input

Oscillator

Oscillation

halted

prot input

2 pins

RST

1 pin

PH0/TX

Pull-up resistor

Low level

IP

Schmitt input

– 9 –

CXP827P16

Absolute Maximum Ratings (Vss = 0V)

Item Symbol Rating Unit Remarks

Supply voltage

Input voltage
Output voltage

Display output voltage

High level output current

High level
total output current

Low level output current

Low level total output current
Operating temperature
Storage temperature

VDD
Vpp
VIN
VOUT

VOD
IOH

IODH1
IODH2

∑IOH
∑IODH

IOL
IOLC
∑IOL
Topr
Tstg

–0.3 to +7.0

–0.3 to +13.0
–0.3 to +7.0∗
–0.3 to +7.0∗

1

1

VDD – 40 to VDD + 0.3

–5

–15

–35

–40

–100

15
20

100

–10 to +75

–55 to +150

V
V
V
V

V

mA
mA

mA
mA

mA
mA
mA
mA

°C
°C

Incorporated PROM

As P channel transistor is open drain,
VDD voltage is determined as reference.

Other than display putput pins∗2: per pin
Display output S13 to S20: per pin
Display output T0 to T7

T8/S28 to T15/S21: per pin
Total of other than display output pins
Total of display output pins
Port 1 pin
Large current port pin∗

3

Total of all pins

Allowable power dissipation

PD

1000

mW

∗1) VIN and VOUT must not exceed VDD+0.3V.
∗2) Specifies output current of general-purpose I/O ports.
∗3) The large current drive transistor is an N-ch transistor of Port C (PC).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be

conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.

– 10 –

CXP827P16

Recommended Operating Conditions (Vss = 0V)

Item Symbol Min. Max. Unit Remarks

Guaranteed operation range for high speed

V

mode (1/2, 1/4 frequency dividing clock)
Guaranteed operation range for low speed

V

mode (1/16 frequency dividing clock)

V

Guaranteed operation range with TEX clock
Guaranteed data hold operation range

V

during STOP

4

V

∗

1

V

∗

V

Hysteresis input∗

V

EXTAL pin∗

1

V

∗

V

Hysteresis input∗

V

EXTAL pin∗

2

3

2

3

°C

Supply voltage

High level
input voltage

Low level
input voltage

Operating temperature

4.5

3.5

VDD

2.7

2.5

Vpp Vpp = VDD
VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr

0.7VDD

0.8VDD

VDD – 0.4

0
0

–0.3

–10

VDD +0.3

0.3VDD

0.2VDD

5.5

5.5

5.5

5.5

VDD
VDD

0.4

+75

∗1) All regular input port (PA, PB4, PB7, PC, PH).
∗2) For pins RST, CS0, CS1, SI0, SI1 SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC.
∗3) Specifies only for external clock input.
∗4) Vpp should be the same voltage as VDD.

– 11 –

Electrical Characteristics
DC Characteristics

CXP827P16

(Ta = –10 to +75°C, Vss = 0V)

Item Symbol

High level
output voltage

Low level
output voltage

Input current

I/O
leak current

Display
output current

Open drain
output leak
current (P-CH
Tr off state)

VOH

VOL

IIHE
IILE
IIHT
IILT
IILR
IIH
IIL

IIZ

IOH

ILOL

Pin

PA, PB, PC,
PE5, PE6

PC

EXTAL

TEX

RST

PA to PC

PA to PC

∗

1

∗1,

PE0 to PE4

S13 to S20

S21/T15 to
S28/T8,
T0 to T7

S13 to S20,
S21/T15 to
S28/T8,
T0 to T7

Condition

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIH = 4.0V
VDD = 5.5V, VIL = 0.4V

VDD = 5.5V
VI = 0, 5.5V

VDD = 4.5V
VOH = VDD –2.5V

VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V

Min. Typ.

4.0

3.5

0.5

–0.5

0.1
–0.1
–1.5
–3.3

–8

–20

Max.

0.4

0.6

1.5
40

–40

10

–10

–400

50

±10

–20

Unit

V
V
V
V

V
µA
µA
µA
µA
µA
µA
µA

µA

mA

mA

µA

Pull-down
resistor

Supply
current

∗

S16 to S20,

RL

S21/T15 to
S28/T8,

VDD = 5V
VFDP = VDD – 35V

60

100

270

kΩ

T0 to T7

High-speed mode operation
(1/2 frequency dividing clock)

IDD1

20

40

mA

VDD = 5.5V, 10MHz crystal oscillation

(C1 = C2 = 15pF)

IDD2

2

IDDS1

VDD

VDD = 3V, 32kHz crystal oscillation

(C1 = C2 = 47pF)

SLEEP mode

VDD = 5.5V, 10MHz crystal oscillation

400

1.2

1000

8

µA

mA

(C1 = C2 = 15pF)

IDDS2

VDD = 3V, 32kHz

(C1 = C2 = 47pF)

crystal oscillation

9

30

µA

STOP mode

IDDS3

VDD = 5.5V,

termination of 10 MHz and

30

µA

32 kHz crystal oscillation.

– 12 –

Item Symbol Pin Min. Typ. Max. UnitCodition

CXP827P16

Input
capacitance

CIN

PA to PC,
PE0 to PE4,
PH, EXTAL,
XTAL, RST

1MHz clock
0V for pins other than the measured
pins

pF2010

∗1) In each pin of PA to PC, the input current is specified when pull-up resistor has been selected; leakage

current is specified when no resistor is selected.

∗2) All output pins are left open.

– 13 –

A

A

A

AC Characteristics
(1) Clock timing

CXP827P16

(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pin Conditions Min. Unit

System clock frequency

System clock input pulse width
System clock input

rise and fall time
Event count input clock

pulse width
Event count input clock

rise and fall time

System clock frequency

Event count input clock
input pulse width

Event count input clock
rise and fall time

∗ tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock

control registor (address: 00FEH).

fC

tXL,
tXH

tCR,
tCF

tEH,
tEL

tER,
tEF

fC

tTL,
tTH

tTR,
tTF

XTAL
EXTAL

EXTAL

EXTAL

EC

EC

TEX
TX

TEX

TEX

Fig. 1, Fig. 2
Fig. 1, Fig. 2

External clock drive
Fig. 1, Fig. 2

External clock drive
Fig. 3

Fig. 3
VDD = 2.7 to 5.5V

Fig. 2 (32kHz clock
applied condition)

Fig. 3

Fig. 3

1

37.5

tsys +

10

50∗

Typ.

32.768

Max.

10

200

20

20

MHz

ns

ns

ns

ms

kHz

µs

ms

tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Fig. 1. Clock timing

EXTAL

Fig. 2. Clock applied conditions

Crystal oscillation
Ceramic oscillation

EXTAL

AA

1 C2

C

Fig. 3. Event count clock timing

TEX
EC

XTAL

1/fc

t

XH tXLtCF tCR

32kHz clock applied condition

External clock

EXTAL

AA

74HCO4

XTAL

Crystal oscillation

TEX

AA

C1 C2

TX

DD – 0.4V

V

0.4V

0.8VDD

0.2VDD

EH tELtEF tER

t
tTH tTLtTF tTR

– 14 –

CXP827P16

(2) Serial transfer

Item

CS0 ↓→ SCK0 (CS1 ↓→ SCK1)
delay time

CS0 ↑→ SCK0 (CS1 ↑→ SCK1)
float delay time

CS0 ↓→ SO0 (CS1 ↓→ SO1)
delay time

CS0 ↑→ SO0 (CS1 ↑→ SO1)
float delay time

CS0 (CS1) high level width

SCK0 (SCK1) cycle time

SCK0 (SCK1)
High and Low level widths

SI0 (SI1) input setup time
(for SCK0 ↑ (SCK1 ↑) )

SI0 (SI1) input hold time

(for SCK0 ↑ (SCK1 ↑) )

SCK0 ↓→ SO0 (SCK1 ↓→ SO1)
delay time

(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Symbol Pin Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0
(SCK1)

SCK0
(SCK1)

SO0
(SO1)

SO0
(SO1)

CS0
(CS1)

SCK0
(SCK1)

SCK0
(SCK1)

SI0
(SI1)

SI0
(SI1)

SO0
(SO1)

Chip select transfer mode
(SCK0 (SCK1) = output mode)

Chip select transfer mode
(SCK0 (SCK1) = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode

Input mode
Output mode
Input mode
Output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode

Condition

tsys + 200

2tsys + 200

16000/fc

tsys + 100

8000/fc–5

0
100
200

tsys + 200

100

Max. Unit

tsys + 200

tsys + 200

tsys + 200

tsys + 200

tsys + 200

100

ns

ns

ns

ns

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns

Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the

control clock registor (address: 00FEH).

tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF+1TTL.

– 15 –

Fig. 4. Serial transfer CH0 timing

CXP827P16

tWHCS

CS0
(CS1)

SCK0
(SCK1)

SI0
(SI1)

0.2V

tDCSK

DD

tKCY

tKL tKH

tKSI

SIK

t

Input
data

0.8VDD

0.2VDD

0.8VDD

0.2VDD

0.8VDD

tDCSKF

0.8VDD

SO0
(SO1)

DCSO tKSO tDCSOF

t

Output
data

– 16 –

0.8VDD

0.2VDD

CXP827P16

(3) A/D converter characteristics (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pin Condition Min. Typ. Max. Unit

Resolution

8

Bits
Linearity error
Zero transition

voltage
Full-scale transition

voltage
Conversion time
Sampling time
Analog input voltage

VZT∗

VFT∗

tCONV
tSAMP

VIAN

1

2

AN0 to AN7

Fig. 5. Definition of A/D converter terms

FFH
FEH

Digital conversion value

01H
00H

Linearity error

Analog input

FTVZT

V

±3 LSB

Ta = 25°C
VDD = 5.0V

–10

10

70 mV

VSS = 0V

4910 mV

160/fADC∗

12/fADC∗

4970

3

3

5030

0

∗1)V ZT : Value at which the digital conversion value changes
  from 00 H to 01H and vice versa.
∗2)V FT : Value at which the digital conversion value changes
  from FE H to FFH and vice versa.
∗3)f ADC indicates the below values due to the bit 6 (CKS) of
 A/D control registor (ADC: 00F9 H) and the bit 7 (PCK1)
 and bit 6 (PCK0) of clock control registor (CLC: 00FE H)

CKS

PCK1, 0

00 (φ= fEX/2)

0 (φ/2 selection) 1 (φ selection)

fADC = fC/2

fADC = fC

µs
µs

VVDD

01 (φ= fEX/4)
11 (φ= fEX/16)

– 17 –

fADC = fC/4

fADC = fC/16

fADC = fC/2
fADC = fC/8

(4) Interruption, reset input (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pin Condition Min. Max. Unit

INT0

External interruption
High and Low level widths

tIH
tIL

INT1
INT2
INT3

1

µs

NMI

CXP827P16

Reset input Low level width

Fig 6. Interruption input timing

INT0
INT1
INT2
INT3
NMI
(NMI is specified only for
the falling edge)

Fig. 7. RST input timing

tRSL

RST

tIH tIL

0.8VDD

tIL tIH

tRSL

32/fc

µs

0.2VDD

RST

0.2VDD

– 18 –

Appendix

Fig. 8. Recommended oscillation circuit

CXP827P16

(i) Main clock

C1

Manufacturer

MURATA
MFG
CO., LTD.

RIVER
ELETEC
CO., LTD.

KINSEKI
LTD.

EXTAL

EXTAL

XTAL

XTAL

Rd

Rd

C

2

Model

CSA4.19MG
CSA8.00MTZ
CSA10.0MTZ
CST4.19MGW∗
CST8.00MTW∗
CST10.0MTW∗

HC-49/U03

HC-49/U (-S)

P3

(ii) Main clock

fc (MHz)

4.19

8.00

10.00

4.19

8.00

10.00

4.19

8.00

10.00

4.19

8.00

10.00

32.768kHz

EXTAL

XTAL

XTAL

Rd

C1 C2

C1 (pF) C2 (pF)

30

12

27

30

12

27

Rd (Ω)

20 20
50 22 1M (iii)

(iii) Sub clock

EXTAL

TEX

1 C2

C

example

0

0

0

Circuit

(i)

(ii)

(i)

XTAL

TX

Rd

The above model with an asterisk (∗) includes the capacitors (C1, C2).

Selection Guide

Option Item
Package
ROM capacitance
Reset pin pull-up resistor
High voltage drive output pin

pull-down resistor

Mask Product

64-pin plastic SDIP

12 Kbytes/16 Kbytes

Existent/Non-Existent
Existent/Non-Existent

– 19 –

CXP827P16S-1-

64-pin plastic SDIP

PROM 16 Kbytes

Existent

Existent (T0 to T7, S16 to S28),
Non-Existent (S13 to S15)

Characteristics Curves

CXP827P16

IDD vs. VDD

(fc = 10MHz, Ta = 25°C, Typical)

20.0

10.0

5.0

1.0

0.5

— Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

3

VDD — Supply voltage [V]

45

1/2 frequency
dividing mode

1/16 frequency
dividing mode

32kHz mode
(instruction)

SLEEP mode

32kHz
SLEEP mode

72

6

(VDD = 5V, Ta = 25°C, Typical)

20

15

10

— Supply current [mA]

DD

I

5

0

51015

fc — System clock [MHz]

IDD vs. fc

1/2 frequency dividing mode

1/16 frequency dividing mode
SLEEP mode

– 20 –

Package Outline Unit: mm

CXP827P16

64PIN SDIP (PLASTIC) 750mil

+ 0.4

57.6 – 0.1

64

132

0.5 ± 0.1

0.9 ± 0.15

1.778

33

+ 0.3

19.05

17.1 – 0.1

+ 0.4

4.75 – 0.1

0.5 MIN

3 MIN

+ 0.1

0.25 – 0.05

PACKAGE STRUCTURE

EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY

8.6g

SONY CODE
EIAJ CODE
JEDEC CODE

SDIP-64P-01

SDIP064-P-0750-A

MOLDING COMPOUND
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT

0° to 15°

– 21 –