Datasheet CXP82716, CXP82712 Datasheet (Sony)

Description

The CXP82712/82716 microcomputer is composed
of a 8-bit CPU, ROM, RAM, and I/O ports. These
chips feature many other high-performance circuits
in a single-chip CMOS design, including an A/D
converter, serial interface, timer/counter, time base
timer, fluorescent display controller/driver, remote
control receiver, PWM output circuit and 32kHz
timer/counter.

This device also includes sleep/stop functions which
can be used to achieve low power consumption.

Features

• Instruction set which supports a wide array of data types

— 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and

boolean bit operations.

• Minimum instruction cycle 400ns for 10MHz, 122µs for 32kHz operation

• On-chip ROM 12K bytes (CXP82712)

16K bytes (CXP82716)

• On-chip RAM 448 bytes (Including fluorescent display data area)

• Peripheral functions

— A/D converter 8-bit, 8-channel, successive approximation system

(conversion rate 32µs/10MHz)

— Serial interface On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer),

1 circuit 2-channel

— Timers 8-bit timer

8-bit timer/counter
19-bit time base timer
32kHz timer/counter

— Fluorescent display controller/driver 24 high voltage tolerance output ports

Maximum of 144 segments display available
1 to 16 digits dynamic display
Dimmer function
High voltage tolerance output (40V)
On-chip pull-down resistor (Mask option)

Hardware key scan function (Maximum of 8 × 8 key matrix available)
— Remote control receiver circuit On-chip 6-stage FIFO 8-bit pulse measurement counter
— PWM output 8-bit, 1-channel

• Interruption 13 factors, 13 vectors, multi-interruption possible

• Standby mode Sleep/stop

• Package 64-pin plastic SDIP

• Piggyback/evaluator CXP82700 64-pin ceramic SDIP

CMOS 8-bit Single Chip Microcomputer

– 1 –

E93Y23A79-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXP82712/82716

64 pin SDIP (Plastic)

Structure

Silicon gate CMOS IC

– 2 –

CXP82712/82716

A/D CONVERTER

FDP

CONTROLLER/

DRIVER

REMOCON

SERIAL

INTERFACE

UNIT

8 BIT TIMER/COUNTER 0

FIFO

FIFO

INTERRUPT CONTROLLER

SPC700

CPU CORE

ROM

12K/16K BYTES

PRESCALER/

TIME BASE TIMER

32kHz

TIMER/COUNTER

RAM

448 BYTES

CLOCK GEN./

SYSTEM CONTROL

8

PA0/AN0

to

PA7/AN7

T0 to T7

PE4/RMC

PB1/CS0

PB3/SI0

PB4/SO0

PB2/SCK0

PB6/SI1

PB7/SO1

PB5/SCK1

PE0/EC

PE0/INT0

PE1/INT1

PE2/INT2

PE3/INT3

PH1/TEX

PH0/TX

EXTAL

XTAL

RST

V

DD

Vss

PORT C

8

PC0 to PC7

PORT F

3

PF5 to PF7

PORT B

8

PB0 to PB7

PORT E

6

2

PE0 to PE4

PE5 to PE6

8

8

8

T8/S28

to

T15/S21

S13 to S20

V

FDP

8 BIT TIMER 1

RAM

80 BYTES

PORT A

8

PA0 to PA7

PB0/CS1

2

PE6/ADJ

PE6/TO

PE3/NMI

2

PORT H

2

PH0 to PH1

8 BIT PWM

PE5/PWM

Block Diagram

– 3 –

CXP82712/82716

Pin Assignment (Top View)

2
3
4
5
6
7
8
9

10

11
12
13
14
15
16
17
18
19

20

21

22

23

24

25

26

27

28

29

30

40
39
38
37
36
35
34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

63

64

61

62

1

PH0/TX

PH1/TEX

NC

PE6/ADJ/TO

PB0/CS1
PB1/CS0

PB2/SCK0

PB3/SI0

PB4/SO0

PB5/SCK1

PB6/SI1
PB7/SO1
PC0/KR0
PC1/KR1
PC2/KR2
PC3/KR3
PC4/KR4
PC5/KR5
PC6/KR6
PC7/KR7
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7

RST

EXTAL

XTAL

Vss

V

DD

PE5/PWM
PE4/RMC
PE3/INT3/NMI
PE2/INT2
PE1/INT1
PE0/EC/INT0
VFDP
T0
T1
T2
T3
T4
T5
T6
T7
T8/S28
T9/S27
T10/S26
T11/S25
T12/S24
T13/S23
T14/S22
T15/S21
S20
S19
S18
S17
S16
PF7/S15
PF6/S14
PF5/S13

Note) 1. NC (Pin 3) is always connected to VDD.

2. PH0/TX (Pin 1) is input port during port selection;
oscillation output during oscillation selection

– 4 –

CXP82712/82716

Pin Description

Symbol I/O Functions

I/O/Analog Input

PA0/AN0

to

PA7/AN7

(Port A)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

Analog inputs to A/D converter.
(8 pins)

I/O/Input

PC0/KR0

to

PC7/KR7

PE0/INT0/
EC0

PE1/INT1
PE2/INT2
PE3/INT3/

NMI
PE4/RMC
PE5/PWM

PE6/ADJ/TO

Input/Input/
Input

Input/Input
Input/Input
Input/Input/

Input
Input/Input
Output/Output

Output

(Port C)
8-bit I/O port. I/O can
be set in a bit unit.
Capable of driving
12mA sink current.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

(Port E)
Lower 5 bits are for
inputs; upper 2 bits are
for outputs.
(7 pins)

Key return input for FDP segment signal which
performs key scanning.

External event input to
timer/counter. (1 pin)

External interrupt
requests.
(4 pins)

Non-maskable interruption request input.
Input for remote control receiver circuit.
8-bit PWM output.

Output for timer/counter rectangular waveform
and 32kHz oscillation frequency division.

I/O/Input
I/O/Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/Input
I/O/Output

PB0/CS1
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1

(Port B)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)

Chip select input for serial interface (CH1).
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).

– 5 –

CXP82712/82716

Symbol I/O Functions

Output/Output

T8/S28

to

T15/S21

Dual purpose output for FDP timing and segment signals.

Output/Output

PF5/S13

to

PF7/S15

(Port F)
3-bit output port.
(3 pins)

Output

S16 to S20

Segment signal output for FDP.

Output

T0 to T7 Timing signal output for FDP.

Input

Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.

EXTAL

Provides voltage for FDP when on-chip resistor is selected under mask option.

VFDP

Output

XTAL

Input/Input

Crystal connectors for 32kHz timer/counter clock
oscillation circuit. Connect a 32kHz crystal oscillator
between TEX and TX. For usage as event input, connect
clock oscillation source to TEX, and leave TX open.

PH1/TEX

Input/OutputPH0/TX
Input System reset pin of active "L" level. RST is input pin.RST

NC.
Under normal operating conditions, connect to VDD.

NC

Vcc supply.

VDD

GND

Vss

(Port H)
2-bit input
port.
(2 pins)

Segment signal output for FDP.

– 6 –

CXP82712/82716

Port B

Data bus

RD (Port B)

Port B direction

IP

Port B data

"0" when reset

"0" when reset

∗

Schmitt input

CS0
CS1
SI0
SI1

∗

Pull-up transistors

approx. 100kΩ

Pull-up resistor

8 pins

Hi-Z

Hi-Z

When reset

PA0/AN0

to

PA7/AN7

PB0/CS1
PB1/CS0
PB3/SI0
PB6/SI1

Port B

Data bus

RD (Port B)

IP

Port B output
selection

"0" when reset

∗

Schmitt input

SCK in

Port B data

Port B direction

"0" when reset

"0" when reset

SCK OUT

Output enable

∗

Pull-up transistors

approx. 100kΩ

Pull-up resistor

4 pins

2 pins

Hi-Z

PB2/SCK0
PB5/SCK1

Data bus

RD (Port A)

Port A direction

IP

Port A data

Pull-up resistor

Port A input
selection

Input protection
circuit

"0" when reset

"0" when reset

"0" when reset

Input multiplexer

A/D converter

∗

Pull-up transistors

approx. 100kΩ

∗

I/O Circuit Format for Pins

Port A

Pin

Circuit format

– 7 –

CXP82712/82716

2 pins

Hi-Z

Hi-Z

Pin

When reset

Circuit format

PB4/SO0
PB7/SO1

PC0/KR0

to

PC7/KR7

8 pins

5 pins

Hi-Z

PE0/EC/INT0
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC

IP

Schmitt input

RD (Port E)

Data bus

EC/INT0
INT1
INT2
INT3/NMI
RMC

Data bus

RD (Port C)

Port C direction

IP

Port C data

"0" when reset

"0" when reset

∗2

∗1

∗

2

Pull-up transistors approx. 100kΩ

∗

1

Large current drive of 12mA possible

Pull-up resistor

Key input signal

Data bus

RD (Port B)

IP

Port B output
selection

"0" when reset

∗

Port B data

Port B direction

"0" when reset

SO

Output enable

∗

Pull-up transistors

approx. 100kΩ

Pull-up resistor

"0" when reset

Port E

Port C

Port B

– 8 –

CXP82712/82716

1 pin

PE5/PWM

Data bus

RD (Port E)

AAA

Port E output
selection

"0" when reset

AAA

Port E data

PWM

Output enable

"1" when reset

Port E

1 pin

High level

PE6/TO/ADJ

Data bus

Port E output
selection

"0" when reset

Port E data

"1" when reset

RD (Port E)

∗

ADJ signals are frequency division outputs
for 32kHz oscillation frequency adjustment.
ADJ2K provides usage as buzzer output.

Port E output
selection

"00" when reset

Port E output
selection

Output enable

TO

ADJ16K

ADJ2K

MPX

Port H

3 pins

Hi-Z or

Low level
When PD
resistor is

connected

PF5/S13

to

PF7/S15

Data bus

RD (Port F)

Port F data

("0" when reset)

∗

Segment output data

Output selection control signal

OP

Mask option

Pull-down
resistor

V

FDP

∗

High voltage tolerance transistor

Port F

High level

High level with
150kΩ resistor

when reset

( )

( )

When resetPin

Circuit format

– 9 –

CXP82712/82716

21 pins

Hi-Z or
Low level
When PD
resistor is

connected

S16 to S20
T15/S21

to
T8/S28
T0 to T7

∗

Segment output data

Output selection control signal
("0" when reset)

OP

Mask option

Pull-down
resistor

V

FDP

∗

High voltage tolerance transistor

2 pins

Oscillation

EXTAL
XTAL

IP

EXTAL

XTAL

• Diagram shows circuit
construction for oscillation.

• During stop feedback
resistor is disconnected.
At this time XTAL pin
outputs "H" level.

IP

2 pins

Oscillation

halted

port input

PH1/TEX
PH0/TX

IP

PH2/TEX

PH0/TX

32kHz oscillation
circuit control

"1" when reset

Data
bus

RD

Data
bus

RD

Clock
input

IP

1 pin

Low level

RST

Schmitt input

Pull-up resistor

Mask option

OP

IP

When resetPin

Circuit format

( )

– 10 –

CXP82712/82716

∗1

VIN and VOUT must not exceed VDD + 0.3V.

∗2

Specifies output current of general-purpose I/O ports.

∗3

The large current drive transistor is an N-ch transistor of Port C (PC).

Note) If the absolute maximum ratings are exceeded, the LSI could reach permanent breakdown. Also, observing

recommended operating conditions is desirable; otherwise, the LSI's reliability could be affected.

Supply voltage
Input voltage
Output voltage

VDD
VIN
VOUT

VOD
IOH

IODH1
IODH2

∑IOH
∑IODH

IOL
IOLC
∑IOL
Topr
Tstg
PD

VDD – 40 to VDD + 0.3

–5

–15

–35

–40

–100

15
20

100

–20 to +75

–55 to +150

1000

Display output voltage

High level output current

High level
total output current

Low level output current

Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation

–0.3 to +7.0

–0.3 to +7.0

∗1

–0.3 to +7.0

∗1

V
V
V

V

mA
mA

mA
mA

mA
mA
mA
mA

°C
°C

mW

Other than display output pins∗2: per pin
Display output S13 to S20: per pin
Display output T0 to T7,

T8/S28 to T15/S21: per pin
Total of pins other than display output pins
Total of display output pins
Port 1 pin
Large current port∗3: per pin
Entire pin total

As P channel transistor is open drain,
VDD voltage is determined as standard.

Item Symbol Rating Unit Remarks

Absolute Maximum Ratings (Vss = 0V)

– 11 –

CXP82712/82716

High level
input voltage

Low level
input voltage

Operating temperature

Supply voltage

5.5

5.5

5.5

5.5

VDD
VDD

VDD + 0.3

0.3VDD

0.2VDD

0.4

+75

V

V
V
V
V

V
V
V
V
V

°C

Item Symbol Min. Max. Unit Remarks

4.5

3.5

2.7

2.5

0.7VDD

0.8VDD

VDD – 0.4

0
0

–0.3

–20

VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr

High speed mode (1/2, 1/4 dividing clock)
guaranteed operation range

Low speed mode (1/16 dividing clock)
guaranteed operation range

Guaranteed operation range with TEX clock
Guaranteed data hold operation range

during stop

∗1

Hysteresis input

∗2

EXTAL pin

∗3

∗1

Hysteresis input

∗2

EXTAL pin

∗3

VDD

∗1

All regular input port (PA, PB4, PB7, PC, PH).

∗2

For pins RST, CS0, CS1, SCK0, SI0, SI1, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC.

∗3

Specifies only for external clock input.

Recommended Operating Conditions (Vss = 0V)

– 12 –

CXP82712/82716

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIH = 4.0V
VDD = 5.5V, VIL = 0.4V

VDD = 4.5V
VOH = VDD – 2.5V

VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V

VDD = 5V
VFDP = VDD – 35V

VDD = 5.5V
VI = 0, 5.5V

High level
output voltage

Display
output current

Open drain
output leak
current (P-CH
Tr off state)

Pull-down
resistor

∗3

Input/Output
leak current

4.0

3.5

0.5

–0.5

0.1
–0.1
–1.5

3.3

–8

–20

60

V
V
V
V

V
µA
µA
µA
µA
µA
µA
µA

mA

mA

µA

kΩ

µA

PC

PA, PB,
PC, PE5,
PE6

EXTAL

TEX

RST

∗1

PA to PC

∗2

Item Symbol Pin Condition Min.

PA to PC∗2,
PE0 to PE4
RST

∗2

S13 to S20
S21/T15 to
S28/T8
T0 to T7

IIZ

IIH
IIL

IOH

ILOL

RL

VOH

VOL

IIHE
IILE
IIHT
IILT
IILR

Low level
output voltage

Input current

100

Typ.

0.4

0.6

1.5
40

–40

10

–10

–400

50

–20

270

±10

Max. Unit

DC Characteristics

Electrical Characteristics

(Ta = –20 to +75°C, Vss = 0V)

S13 to S20
S21/T15 to
S28/T8
T0 to T7

S21/T15 to
S28/T8
T0 to T7

S13 to S20

Supply
current

∗4

20

35

9

10030µA

µA

40

mA

mA

µA

1.2

8

10

VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)

VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)

High-speed mode operation
(1/2 frequency dividing clock)

VDD

IDD1

IDD2

IDDS1

IDDS2

IDDS3

VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)

VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)

Sleep mode

Stop mode
VDD = 5.5V, 10MHz termination of
10MHz and 32kHz crystal oscillation.

– 13 –

CXP82712/82716

Item Symbol Pin Codition Min.

Pins other
than
S13 to S28,
T0 to T7,
PE5, PE6,
VDD, Vss,
VFDP

1MHz clock
0V for pins other than the
measured pins

CIN

Typ. Max. Unit

∗1

RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.

∗2

Pins PA to PC specify the input current when pull-up resistor has been selected; leakage current when no
resistor has been selected.

∗3

Applies when the on-chip pull-down resistor is selected under the mask option.

∗4

All output pins are left open.

Input
capacitance

pF2010

– 14 –

CXP82712/82716

∗

tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock

control register (address: 00FEH).

tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

EXTAL

t

XH tXLtCF tCR

0.4V

V

DD – 0.4V

1/fc

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

External clock

EXTAL

XTAL

74HC04

C

1 C2

32kHz clock applied condition
Crystal oscillation

TEX

TX

C

1

C2

AC Characteristics
(1) Clock timing

System clock frequency

System clock input pulse width
System clock input

rise and fall time
Event count input clock

pulse width
Event count input clock

rise and fall time

System clock frequency

Event count input clock
input pulse width

Event count input clock
rise and fall time

fC

tXL,
tXH

tCR,
tCF

tEH,
tEL

tER,
tEF

fC

tTL,
tTH

tTR,
tTF

XTAL
EXTAL

EXTAL

EXTAL

EC

EC

TEX
TX

TEX

TEX

MHz

ns

ns

ns

ms

kHz

µs

ms

Item Symbol Pins Conditions Min. Unit

Fig. 1, Fig. 2
Fig. 1, Fig. 2

External clock drive
Fig. 1, Fig. 2

External clock drive
Fig. 3

Fig. 3
VDD = 2.7 to 5.5V

Fig. 2 (32kHz clock
applied condition)

Fig. 3

Fig. 3

1

37.5

tsys + 50

∗

10

Typ.

32.768

Max.

10

200

20

20

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Fig. 2. Clock applied conditions

Fig. 1. Clock timing

TEX
EC

t

EH tELtEF tER

0.2VDD

0.8VDD

tTH tTLtTF tTR

Fig. 3. Event count clock timing

– 15 –

CXP82712/82716

(2) Serial transfer

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

CS0 ↓ → SCK0 (CS1 ↓ → SCK1)
delay time

CS0 ↑ → SCK0 (CS1 ↑ → SCK1)
float delay time

CS0 ↓ → SO0 (CS1 ↓ → SO1)
delay time

CS0 ↑ → SO0 (CS1 ↑ → SO1)
float delay time

CS0 (CS1) high level width

SCK0 (SCK1) cycle time

SCK0 (SCK1)
high and low level widths

SI0 (SI1) input seup time
(for SCK0 ↑ (SCK1 ↑) )

SI0 (SI1) input hold time
(for SCK0 ↑ (SCK1 ↑) )

SCK0 ↓ → SO0
(SCK1 ↓ → SO1) delay time

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0
(SCK1)

SCK0
(SCK1)

SO0
(SO1)

SO0
(SO1)

CS0
(CS1)

SCK0
(SCK1)

SCK0
(SCK1)

SI0
(SI1)

SI0
(SI1)

SO0
(SO1)

Input mode
Output mode
Input mode
Output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode

ns

ns

ns

ns

ns

Symbol Pin Min.

1.5tsys + 200

1.5tsys + 200

1.5tsys + 200

1.5tsys + 200

tsys + 200

2tsys + 200

16000/fc

tsys+100

8000/fc – 50

100
200

tsys + 200

100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tsys + 200

100

Max. Unit

Chip select transfer mode
(SCK0 (SCK1) = output mode)

Chip select transfer mode
(SCK0 (SCK1) = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode

Condition

Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the

clock control register (address: 00FEH).

tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.

– 16 –

CXP82712/82716

Fig. 4. Serial transfer timing

CS0
(CS1)

SCK0
(SCK1)

0.2V

DD

0.8VDD

tWHCS

tDCSK

tDCSKF

0.8VDD

0.2VDD

0.8VDD

tKCY

tKL tKH

0.8VDD

0.2VDD

SI0
(SI1)

t

SIK

tKSI

Input
data

t

DCSO

tKSO

tDCSOF

Output data

0.8V

DD

0.2VDD

SO0
(SO1)

– 17 –

CXP82712/82716

tCONV
tSAMP

VIAN

VZT

∗1

VFT

∗2

Ta = 25°C
VDD = 5.0V
VSS = AVSS = 0V

µs
µs

VVDD

AN0 to AN7

160/fADC

∗3

12/fADC

∗3

0

Item Symbol Pin Condition Min. Typ. Max. Unit

Bits

(3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss = 0V)

8

±3 LSB

150 mV

5120

70

5050

–10

4930 mV

Analog input

Linearity error

V

FTVZT

00H

01H

FEH

FFH

Digital conversion value

∗

1

VZT : Value at which the digital conversion value changes

from 00H to 01H and vice versa.

∗

2

VFT : Value at which the digital conversion value changes

from FEH to FFH and vice versa.

∗

3

fADC indicates the below values due to the Bit6 (CKS) of
A/D control register (address: 00F9H) and the Bit7 (PCK1)
and Bit6 (PCK0) of clock control register (address: 00FEH)

00 (φ = fEX/2)
01 (φ = fEX/4)
11 (φ = fEX/16)

fADC = fC/2
fADC = fC/4

fADC = fC/16

fADC = fC

CSK

PCK1, 0

0 (φ/2 selection) 1 (φ selection)

fADC = fC/2
fADC = fC/8

Conversion time
Sampling time
Analog input voltage

Linearity error
Zero transition

voltage
Full-scale transition

voltage

Resolution

Fig. 5. Definition of A/D converter terms

– 18 –

CXP82712/82716

External interruption
high and low level widths

Reset input low level width

INT0
INT1
INT2
INT3
NMI

RST

1

32/fc

µs

µs

Item Symbol Pin Condition Min. Max. Unit

tIH
tIL

tRSL

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

0.2VDD

0.8VDD

tIH tIL

INT0
INT1
INT2
INT3
NMI
(NMI is specified only for
the falling edge)

tIL tIH

Fig 6. Interruption input timing

tRSL

0.2VDD

RST

Fig. 7. RST input timing

Fig. 8. Recommended oscillation circuit

– 19 –

CXP82712/82716

Appendix

C1

A

EXTAL

XTAL

C

2

Rd

A

EXTAL

XTAL

Rd

(i) Main clock

A

EXTAL

XTAL

C1 C2

Rd

XTAL

(ii) Main clock

A

EXTAL

XTAL

C

1 C2

Rd

A

TEX

TX

(iii) Sub clock

Manufacturer

MURATA
MFG
CO., LTD.

RIVER
ELETEC
CORPORATION
.

KINSEKI
LTD.

Model

CSA4.19MG
CSA8.00MTZ

CST4.19MGW

∗

CST8.00MTW

∗

HC-49/U03

HC-49/U (-S)

P3

fc (MHz)

4.19

8.00

10.00

4.19

8.00

10.00

4.19

8.00

10.00

4.19

8.00

10.00

20 20
50 22 1M (iii)

32.768kHz

30

12

27

30

12

27

0

0

0

C1 (pF) C2 (pF)

Rd (Ω)

Circuit

example

(i)

CSA10.0MTZ

(ii)

CST10.0MTW

∗

(i)

Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).

Item

Content
Reset pin pull-up resistor
High tension proof pull-down resistor

Non-existent
Non-existent

Existent

Existent (selected every pin)

Mask Option Table

AA

AA

AA

AA

AA

– 20 –

CXP82712/82716

Characteristics Curves

0

15

10

5

5 10 15

20

(100µA)

3

4 5

6

0.1

5.0

1.0

72

0.05

(50µA)

0.01

(10µA)

0.5

10.0

20.0

VDD – Supply voltage [V]

I

DD

– Supply current [mA]

IDD vs. VDD

(fc = 10MHz, Ta = 25°C, Typical)

Sleep mode

32kHz mode
(instruction)

32kHz
Sleep mode

fc – System clock [MHz]

I

DD

– Supply current [mA]

IDD vs. fc

(VDD = 5V, Ta = 25°C, Typical)

1/2 dividing mode

1/2 dividing mode

1/16 dividing mode

1/16 dividing mode

Sleep mode

1/4 dividing mode

1/4 dividing mode

– 21 –

CXP82712/82716

Package Outline Unit: mm

PACKAGE STRUCTURE

PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS

SONY CODE
EIAJ CODE
JEDEC CODE

SDIP-64P-01

42 ALLOY

SOLDER PLATING

EPOXY RESIN

64PIN SDIP (PLASTIC)

SDIP064-P-0750

57.6 – 0.1

+ 0.4

64

33

1 32

1.778

19.05

17.1 – 0.1

+ 0.3

0° to 15°

0.25 – 0.05

+ 0.1

0.5 MIN

4.75 – 0.1

+ 0.4

3.0 MIN

0.5 ± 0.1

0.9 ± 0.15

8.6g