Page 1
CXP824P40A
CMOS 8-bit Single Chip Microcomputer
Description
The CXP824P40A is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer counter, fluorescent display tube,
controller/driver, remote control reception circuit, CTL
duty detection circuit, 14-bit PWM output and highspeed output circuit besides the basic configurations
of 8-bit CPU, PROM, RAM, and I/O port.
The CXP824P40A also provides sleep/stop function
that enables lower power consumption.
CXP824P40A is the PROM-incorporated version of
the CXP82440A with built-in mask ROM. This
provides the additional feature of being able to write
directly into the program. Thus, it is most suitable for
evaluation use during system development and for
small-quantity production.
Structure
Silicon gate CMOS IC
100 pin QFP (Plastic)
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle 400ns at 10MHz operation
122µs at 32kHz operation
• Incorporated PROM capacity 40K bytes
• Incorporated RAM capacity 1120 bytes (including fluorescent display area)
• Peripheral functions
— A/D converter 8-bit, 8-channel, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface Incorporated 8-bit, 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock sync type, 1 channel
— Timers 8-bit timer, 8-bit timer/counter, 19-bit time base timer
16-bit capture timer/counter, 32kHz timer/counter
— Fluorescent display tube controller/driver Maximum of 384 segments display possible
1 to 16-digit dynamic display
Dimmer function
High voltage drive output (40V)
On-chip pull-down resistor (Mask option)
Hardware key scan function
(Maximum of 16 × 8 key matrix compatible)
— Remote control receiving circuit Incorporated noise elimination circuit
8-bit measurement counter with on-chip 6-stage FIFO
— PWM output 14 bits, 1 channel
— CTL duty detection circuit
— High-speed output circuit RTG 4 pins
• Interruption 19 factors, 15 vectors, multi-interruption possible
• Standby mode SLEEP/STOP
• Package 100-pin plastic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94Z17-PP
Page 2
CXP824P40A
V
SS
Vpp
V
DD
RST
XTAL
EXTAL
TX
TEX
PB0 to PB6
PA0 to PA7
8
PORT A
PB7
7
PORT B
CLOCK GEN./
SYSTEM CONTROL
SPC 700
CPU CORE
PC0 to PC7
8
PORT C
RAM
1120 BYTES
PROM
40K BYTES
PD0 to PD7
8
PE0 to PE5
6
PORT D
PE6 to PE7
2
PF0 to PF7
8
PORT E
32kHz
PRESCALER/
PG0 to PG7
8
PORT F
PORT G
TIMER/COUNTER
TIME BASE TIMER
PH0 to PH7
8
PORT H
PULSE
REALTIME
GENERATOR
PI0 to PI7
8
PORT I
4
CH0 CH1
PG3/RTO3
PG0/RTO0 to
PE3/INT3/NMI
PE2/INT2
PE1/EC1/INT1
PE0/EC0/INT0
AV
REF
AV
SS
RAM
A/D CONVERTER
FDP
CONTROLLER/
8
8
PA7/AN7
8
T0 to T7
PA0/AN0 to
T15/S24 to T8/S31
DRIVER
14 BIT PWM GENERATOR
24
FDP
V
PE6/PWM
PD0/S0 to PI7/S23
INTERRUPT CONTROLLER
2
2 2
FIFOREMOCON
CTL DUTY DET
FIFO
UNIT 0
SERIAL
INTERFACE
PE5/CTL
PE7/DDO
PE4/RMC
PB3/SI0
PB1/CS0
PB4/SO0
PB2/SCK0
2
2
8 BIT TIMER/COUNTER 0
SERIAL INTERFACE UNIT 1
PB6/SI1
PB7/SO1
PB5/SCK1
2
8 BIT TIMER 1
16 BIT CAPTURE
TIMER/COUNTER 2
PE7/TO
PB0/CINT
PE0/INT0/EC0
PE7/ADJ
PE1/INT2/EC1
Block Diagram
– 2 –
Page 3
Pin Assignment (Top View)
100
PG6
PG7
PE0/EC0/INT0
99
98
97
PG5
96
PG3/RTO3
PG4
95
PG1/RTO1
PG2/RTO2
93
94
Vss
PG0/RTO0
92
91
90
Vpp
89
DD
V
88
FDP
V
87
T0
86
T1
85
T2
84
T3
83
T4
82
T5
CXP824P40A
T6
81
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5/CTL
PE6/PWM
PE7/TO/DDO/ADJ
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0/KR0
PC1/KR1
PC2/KR2
PC3/KR3
PC4/KR4
PC5/KR5
PC6/KR6
PC7/KR7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
49
50
80
75
74
73
72
65
62
61
79
78
77
76
71
70
69
68
67
66
64
63
60
59
58
57
56
55
54
53
52
51
T7
T8/S31
T9/S30
T10/S29
T11/S28
T12/S27
T13/S26
T14/S25
T15/S24
PI7/S23
PI6/S22
PI5/S21
PI4/S20
PI3/S19
PI2/S18
PI1/S17
PI0/S16
PF7/S15
PF6/S14
PF5/S13
PF4/S12
PF3/S11
PF2/S10
PF1/S9
PF0/S8
PD7/S7
PD6/S6
PD5/S5
PD4/S4
PD3/S3
1
2
3
4
5
6
7
8
9
35
31
32
33
34
36
37
38
39
40
41
42
43
44
45
46
47
48
PH7
PA1/AN1
PA0/AN0
PA3/AN3
PA2/AN2
PA5/AN5
PA4/AN4
RST
XTAL
EXTAL
Vss
TEX
PA6/AN6
TX
Note) 1. Vpp (Pin 90) must be connected to VDD.
2. Vss (Pins 41 and 91) are both connected to GND.
– 3 –
REF
AV
PA7/AN7
AVss
PD1/S1
PD0/S0
PD2/S2
Page 4
Pin Description
Pin code I/O Functions
(Port A)
PA0/AN0
to
PA7/AN7
I/O/
Analog input
8-bit I/O port. I/O can
be set in single bit
units.
Analog inputs to A/D converter. (8 pins)
(8 pins)
CXP824P40A
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0/KR0
to
PC7/KR7
PD0/S0
to
PD7/S7
PE0/INT0/
EC0
PE1/INT1/
EC1
PE2/INT2
PE3/INT3/
NMI
PE4/RMC
PE5/CTL
I/O/Input
I/O/Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/Input
Output/Output
I/O/Input
Output/Output
Input/Input/Input
Input/Input/Input
Input/Input
Input/Input/Input
Input/Input
Input/Input
(Port B)
8-bit I/O port. I/O for
lower 7 bits can be set
in a unit of single bits.
Uppermost bit (PB7) is
for output only.
(8 pins)
(Port C)
8-bit I/O port. I/O can
be set in a unit of single
bits. Capable of driving
12mA sync current.
(8 pins)
(Port D)
8-bit output port.
(8 pins)
(Port E)
8-bit port. Lower 6 bits
are for inputs; upper
2 bits are for outputs.
(8 pins)
Capture input to 16-bit timer/counter.
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
Serves as key return inputs when operating
key scan with FDP segment signal.
FDP segment signal outputs.
External event inputs for
Inputs for
external
timer/counter.
(2 pins)
interruption
request.
(4 pins)
Non-maskable interruption
request input.
Remote control reception circuit input.
Input for CTL duty direction circuit.
PE6/PWM
PE7/TO/
DDO/ADJ
PF0/S8
to
PF7/S15
PG0/RTO0
to
PG3/RTO3
PG4 to PG7
Output/Output
Output/Output/
Output/Output
Output/Output
I/O/Output
I/O
14-bit PWM output.
Output for the 16-bit timer/counter rectangular
waves, CTU duty detection, and 32kHz
oscillation frequency demultiplication.
(Port F)
8-bit output port.
FDP segment signal outputs.
(8 pins)
(Port G)
8-bit I/O port. I/O can
be set in a unit of single
bits. Data for the lower
Outputs for real-time pulse generator (RTG).
Functions as high-precision, real-time pulse
output port.
(4 pins)
4 bits are gated with the
contents of RTO or OR-gate output. (8 pins)
– 4 –
Page 5
Pin code I/O Functions
(Port H)
I/OPH0 to PH7
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
CXP824P40A
PI0/S16
to
PI7/S23
T8/S31
to
T15/S24
T0 to T7
VFDP
EXTAL
XTAL
TEX
TX
RST
AVREF
AVSS
VDD
Vpp
Output/Output
Output/Output
Output
Input
Output
Input
Output
Input
Input
(Port I)
8-bit output ports.
FDP segment signal outputs.
(8 pins)
Outputs for FDP timing (digit) signals/segment signals.
FDP timing signal outputs.
FDP voltage supply when incorporated resistor is set by mask option.
Crystal connectors system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to
XTAL.
Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz
crystal oscillator between TEX and TX. For usage as event input, attach
clock source to TEX, and open TX.
Low-level active, system reset.
Reference voltage input for A/D converter.
A/D converter GND.
Vcc supply.
VCC supply for incorporated PROM writing.
Connect to VDD during normal operation.
VSS
GND.
– 5 –
Page 6
I/O Circuit Format for Pins
CXP824P40A
Pin
PA0/AN0
to
PA7/AN7
8 pins
Port A
Port B
Data bus
Circuit format
Port A data
Port A direction
“0” when reset
RD (Port A)
Port A input selection
“0” when reset
A/D converter
Port B data
Input protection circuit
Input multiplexer
IP
When reset
Hi-Z
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
4 pins
PB2/SCK0
PB5/SCK1
Port B
Data bus
Port B direction
“0” when reset
Data bus
RD (Port B)
SCK OUT
Output enable
Port B output selection
“0” when reset
Port B data
Port B direction
“0” when reset
CINT
CS0
SI0
SI1
Schmitt input
Schmitt input
IP
Hi-Z
IP
Hi-Z
2 pins
RD (Port B)
SCK in
– 6 –
Page 7
CXP824P40A
Pin
PB4/SO0
1 pin
PB7/SO1
Port B
Ouput enable
Port B output selection
“0” when reset
Port B data
Port B direction
“0” when reset
Data bus
RD (Port B)
Port B
Output enable
Port B output selection
“1” when reset
SO
SO
Circuit format
Internal reset signal
When reset
Hi-Z
IP
∗
High level
1 pin
PC0/KR0
to
PC7/KR7
8 pins
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE4/CTL
“1” when reset
Data bus
Port C
Data bus
Port E
Port B data
RD (Port B)
Port C data
Port C direction
“0” when reset
RD (Port C)
Key input signal
Schmitt input
IP
∗
Pull-up transistor approx.
200kΩ
∗
IP
∗
High current drive of 12mA possible
EC0/INT0
EC1/INT1
INT2
INT3/NMI
RMC
CTL
Data bus
Hi-Z
Hi-Z
6 pins
RD (Port E)
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Page 8
CXP824P40A
Pin
PE6/PWM
1 pin
PE7/TO/
DDO/ADJ
1 pin
Port E
Port E output selection
“0” when reset
Port E data
“1” when reset
Data bus
Port E
Output enable
TO
DDO
∗
ADJ16K
∗
ADJ2K
Port E output selection
Port E output selection
“00” when reset
Port E output selection
“0” when reset
Port E data
“1” when reset
Data bus
RD (Port E)
PWM
RD (Port E)
0
1
MPX
2
3
Circuit format
∗
ADJ signal is a frequency demultiplication
output for 32kHz oscillation frequency
adjustment.
ADJ2 can be used for buzzer output.
When reset
High level
High level
PG0/RTO0
to
PG3/RTO3
4 pins
PG4 to PG7
PH0 to PH7
12 pins
Port G
Port G
Port H
Data bus
Data bus
RTO data
“0” when reset
Port G data
Port G direction
“0” when reset
RD (Port G)
Port G or Port H data
Port G or Port H direction
“0” when reset
RD (Port G or Port H)
Hi-Z
IP
IP
Hi-Z
– 8 –
Page 9
CXP824P40A
Pin
PD0/S0
to
PD7/S7
PF0/S8
to
PF7/S15
PI0/S16
to
PI7/S23
24 pins
T15/S24
to
T8/S31
T0 to T7
16 pins
Port D
Port F
Port I
Output selection control signal
Data bus
Output selection control signal
Segment output data
(“0” when reset)
Data for Port D, F, or I
“0” when reset
RD (Port D, F, or I)
Segment output data
(“0” when reset)
Circuit format
Pull-down resistor
∗
Pull-down resistor
∗
High voltage drive transistor
∗
OP
Mask option
High voltage drive transistor
∗
OP
Mask option
V
FDP
When reset
Hi-Z or
Low level
(when PD
resistance is
added)
FDP
V
Hi-Z or
Low level
(when PD
resistance is
added)
EXTAL
XTAL
2 pins
TEX
TX
2 pins
RST
1 pin
EXTAL
XTAL
TEX
TX
• Diagram shows circuit
IP
IP
IP
IP
composition during
oscillation.
• Feedback resistor is
removed during stop.
• Diagram shows circuit
composition during
oscillation.
Oscillation
Oscillation
• When the operation of the oscillation
circuit is stopped by the software, the
feedback resistor is removed, and TEX
and TX become “Low” level and “High”
level respectively.
Pull-up resistor
Hi-Z or
High level
OP
Mask option
IP
Schmitt input
(when pull-up
resistance is
added)
– 9 –
Page 10
CXP824P40A
Absolute Maximum Ratings (Vss = 0V reference)
Item Symbol Rating Unit Remarks
Supply voltage
Input voltage
Output voltage
Display output voltage
High level output current
High level total output
current
Low level output current
Low level total output current
Operating temperature
VDD
Vpp
AVss
VIN
VOUT
VOD
IOH
IODH1
IODH2
∑IOH
∑IODH
IOL
IOLC
∑IOL
Topr
–0.3 to +7.0
–0.3 to +13.0
–0.3 to +0.3
–0.3 to +7.0
–0.3 to +7.0
∗1
∗1
VDD – 40 to VDD + 0.3
–5
–15
–35
–40
–100
15
20
100
–20 to +75
V
V
Incorporated PROM
V
V
V
As P channel transistor is open drain,
V
VDD is reference.
mA
All pins excluding outputs∗2(value per pin)
mA
Display outputs S0 to S23 (value per pin)
Display outputs T0 to T7, and T8/S31 to
mA
T15/S24 (value per pin)
mA
Total for all pins excluding display outputs
mA
Total for all display outputs
mA
Port 1
mA
High current Port 1
mA
Total for all output pins
∗3
°C
Storage temperature
Allowable power dissipation
∗
1) VIN and VOUT must not exceed VDD + 0.3V.
∗
2) Specifies output current of general-purpose I/O ports.
∗
3) The high current drive transistor is the N-CH transistor of Port C (PC).
Tstg
PD
–55 to +150
600
°C
mW
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be
conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.
– 10 –
Page 11
CXP824P40A
Recommended Operating Conditions (Vss = 0V reference)
Item Symbol Min. Max. Unit Remarks
High-speed mode
V
Guaranteed operation range
Low-speed mode
V
Guaranteed operation range
Guaranteed operation range with TEX
V
clock
Guaranteed data hold range during STOP
V
∗4
V
∗1
V
Hysteresis input
V
EXTAL
V
∗1
V
Hysteresis input
V
EXTAL
V
∗3
∗3
∗2
∗2
Supply voltage
High level input
voltage
Low level input
voltage
VDD
Vpp
VIH
VIHS
VIHEX
VIL
VILS
VILEX
4.5
3.5
2.7
2.5
Vpp = VDD
0.7VDD
0.8VDD
VDD – 0.4
0
0
–0.3
5.5
5.5
5.5
5.5
VDD
VDD
VDD + 0.3
0.3VDD
0.2VDD
0.4
Operating temperature
∗
1) Value for each pin of normal input port (PA, PB4, PC, PG, PH).
∗
2) Value of the following pins: RST, CINT, CS0, SCK0, SCK1, SI0, SI1, EC0/INT0, EC1/INT1, INT2,
Topr
–10
+75
°C
INT3/NMI, RMC, CTL.
∗
3) Specifies only during external clock input.
∗
4) Vpp and VDD should be set a same voltage.
– 11 –
Page 12
Electrical Characteristics
CXP824P40A
DC Characteristics
Item Symbol Pins Conditions Min.
High level
output current
Low level
output current
VOH
VOL
IIHE
PA, PB,
PC, PE6,
PE7, PG,
PH
PC
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
EXTAL
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V
VIL = 0.4V
Input current
IILE
IIHT
IILT
IILR
TEX
RST
S0 to S23
Display output
current
IOH
S24/T15 to
S31/T8,
VDD = 4.5V
VOH = VDD – 2.5V
T0 to T7
Open drain output
leakage current
(P-CH Tr off
state)
ILOL
S24/T15 to
S31/T8,
T0 to T7
VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V
(Ta = –10 to +75°C, Vss = 0V reference)
Typ.
4.0
3.5
0.5
–0.5
0.1
–0.1
–1.5
–8
–20
Max. Unit
V
V
0.4
0.6
1.5
40
–40
10
–10
–400
V
V
V
µA
µA
µA
µA
µA
mA
mA
–20
µA
Pull-down
resistance
I/O
leakage current
RL
IIZ
S24/T15 to
S31/T8,
T0 to T7
PA to PC,
PE, PG, PH
VDD = 5V
VFDP = VDD – 35V
VDD = 5.5V
VI = 0, 5.5V
60
100
270
±10
kΩ
µA
– 12 –
Page 13
CXP824P40A
Item Symbol Pins Conditions Min. Typ. Max. Unit
High speed mode operation
IDD1
(1/2 frequency demultiplier clock)
20 40 mA
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
SLEEP mode
VDD = 5.5V, 10MHz crystal
Power supply
current
∗
IDD2
IDDS1
VDD
oscillation (C1 = C2 = 15pF)
IDDS2
IDDS3
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
STOP mode
V
DD
= 5.5V, 10MHz crystal oscillation;
and termination of 32kHz oscillation
Pins other
than
Input
capacity
CIN
S0 to S31,
T0 to T7,
PB7, PE6,
AVREF,
Clock 1MHz
0V for all pins excluding
measured pins
AVSS, VFDP,
VDD, VSS
∗
When all pins are open.
The leakage carrent is not specified because PB7 is dedicated for output.
450 1100 µA
1.2 8 mA
930µA
30 µA
10 20
pF
– 13 –
Page 14
A
A
A
AC Characteristics
(1) Clock timing
CXP824P40A
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pin Conditions Min. Unit
System clock frequency
System clock input pulse width
System clock input rise time,
fall time
Event count input clock
pulse width
Event count input clock
rise time, fall time
System clock frequency
Event count input
pulse width
Event count input rise time,
fall time
∗
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control
clock register (address: 00FEH).
fC
tXL
tXH
tCR
tCF
tEH
tEL
tER
tEF
fC
tTL
tTH
tTR
tTF
XTAL
EXTAL
EXTAL
EXTAL
EC0,
EC1
EC0,
EC1
TEX
TX
TEX
TEX
Fig. 1, Fig. 2
Fig. 1, Fig. 2
External clock drive
Fig. 1, Fig. 2
External clock drive
Fig. 3
Fig. 3
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
application condition)
Fig. 3
Fig. 3
1
37.5
tsys + 50
10
∗
32.768
Typ.
Max.
10
200
20
20
MHz
ns
ns
ns
ms
kHz
µs
ms
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Fig. 1. Clock timing
EXTAL
Fig. 2. Clock application conditions
Crystal oscillation
Ceramic oscillation
EXTAL
AA
C
1 C2
Fig. 3. Event count clock timing
TEX
EC0
EC1
XTAL
1/fc
XH tXLtCF tCR
t
32kHz clock application condition
External clock
EXTAL
AA
74HC04
XTAL
Crystal oscillation
TEX
AA
C1 C2
DD – 0.4V
V
0.4V
TX
0.8VDD
0.2VDD
t
EH tELtEF tER
tTH tTLtTF tTR
– 14 –
Page 15
CXP824P40A
(2) Serial transfer (CH0) (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
CS0 ↓ → SCK0
delay time
CS0 ↑ → SCK0
float delay time
CS0 ↑ → SO0
delay time
CS0 ↑ → SO0
float delay time
CS0 High level width
SCK0 cycle time
SCK0
High, Low level width
SI0 input set-up time
(for SCK0 ↑)
SI0 input hold time
(for SCK0 ↑)
SCK0 ↑ → SO0
delay time
Symbol Pin Min.
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK0
SCK0
SO0
SO0
CS0
SCK0
SCK0
SI0
SI0
SO0
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys + 200
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
200
tsys + 200
100
Max. UnitCondition
tsys + 200
tsys + 200
tsys + 200
tsys + 200
tsys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
control clock register (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 15 –
Page 16
Fig. 4. Serial transfer CH0 timing
CXP824P40A
tWHCS
CS0
SCK0
DD
0.2V
tKCY
tDCSK tDCSKF
tKL tKH
0.8VDD
0.2VDD
SIK tKSI
t
0.8VDD
0.8VDD
SI0
SO0
0.8VDD
Input data
0.2VDD
t
DCSO tKSO tDCSOF
Ouput data
0.8V
0.2VDD
DD
– 16 –
Page 17
CXP824P40A
Serial transfer (CH1) (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
SCK1 cycle time
SCK1
High, Low level width
SI1 input set-up time
(for SCK1 ↑)
SI1 input hold time
(for SCK1 ↑)
Symbol Pin Condition Min. Max. Unit
tKCY
tKH
tKL
tSIK
tKSI
SCK1
Input mode
Ouput mode
Input mode
SCK1
Ouput mode
SCK1 input mode
SI1
SCK1 ouput mode
SCK1 input mode
SI1
SCK1 ouput mode
1000
16000/fc
400
8000/fc – 50
100
200
200
100
SCK1 input mode
SCK1 ↓ → SO1 delay time
tKSO
SO1
SCK1 ouput mode
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY
200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1
SI1
SO1
tKL tKH
tSIK
Input data
tKSO
0.8VDD
0.2VDD
0.8VDD
0.2VDD
tKSI
0.8VDD
0.2VDD
Output data
– 17 –
Page 18
(3) A/D converter characteristics
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
Item Symbol Pin Condition Min. Typ. Max. Unit
CXP824P40A
Resolution
Linearity error
Zero transition
voltage
Full-scale
transition voltage
Conversion time
Sampling time
Reference input voltage
Analog input voltage
∗1
VZT
∗2
VFT
tCONV
tSAMP
VREF
VIAN
AVREF
AN0 to AN7
IREF
AVREF current
AVREF
IREFS
Fig. 6. Definition of A/D converter terms
Ta = 25°C
VDD = 5.0V
VSS = AVSS = 0V
Operation mode
SLEEP mode
STOP mode
32kHz operation mode
8
±3 LSB
–10
4910 mV
160/fADC
12/fADC
∗3
∗3
10
4970
VDD – 0.5
0
0.6
70 mV
5030
VDD
AVREF
1.0
10 µA
Bits
µs
µs
V
V
mA
FFH
FEH
Digital conversion value
01H
00H
Linearity error
Analog input
∗
1) VZT: Value at which the digital transfer value changes
from 00H to 01H and vice versa.
∗
2) VFT: Value at which the digital transfer value changes
from FEH to FFH and vice versa.
∗
3) fADC indicates the below values due to ADC operation
clock selection (ADCS: Bit 6 of address 00F9H).
During PS2 selection, fADC = fc/2
During PS1 selection, fADC = fc
V
FTVZT
– 18 –
Page 19
(4) Interruption, reset input (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pin Condition Min. Max. Unit
INT0
External interruption
High, Low level width
tIH
tIL
INT1
INT2
1
µs
NMI/INT3
CXP824P40A
Reset input Low level width
Fig. 7. Interruption input timing
INT0
INT1
INT2
NMI/INT3
(NMI specifies only for the
falling edge)
Fig. 8. RST input timing
tRSL
RST
tIH tIL
0.8VDD
tIL tIH
tRSL
32/fc
µs
0.2VDD
RST
0.2VDD
(5) Others (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
CLK input
High, Low level width
Symbol Pin Condition Min. Max. Unit
tCTH
tCTL
CTL
tsys = 2000/fc tsys + 200
ns
Fig. 9. Other timing
tCTH tCTL
CTL
0.8VDD
0.2VDD
– 19 –
Page 20
Appendix
A
A
A
A
Fig. 10. Recommended oscillation circuit
CXP824P40A
(i) Main clock
EXTAL
AA
C1
Manufacturer
MURATA
MFG
CO., LTD.
RIVER
ELETEC
CO., LTD
KINSEKI
LTD.
XTAL
Rd
2
C
CSA4.19MG
CSA8.00MTZ
CSA10.0MTZ
CST4.19MGW
CST8.00MTW
CST10.0MTW
HC-49/U03
HC-49/U (-S)
Model
(ii) Main clock
fc (MHz)
∗
∗
∗
EXTAL
AA
C
1 C2
4.19
8.00
10.00
4.19
8.00
10.00
4.19
8.00
10.00
4.19
8.00
10.00
(iii) Sub clock
XTAL
XTAL
Rd
C1 (pF) C2 (pF) Rd (Ω)
30
12
27
20 20
30
12
27
AAA
AAA
C
EXTAL
TEX
1
0
0
0
XTAL
TX
Rd
C2
Circuit
example
(i)
(ii)
(i)
P3
Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).
Mask option table
Option
Package
ROM capacitance
Reset pin pull-up resistance
High voltage drive pin pull-up resistor
32.768kHz
32K bytes/40K bytes
Existent/non-existent
Existent/non-existent
50 22
Mask product
100-pin plastic QFP
– 20 –
1M
CXP824P40Q-1-
100-pin plastic QFP
PROM 40K bytes
Non-existent (S0/PD0 to S23/PI7)
Existent (T0 to T15/S24)
(iii)
Existent
Page 21
Package Outline Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.4
17.9 ± 0.4
14.0 – 0.01
+ 0.1
0.15 – 0.05
15.8 ± 0.4
CXP824P40A
A
SONY CODE
EIAJ CODE
JEDEC CODE
0.65
0° to 15°
±0.12
DETAIL A
QFP-100P-L01
∗QFP100-P-1420-A
0.15
(16.3)
0.8 ± 0.2
M
+ 0.35
2.75 – 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER PLATING
COPPER / 42 ALLOY
1.4g
– 21 –
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