CMOS 8-bit Single Chip Microcomputer
Description
The CXP82032/82040/82052/82060 is a CMOS 8bit single chip microcomputer integrating on a single
chip an A/D converter, serial interface, timer/counter,
time-base timer, capture timer/counter, fluorescent
display panel controller/driver, remote control
reception circuit, and PWM output besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O port.
The CXP82032/82040/82052/82060 also provides
sleep/stop function that enables lower power
consumption.
Features
• Wide-range instruction system (213 instructions)
to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle 250ns at 16MHz operation
122µs at 32kHz operation
• Incorporated ROM capacity 32k bytes (CXP82032)
40k bytes (CXP82040)
52K bytes (CXP82052)
60K bytes (CXP82060)
• Incorporated RAM capacity 3984 bytes (including fluorescent display area)
• Peripheral functions
— A/D converter 8 bits, 8 channels, successive approximation method
(Conversion time of 3.25µs/16MHz)
— Serial interface Buffer RAM incorporated (Auto transfer for 1 to 32 bytes), 1 channel
8-bit clock synchronized type (MSB/LSB first selectable), 1 channel
Start-stop synchronized type (UART), 1 channel
— Timers 8-bit timer, 8-bit timer/counter, 19-bit time-base timer
16-bit capture timer/counter, 32kHz timer/counter
—
Fluorescent display panel controller/driver
Supports the universal grid fluorescent display panel.
High voltage drive output port of 56 pins (40V)
Maximum of 640 segments display possible
Display timing number of 1 to 20
Dimmer function
Incorporated pull-down resistor (Mask option)
Hardware key scan function (Maximum of 16 × 8 key matrix
supportable)
— Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO
— PWM output 14 bits, 1 channel
• Interruption 17 factors, 15 vectors, multi-interruption possible
• Standby mode Sleep/stop
• Package 100-pin plastic QFP
• Piggy/evaluation chip CXP82000 100-pin ceramic QFP
– 1 –
E97413A95-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP82032/82040/82052/82060
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
– 2 –
CXP82032/82040/82052/82060
8-BIT TIMER/COUNTER 0
8-BIT TIMER 1
UART BAUD RATE
GENERATOR
UART RECEIVER
UART TRANSMITTER
INT2
XTAL
PWM
RAM
3984
BYTES
SPC 700
CPU CORE
A/D CONVERTER
INT3/NMI
INT1
INT0
AN0 to AN7
8
PA0 to PA7
FDP
CONTROLLER/
DRIVER
32kHz
TIMER/COUNTER
PRESCALER/
TIME-BASE TIMER
RST
V
DD
V
SS
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F
PORT G
8
8
6
2
8
8
8
8
PB0 to PB7
PC0 to PC7
PD0 to PD7
PE0 to PE5
PF0 to PF7
PG0 to PG7
PE6 to PE7
TEX
EXTAL
TX
CS0
2
ROM
32K/40K/ 52K/60K
BYTES
RAM
KEY SCAN
PORT H
PH0 to PH7
8
CLOCK GENERATOR/
SYSTEM CONTROL
14-BIT PWM GENERATOR
FIFOREMOCON
RMC
SI0
SO0
SCK0
SI1
SO1
SCK1
EC0
TO
CINT
EC1
ADJ
G0/A0 to G15/A15
A16 to A23
A24 to A56
V
FDP
KR0 to KR7
16
8
32
8
2
SERIAL INTERFACE (CH1)
16-BIT CAPTURE
TIMER/COUNTER 2
SERIAL
INTERFACE
(CH0)
BUFFER
RAM
2
2
PORT I
PI0 to PI4
4
TxD
RxD
INTERRUPT CONTROLLER
RAM
Block Diagram
– 3 –
CXP82032/82040/82052/82060
Pin Assignment (Top View)
G1/A1
G0/A0
NC
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5/CINT
PE6/PWM
PE7/TO/ADJ
PC0/KR0
PC1/KR1
PC2/KR2
PC3/KR3
PC4/KR4
PC5/KR5
PC6/KR6
PC7/KR7
PB0/TxD
PB1/CS0/RxD
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PI0
PA0/AN0
PA1/AN1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
81
82
83
84
75
76
77
78
88
87
86
85
79
80
89
90
100
99
98
97
96
95
94
91
92
93
1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
PI1
RST
EXTAL
XTAL
Vss
PI2/TX
PI3/TEX
V
DD
V
FDP
PD0/A55
PD1/A54
PD2/A53
PD3/A52
PD4/A51
A21
A22
A23
PH7/A24
PH6/A25
PH5/A26
PH4/A27
PH3/A28
PH2/A29
PH1/A30
PH0/A31
PG7/A32
PG6/A33
PG5/A34
PG4/A35
PG3/A36
PG2/A37
PG1/A38
PG0/A39
PF7/A40
PF6/A41
PF5/A42
PF4/A43
PF3/A44
PF2/A45
PF1/A46
PF0/A47
PD7/A48
PD6/A49
PD5/A50
G2/A2
G3/A3
G4/A4
G5/A5
G6/A6
G7/A7
G8/A8
G9/A9
G10/A10
G11/A11
G12/A12
V
DD
G13/A13
G14/A14
G15/A15
A16
A17
A18
A19
A20
Note) 1. NC (Pin 3) is left open.
2. VDD (Pins 44 and 89) must be connected to VDD.
– 4 –
CXP82032/82040/82052/82060
Pin Description
Symbol I/O
Functions
I/O/
Analog input
PA0/AN0
to
PA7/AN7
(Port A)
8-bit I/O port. I/O can be set in a
unit of single bits. Incorporation
of the pull-up resistor can be set
through the program in a unit of
4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
I/O/Input
PC0/KR0
to
PC7/KR7
PE0/INT0/
EC0
PE1/INT1/
EC1
PE2/INT2
PE3/INT3/
NMI
PE4/RMC
PE5/CINT
PE6/PWM
PE7/TO/
ADJ
Input/Input/
Input
Input/Input/
Input
Input/Input
Input/Input/
Input
Input/Input
Input/Input
Output/Output
Output/Output/
Output
(Port C)
8-bit I/O port. I/O can be set in a
unit of single bits. Can drive
12mA sink current.
Incorporation of the pull-up
resistor can be set through the
program in a unit of 4 bits.
(8 pins)
Serves as key return inputs when
operating key scan with fluorescent
display panel (FDP) segment signal.
(8 pins)
I/O/Output
PD0/A55
to
PD7/A48
(Port D)
8-bit I/O port. I/O can be set in a
unit of single bits.
(8 pins)
FDP segment signal (anode
connection) outputs.
(Port E)
8-bit port. Lower 6 bits are for
inputs; upper 2 bits are for
outputs.
(8 pins)
External event inputs
for timer/counter.
(2 pins)
Inputs for
external
interruption
request.
(4 pins)
Non-maskable
interruption request input.
Remote control reception circuit input.
External capture input to 16-bit
timer/counter.
14-bit PWM output.
Output for the 16-bit timer/counter
rectangular waves, and 32kHz
oscillation frequency division.
I/O/Output
I/O/Input/
Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/Input
I/O/Output
PB0/TxD
PB1/CS0/
RxD
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
(Port B)
8-bit I/O port. I/O can be set in a
unit of single bits. Incorporation
of the pull-up resistor can be set
through the program in a unit of
4 bits.
(8 pins)
UART transmission data output.
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
Chip select input
for serial interface
(CH0).
UART reception
data input pin.
– 5 –
CXP82032/82040/82052/82060
(Port F)
8-bit I/O port. I/O can be set in a
unit of single bits.
(8 pins)
FDP segment signal (anode
connection) outputs.
(8 pins)
Symbol
I/O
Functions
OutputA16 to A23
FDP segment signal (anode connection) outputs.
(8 pins)
Output/Output
G0/A0
to
G15/A15
Outputs for FDP timing signals (grid connection)/segment signals (anode
connection).
(16 pins)
Output/Output
Input
Input
Input
Input/Input
PH0/A31
to
PH7/A24
PI0
PI1
PI2/TX
PI3/TEX
Output/Output
PG0/A39
to
PG7/A32
(Port H)
8-bit output port.
(8 pins)
(Port I)
4-bit input port.
(4 pins)
VFDP
EXTAL
XTAL
RST
NC
VDD
VSS
Input
Input
FDP voltage supply when incorporated pull-down (PD) resistor is set by
mask option.
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
Low-level active, system reset.
NC. Under normal operation, leave this pin open.
VCC supply.
GND.
FDP segment signal (anode
connection) outputs.
(8 pins)
Crystal connectors for 32kHz timer/counter clock
oscillation. For usage as event counter, input to TEX,
and leave TX open.
(Port G)
8-bit output port.
(8 pins)
FDP segment signal (anode
connection) outputs.
(8 pins)
PF0/A47
to
PF7/A40
I/O/Output
– 6 –
CXP82032/82040/82052/82060
Port B
8 pins
Hi-Z
Hi-Z
After a reset
PA0/AN0
to
PA7/AN7
PB0/TxD
PB1/CS0/RxD
PB3/SI0
PB6/SI1
Port B
4 pins
2 pins
Hi-Z
PB2/SCK0
PB5/SCK1
IP
Pull-up resistor
Port A data
Port A direction
"0" after a reset
Port A input selection
"0" after a reset
RD (Port A)
Internal data bus
A/D converter
∗
Pull-up transistor approx. 100kΩ
∗
Input multiplexer
"0" after a reset
Input protection circuit
I/O Circuit Format for Pins
Port A
Pin
Circuit format
Pull-up resistor
"0" after a reset
Port B data
∗
Internal data bus
Serial clock output enable
Internal
data bus
Port B direction
"0" after a reset
RD (Port B)
Pull-up resistor
"0" after a reset
SCK OUT
Port B output selection
"0" after a reset
Port B data
Port B direction
"0" after a reset
RD (Port B)
SCK IN
CS0
SI0
SI1
RxD
IP
Schmitt input
∗
Pull-up transistor approx. 100kΩ
∗
Pull-up transistor approx. 100kΩ
(PB0/TxD excluded)
IP
Schmitt input
∗
– 7 –
CXP82032/82040/82052/82060
2 pins
Hi-Z
Hi-Z
Pin
After a reset
Circuit format
PB4/SO0
PB7/SO1
PC0/KR0
to
PC7/KR7
8 pins
6 pins
Hi-Z
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5/CINT
IP
Schmitt input
Internal data bus
EC0/INT0
EC1/INT1
INT2
INT3/NM1
RMC
CINT
RD (PortE)
IP
Pull-up resistor
Port C data
Port C direction
"0" after a reset
RD (Port C)
Internal data bus
∗
1
Large current 12mA
∗
2
Pull-up transistor approx. 100kΩ
∗
2
"0" after a reset
∗
1
Key input signak
∗
Pull-up transistor approx. 100kΩ
Pull-up resistor
Port B data
Port B direction
"0" after a reset
RD (Port B)
Internal
data bus
IP
∗
"0" after a reset
Serial data output enable
Port B output selection
"0" after a reset
SO
Port E
Port C
Port B
1 pin
PE6/PWM
Port E output selection
Port E data
RD (Port E)
Internal data bus
"1" after a reset
"0" after a reset
PWM
Output enable
Port E
High level
– 8 –
CXP82032/82040/82052/82060
Pin
After a reset
Circuit format
1 pin
PE7/TO/ADJ
∗
1
ADJ signal is a frequency dividing
output for 32kHz oscillation frequency adjustment.
ADJ2K can be used for buzzer output.
∗
2
Pull-up transistor approx. 150kΩ
Port E data
"00" after a reset
∗
2
TO output enable
TO
ADJ16K
∗
1
ADJ2K
∗
2
00
01
10
11
MPX
Internal reset signal
Port E output selection (upper)
Port E output selection (lower)
"1" after a reset
Port E
16 pins
Hi-Z or
Low level
(when PD
resistor is
connected)
PD0/A55
to
PD7/A48
PF0/A47
to
PF7/A40
Port D
Port F
High level
(High level at
ON resistance
of pull-up
transistor
during a reset)
∗
High voltage drive transistor
RD (Ports D and F)
Internal
data bus
∗
"1" after a reset
Pull-down resistor
Port D and F data
Port D and F direction
Segment output data
Output selection control signal
("0" after a reset)
IP
∗
OP
VFDP
16 pins
Hi-Z or
Low level
(when PD
resistor is
connected)
PG0/A39
to
PG7/A32
PH0/A31
to
PH7/A24
Port G
Port H
RD (Ports G and H)
Internal data bus
Output selection control signal
("0" after a reset)
Port G and H data
"0" after a reset
Segment output data
∗
∗
High voltage drive transistor
Pull-down resistor
Mask option
V
FDP
OP
Output selection control signal
("0" after a reset)
Segment output data
∗
∗
High voltage drive transistor
Pull-down resistor
Mask option
V
FDP
OP
8 pins
Hi-Z or
Low level
(when PD
resistor is
connected)
A16 to A23
– 9 –
CXP82032/82040/82052/82060
Pin
After a reset
Circuit format
16 pins
G0/A0
to
G15/A15
2 pins
2 pins
EXTAL
XTAL
2 pins
Oscillation
Oscillation
stop
Port input
Low level
Hi-Z
PI2/TX
PI3/TEX
1 pin
RST
PI0
PI1
Hi-Z or
Low level
(when PD
resistor is
connected)
Output selection control signal
("0" after a reset)
Segment output data
Timing output data
∗
∗
High voltage drive transistor
Pull-down resistor
Mask option
V
FDP
OP
EXTAL
XTAL
IP
IP
IP
PI3/TEX
PI2/TX
IP
TEX oscillation circuit control
"1" after a reset
Internal data bus
RD
Internal data bus
RD
Clock input
IP
Schmitt input
Mask option
Pull-up resistor
OP
• Diagram shows circuit
composition during
oscillation.
• Feedback resistor is
removed and XTAL
becomes High level
during stop.
IP
RD (Port I)
Internal data bus
– 10 –
CXP82032/82040/82052/82060
∗1
VIN, VOUT and VOD must not exceed VDD + 0.3V.
∗2
VFDP and VOD must not exceed VDD – 40V.
∗3
Specifies output current of general-purpose I/O ports.
∗4
The large current drive transistor is the N-CH transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be
conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.
Supply voltage
FDP display supply voltage
Input voltage
Output voltage
Display output voltage
High level output current
High level total output
current
Low level output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
VDD
VFDP
VIN
VOUT
VOD
IOH
IODH1
IODH2
∑IOH
∑IODH
IOL
IOLC
∑IOL
Topr
Tstg
PD
–0.3 to +7.0
–40∗2to +7.0
∗1
–0.3 to +7.0
∗1
–0.3 to +7.0
∗1
–40∗2to +7.0
∗1
–5
–15
–50
–30
–120
15
20
100
–20 to +75
–55 to +150
600
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
°C
°C
mW
All pins excluding display outputs
∗3
(value per pin)
Display outputs A20 to A55 (value per pin)
Display outputs G0/A0 to G15/A15, and
A16 to A19 (value per pin)
Total for all pins excluding display outputs
Total for all display outputs
Pins excluding large current output (value per pin)
Large current output pins
∗4
(value per pin)
Total for all output pins
Item Symbol Rating Unit Remarks
Absolute Maximum Ratings (Vss = 0V reference)
– 11 –
CXP82032/82040/82052/82060
High level input
voltage
Low level input
voltage
Operating temperature
Supply voltage
5.5
5.5
5.5
5.5
VDD
VDD
VDD
VDD + 0.3
0.3VDD
0.2VDD
0.7
0.4
+75
V
V
V
V
V
V
V
V
V
V
V
V
°C
Item Symbol Min. Max. Unit Remarks
4.5
3.5
2.7
2.5
0.7VDD
0.8VDD
0.7VDD
VDD – 0.4
0
0
0
–0.3
–20
VIH
VIHS
VIHH
VIHEX
VIL
VILS
VILH
VILEX
Topr
Guaranteed operation range during
1/2 and 1/4 frequency dividing operation
mode
During 1/16 frequency dividing
operation mode or sleep mode
Guaranteed operation range with TEX
clock
Guaranteed data hold range during stop
∗1
∗2
∗3
EXTAL
∗4
∗1
∗2
∗3
EXTAL
∗4
VDD
∗1
Value for each pin of normal input port (PA,PB0, PB4, PB7, PC).
∗2
Value of the following pins: RST, CINT, CS0/TxD, RxD, SI0, SI1, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2,
INT3/NMI, RMC.
∗3
Value of the following pins: PD, PF.
∗4
Specifies only during external clock input.
Recommended Operating Conditions (Vss = 0V reference)
– 12 –
CXP82032/82040/82052/82060
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
VDD = 4.5V
VOH = VDD –2.5V
VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V
VDD = 5V
VOD – VFDP = 30V
VDD = 5.5V
VI = 0, 5.5V
High level
output voltage
Display output
current
4.0
3.5
0.5
–0.5
0.1
–0.1
–1.5
–3.3
–8
–30
30
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
mA
mA
µA
kΩ
µA
PC
PA to PD,
PE6, PE7,
PF to PH
EXTAL
TEX
RST
∗1
Item Symbol Pins Conditions Min.
PA to PC
∗2
A20 to A55
G0/A0 to
G15/A15
A16 to A19
G0/A0 to
G15/A15
A16 to A55
G0/A0 to
G15/A15
A16 to A55
PA to PC∗2,
PD∗4,PE0 to
PE5,PF∗4,PI,
RST
∗1
IOH
Open drain
output leakage
current (P-CH
Tr off state)
ILOL
Pull-down
resistor
∗3
I/O leakage
current
RL
IIZ
VOH
VOL
IIHE
IILE
IIHT
IILT
IILR
IIL
Low level
output voltage
Input current
70
Typ.
0.4
0.6
1.5
40
–40
10
–10
–400
–50
–20
220
±10
Max. Unit
DC Characteristics
Electrical Characteristics
(Ta = –20 to +75°C, VSS = 0V reference)
PA to PC,
PE6, PE7
– 13 –
CXP82032/82040/82052/82060
∗1
RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
∗2
PA to PC pins specify the input current when pull-up resistor has been selected; leakage current when no
resistor has been selected.
∗3
When incorporated pull-down resistor has been selected through mask option.
∗4
PD and PF pins are used as inputs by program. They specify pull-down resistor when no resistor has been
selected by mask option.
∗5
When all pins are open.
Item Symbol Pins Conditions Min. Typ. Max. Unit
Power supply
current
∗5
Input capacity
VDD
PA to PC,
PD∗4,
PE0 to PE5,
PF∗4,PI,
EXTAL,
TEX, RST
IDD1
1/2 frequency dividing
operation mode
IDDS1
IDDS2
IDDS3
IDD2
VDD = 5.5V, 16MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
Sleep mode
Stop mode
VDD = 5.5V, termination of 16MHz
and 32kHz crystal oscillation
VDD = 5.5V, 16MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
23 50 mA
30 100 µA
1.2 8 mA
12 30 µA
10 µA
CIN
Clock 1MHz
0V for all pins excluding
measured pins
10
20
pF
– 14 –
CXP82032/82040/82052/82060
EXTAL
t
XH tXLtCF tCR
0.4V
V
DD – 0.4V
1/fc
Crystal oscillation
Ceramic oscillation
EXTAL
XTAL
External clock
EXTAL
XTAL
74HC04
C1 C2
32kHz clock applied condition
Crystal oscillation
TEX
TX
C
1 C2
TEX
EC0
EC1
t
EH tELtEF tER
0.2VDD
0.8VDD
tTH tTLtTF tTR
∗1
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
AC Characteristics
(1) Clock timing
System clock frequency
System clock input pulse width
System clock input rise time,
fall time
Event count input clock
pulse width
Event count input clock
rise time, fall time
System clock frequency
Event count input
pulse width
Event count input rise time,
fall time
fC
tXL
tXH
tCR
tCF
tEH
tEL
tER
tEF
fC
tTL
tTH
tTR
tTF
XTAL
EXTAL
EXTAL
EXTAL
EC0,
EC1
EC0,
EC1
TEX
TX
TEX
TEX
MHz
ns
ns
ns
ms
kHz
µs
ms
Item Symbol Pin Conditions Min. Unit
Fig. 1, Fig. 2
Fig. 1, Fig. 2
External clock drive
Fig. 1, Fig. 2
External clock drive
Fig. 3
Fig. 3
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
Fig. 3
Fig. 3
1
28
tsys + 50
∗
1
10
Typ.
32.768
Max.
16
200
20
20
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Fig. 2. Clock applied conditions
Fig. 1. Clock timing
Fig. 3. Event count clock timing
– 15 –
CXP82032/82040/82052/82060
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
CS0 ↓ → SCK0
delay time
CS0 ↑ → SCK0
float delay time
CS0 ↓ → SO0
delay time
CS0 ↑ → SO0
float delay time
CS0 High level width
SCK0 cycle time
SCK0
High, Low level width
SI0 input set-up time
(for SCK0 ↑)
SI0 input hold time
(for SCK0 ↑)
SCK0 ↓ → SO0
delay time
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK0
SCK0
SO0
SO0
CS0
SCK0
SCK0
SI0
SI0
SO0
Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
ns
ns
ns
ns
ns
Symbol Pin Min.
tsys + 200
tsys + 200
tsys + 200
tsys + 200
tsys + 200
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
200
tsys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsys + 200
100
Max. UnitConditions
– 16 –
CXP82032/82040/82052/82060
CS0
SCK0
0.2V
DD
0.8VDD
tWHCS
tDCSK
tDCSKF
0.8VDD
0.2VDD
0.8VDD
tKCY
tKL tKH
0.8VDD
0.2VDD
SI0
t
SIK tKSI
Input data
t
DCSO tKSO tDCSOF
Output data
0.8V
DD
0.2VDD
SO0
Fig. 4. Serial transfer CH0 timing
– 17 –
CXP82032/82040/82052/82060
SCK1
0.2VDD
0.8VDD
tKL tKH
SO1
tKCY
tSIK
tKSI
0.2VDD
0.8VDD
tKSO
0.2VDD
0.8VDD
Output data
Input data
SI1
Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
SCK1 cycle time
tKCY
SCK1
Input mode
Ouput mode
Input mode
Ouput mode
SCK1 input mode
SCK1 ouput mode
SCK1 input mode
SCK1 ouput mode
SCK1 input mode
SCK1 ouput mode
1000
16000/fc
400
8000/fc – 50
100
200
200
100
200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1
SI1
SI1
SO1
tKH
tKL
tSIK
tKSI
tKSO
SCK1
High, Low level width
SI1 input set-up time
(for SCK1 ↑)
SI1 input hold time
(for SCK1 ↑)
SCK1 ↓ → SO1 delay time
Symbol Pin Condition Min. Max. Unit
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
– 18 –
CXP82032/82040/82052/82060
Analog input
Linearity error
V
FTVZT
00h
01h
FEh
FFh
Digital conversion value
Conversion time
Sampling time
Analog input voltage
tCONV
tSAMP
VIAN
VZT
∗1
VFT
∗2
AN0 to AN7
Ta = 25°C
VDD = 5.0V
VSS = 0V
Linearity error
Zero transition
voltage
Full-scale
transition voltage
Resolution
µs
µs
V
VDD
26/fADC
∗3
6/fADC
∗3
0
Item Symbol Pin Condition Min. Typ. Max. Unit
Bits
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
8
±3
LSB
70
mV
5030
10
4970
–10
4910 mV
Fig. 6. Definition of A/D converter terms
∗1
VZT: Value at which the digital conversion value changes from
00h to 01h and vice versa.
∗2
VFT: Value at which the digital conversion value changes from
FEh to FFh and vice versa.
∗3
fADC indicates the below values due to the contents of bit 6 (CKS)
of the A/D control register (ADC: 00F9h) and bits 7 (PCK1) and 6
(PCK0) of the clock control register (CLC: 00FEh).
fADC = fc (CKS = "0"), fc/2 (CKS = "1")
However, the selection for fADC = fc (CKS = "0") is
limited in the clock range of fc = 1 to 14MHz (VDD = 4.5
to 5.5V).
– 19 –
CXP82032/82040/82052/82060
0.2VDD
0.8VDD
tIH
tIL
INT0
INT1
INT2
NMI/INT3
(NMI specifies only for the
falling edge)
tIL tIH
tRSL
0.2VDD
RST
External interruption
High, Low level width
Reset input Low level width
INT0
INT1
INT2
NMI/INT3
RST
1
32/fc
µs
µs
Item Symbol Pin Condition Min. Max. Unit
tIH
tIL
tRSL
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Fig. 7. Interruption input timing
Fig. 8. RST input timing
– 20 –
CXP82032/82040/82052/82060
C1
EXTAL
XTAL
C
2
Rd
EXTAL
XTAL
(i) Main clock
EXTAL
XTAL
C1 C2
Rd
XTAL
(ii) Main clock
AAAA
EXTAL
XTAL
C
1 C2
Rd
AAAA
TEX
TX
(iii) Sub clock
Appendix
Models marked with an asterisk (∗) have the built-in ground capacitance (C1, C2).
Fig. 9. Recommended oscillation circuit
Manufacturer
MURATA
MFG
CO., LTD.
RIVER ELETEC
CO., LTD
KINSEKI
LTD.
Model
Circuit
example
(i)
CSA10.0MTZ
CSA12.0MTZ
CSA16.00MXZ040
CST10.0MTW
∗
CST12.0MTW
∗
CST16.00MXW0C1
∗
Seiko
Instruments Inc.
HC-49/U03
HC-49/U (-S)
VTC-200
SP-T
fc (MHz)
10.0
12.0
16.0
10.0
12.0
16.0
8.0
12.0
16.0
8.0
12.0
16.0
30
5
30
5
18
12
10
10
5
Open
18
30
5
30
5
18
12
10
10
5
Open
18
0
330
0
32.768kHz
330k
(iii)
C1 (pF) C2 (pF)
Rd (Ω)
(i)
(ii)
CL = 12.5pF
Remarks
– 21 –
CXP82032/82040/82052/82060
1/2 dividing mode
1/4 dividing mode
Sleep mode
10
1
0.1
0.01
100
0 1 2
3
4 5 6 7
1/16 dividing mode
IDD vs. VDD
(Ta = 25°C, Typical)
V
DD – Supply voltage [V]
I
DD
– Supply current [mA]
32kHz mode
32kHz
Sleep mode
0 5 10 15 20
0
5
10
15
20
25
1/2 dividing mode
1/4 dividing mode
1/16 dividing mode
Sleep mode
IDD vs. fc
(VDD = 5V, Ta = 25°C, Typical)
fc – System clock [MHz]
I
DD
– Supply current [mA]
Characteristics Curve
– 22 –
CXP82032/82040/82052/82060
Package Outline Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
PACKAGE STRUCTURE
23.9 ± 0.4
QFP-100P-L01
100PIN QFP (PLASTIC)
20.0 – 0.1
+ 0.4
0.15 – 0.05
+ 0.1
15.8 ± 0.4
17.9 ± 0.4
14.0 – 0.1
+ 0.4
2.75 – 0.15
+ 0.35
A
0.65
M
0.13
QFP100-P-1420
1.7g
1
100
81
80 51
50
31
30
0.3 – 0.1
+ 0.15
DETAIL A
0° to 10°
0.8 ± 0.2
(16.3)
0.15
0.1 – 0.05
+ 0.2
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