Datasheet CXP81848A, CXP81840A Datasheet (Sony)

CXP81840A/81848A

CMOS 8-bit Single Chip Microcomputer

Description

The CXP81840A/81848A is a CMOS 8-bit micro­computer which consists of A/D converter, serial
interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, 32kHz
timer/event counter, remote control receiving circuit,
as well as basic configurations like 8-bit CPU, ROM,
RAM and I/O port. They are integrated into a single
chip.

Also CXP81840A/81848A provides sleep/stop
function which enables to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.

100 pin QFP (PIastic) 100 pin LQFP (PIastic)

Structure

Silicon gate CMOS IC

Features

• A wide instruction set (213 instructions) which cover various types of data

— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction

• Minimum instruction cycle During operation 333ns/12MHz (Supply voltage 3.0 to 5.5V)

During operation 250ns/16MHz (Supply voltage 4.5 to 5.5V)
During operation 122µs/32kHz

• Incorporated ROM capacity 40K bytes (CXP81840A)

48K bytes (CXP81848A)

• Incorporated RAM capacity 1344bytes

• Peripheral functions

— A/D converter 8-bit, 12-channel, successive approximation system

(Conversion time 20.0µs/16MHz)

— Serial interface Incorporated 8-bit and 8-stage FIFO, 1-channel

(1 to 8 bytes auto transfer)
8-bit serial I/O, 1-channel

— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer

32kHz timer/counter

— High precision timing pattern generator PPG 19 pins 32-stage programmable

RTG 5-pins 2-channel
— PWM/DA gate output 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14-bit, 1-channel
— Remote control receiving circuit 8-bit pulse measuring counter, 6-stage FIFO

• Interruption 20 factors, 15 vectors, multi-interruption possible

• Standby mode SLEEP/STOP

• Package 100-pin plastic QFP/LQFP

• Piggyback/evaluation chip CXP81800 100-pin ceramic QFP/LQFP

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94Z12-ST

CXP81840A/81848A

Vss
V

DD

MP
RST

XTAL
EXTAL

TX
TEX

PE1/INT2
PI4/INT1/NMI

PE0/INT0

PA0 to PA7

PB0 to PB7

8

PORT A8PORT B8PORT C

CLOCK

GENERATOR/

SYSTEM CONTROL

SPC700

CPU CORE

NMI

2

PC0 to PC7

PD0 to PD7
8

PORT D

RAM

1344 BYTES

PROM

40K/48K BYTES

INTERRUPT CONTROLLER

PE0 to PE1

PE2 to PE7

2

6

PORT E

2

PF4 to PF7

PF0 to PF3

4

PG0 to PG7

PH0 to PH7

4

PORT F8PORT G8PORT H7PORT I

32kHz

PRESCALER/

TIME BASE TIMER

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

2

PI1 to PI7

REALTIME

2

PJ0 to PJ7

8

PORT J

CH1

519

PULSE

CH0

GENERATOR

RAM

PATTERN

GENERATOR

PROGRAMMABLE

4

2

PC7/RTO7

to

PC3/RTO3

PC2/PPO18

to

PA0/PPO0

AVss

AV

REF

AV

DD

AN0 to AN3

Block Diagram

A/D CONVERTER

12

PF0/AN4

PF7/AN11

to

FIFO

(CH0)

SERIAL

INTERFACE UNIT

SI0

CS0

SO0

SCK0

(CH1)

8 BIT TIMER 1

SERIAL INTERFACE UNIT

PI7/SI1

PI6/SO1

PI5/SCK1

8 BIT TIMER/COUNTER 0

PI3/TO

PE1/EC

– 2 –

PG7/EXI1

PG6/EXI0

FIFO

REMOCON INPUT

PI1/RMC

14 BIT PWM GENERATOR

PI2/PWM

12 BIT PWM GENERATOR CH1

12 BIT PWM GENERATOR CH0

PI3/ADJ

PE7/DAB1

PE5/DAA1

PE6/DAB0

PE4/DAA0

PE3/PWM1

PE2/PWM0

Pin Configuration 1 (Top View) 100 pin QFP package

PA6/PPO6

PA5/PPO5

PA4/PPO4

PA3/PPO3

PA2/PPO2

PA1/PPO1

PA0/PPO0

PB7/PPO15

PB6/PPO14

DD

V

NC

PA7/PPO7

CXP81840A/81848A

SS

TX

V

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/ADJ

PB5/PPO13
PB4/PPO12
PB3/PPO11
PB2/PPO10

PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4

PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0

10

12
13
14
15
16
17

19

25

29
30

11

18

20
21
22
23
24

26
27
28

100

99

98

1

2
3
4

5
6
7
8
9

32

31

33

97

34

96

35

95

36

94

37

93

38

92

39

91

40

90

41

89

42

88

43

87

44

45

86

85

46

84

47

83

48

82

49

81

50

80
79
78
77
76
75

71

69
68
67
66
65
64
63
62
61
60
59
58
57
56
55

53
52
51

74
73
72

70

54

PI6/SO1
PI7/SI1
PE0/INT0
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0
PG1
PG2
PG3
PG4
PG5
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AV

DD

AVREF
AVSS
PF4/AN8

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

MP

RST

SS

V

XTAL

CS0

EXTAL

SI0

SO0

SCK0

Note) 1. NC (Pin 90) is always connected to VDD.

2. Vss (Pins 41 and 88) are both connected to GND.

– 3 –

PF5/AN9

PF6/AN10

PF7/AN11

Pin Configuration 2 (Top View) 100 pin LQFP package

PA7/PPO7

PA6/PPO6

PA5/PPO5

PA4/PPO4

PA3/PPO3

PA2/PPO2

PA1/PPO1

PA0/PPO0

PB7/PPO15

PB6/PPO14

PB5/PPO13

PB4/PPO12

NC

CXP81840A/81848A

SS

DD

V

TX

V

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/ADJ

PI7/SI1

PI6/SO1

PE0/INT0

PB3/PPO11
PB2/PPO10

PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4

PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5
PD4
PD3

10
11
12
13
14
15
16
17
18
19

21
22

20

23
24
25

100

99

98
1
2

3

4
5

6

7
8
9

27

28

26

97

29

96

30

95

31

94

32

93

33

92

34

91

35

90

36

89

37

88

38

87

39

86

40

85

41

84

42

83

43

82

44

81

45

80

46

79

47

78

48

77

49

76

50

75
74
73
72

70
69

67

65
64
63
62
61

59
58

56
55
54
53
52
51

71

68

66

60

57

PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0
PG1
PG2
PG3
PG4
PG5
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7

DD

AV
AVREF

PD2

PD1

PD0

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

V

XTAL

CS0

EXTAL

SS

MP

Note) 1. NC (Pin 88) is always connected to VDD.

2. Vss (Pins 39 and 86) are both connected to GND.

– 4 –

SI0

SO0

SCK0

PF7/AN11

PF4/AN8

PF5/AN9

PF6/AN10

SS

AV

Pin Description

Symbol I/O Description

(Port A)

PA0/PPO0

to

PA7/PPO7

Output/
Real time
Output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port B)

PB0/PPO8

to

PB7/PPO15

Output/
Real time
Output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

CXP81840A/81848A

Programmable pattern generator (PPG)
output.
Functions as high precision real time
pulse output port.
(19 pins)

PC0/PPO16

to

PC2/PPO18
PC3/RTO3

to

PC7/RTO7

PD0 to PD7

PE0/INT0

PE1/EC/INT2

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0

I/O/
Real time
Output

I/O/
Real time
Output

I/O

Input/input

Input/input/input

Output/output
Output/output
Output/output
Output/output
Output/output

(Port C)
8-bit I/O port, enables to
specify I/O by bit unit.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)

Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)

(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current.
(8 pins)

Input pin to request external interruption.
Active when falling edge.

External event
input pin for

(Port E)

timer/counter.
8-bit port. Lower 2 bits are
input pins and upper 6 bits
are output pins.

PWM output pins.

(2 pins)
(8 pins)

DA gate pulse output pins.

(4 pins)

Input pin to request
external interruption.
Active when falling edge.

PE7/DAB1
AN0 to AN3
PF0/AN4

to

PF3/AN7
PF4/AN8

to

PF7/AN11
SCK0
SO0
SI0
CS0

Output/output
Input

Input/input

Output/input

I/O
Ouput
Input
Input

Analog input pins to A/D converter. (12 pins)

(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)

Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.
Serial data (CH0) input pin.
Serial chip select (CH0) input pin.

– 5 –

Symbol I/O Description

CXP81840A/81848A

PG0 to PG5
PG6/EXI0
PG7/EXI1

PH0 to PH7

PI1/RMC
PI2/PWM

PI3/TO/ADJ
PI4/INT1/

NMI
PI5/SCK1
PI6/SO1
PI7/SI1

PJ0 to PJ7

Input
Input/input
Input/input

Output

I/O/input
I/O/output

I/O/output/output

I/O/input/input
I/O/I/O

I/O/output
I/O/input

I/O

(Port G)
8-bit input port.
(8 pins)

External input pin to FRC capture unit.

(Port H)
N-ch open drain output of middle tension proof (12V) and high current
(12mA).
(8 pins)

Remote control receiving circuit input pin.
14-bit PWM output pin.

(Port I)
7-bit I/O port.
I/O port can be
specified by the
bit unit.
(7 pins)

Timer/counter, 32kHz oscillation adjustment output
pin.

Input pin to request external interruption and
non maskable interruption. Active when falling edge.

Serial clock (CH1) I/O pin.
Serial data (CH1) output pin.
Serial data (CH1) input pin.

(Port J)
8-bit I/O port. Function as standby release input can be specified by

the bit unit. I/O can be specified by the bit unit.
EXTAL
XTAL
TEX
TX
RST

MP
AVDD
AVREF
AVss
VDD
Vss

Input
Output
Input
Output

Input
Input

Input

Connecting pin of crystal oscillator for system clock. When supplying

the external clock, input the external clock to EXTAL pin and input

opposite phase clock to XTAL pin.

Connecting pin of crystal oscillator for 32kHz timer clock. When used

as event counter, input to TEX pin and leave TX pin open.

(Feedback resistor is not removed.)

System reset pin of active "Low" level.

Microprocessor mode input pin. Always connect to GND.

Positive power supply pin of A/D converter.

Reference voltage input pin of A/D converter.

GND pin of A/D converter.

Positive power supply pin.

GND pin. Connect both Vss pins to GND.

– 6 –

Input/Output Circuit Formats for Pins

CXP81840A/81848A

Pin

PA0/PPO0

to

PA7/PPO7
PB0/PPO8

to

PB7/PPO15

16 pins

PC0/PPO16

to

PC2/PPO18
PC3/RTO3

to

PC7/RTO7

Port A
Port B

Data bus

Port C

PPO data

Port A or Port B

RD

PPO, RTO data

Port C data

Port C direction

Circuit format

Output becomes active from high
impedance by data writing to port register.

(Every bit)

IP

Input
protection
circuit

When reset

Hi-Z

Hi-Z

8 pins

PD0

to

PD7

8 pins

Data bus

Port D

Data bus

RD (Port C)

Port D data

Port D direction

RD (Port D)

(Every 4 bits)

PD0 to 3
PD4 to 7

IP

High
current
12mA

Hi-Z

– 7 –

CXP81840A/81848A

Pin

PE0/INT0
PE1/EC/INT2

2 pins

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1

4 pins

Port E

Port E

Data bus

DA gate output
or PWM output

Hi-Z control

Port E data

Port/DA output
select

RD (Port E)

Schmitt input

IP

Circuit format

RD (Port E)

MPX

When reset

Hi-Z

Data bus

Hi-Z

PE6/DAB0
PE7/DAB1

2 pins

AN0

to

AN3

4 pins

PF0/AN4

to

PF3/AN7

Port E

Data bus

Port F

DA gate output

Hi-Z control

Port E data

Port/DA output
select

AA

RD (Port E)

Input multiplexer

IP

Input multiplexer

IP

MPX

A/D converter

A/D converter

H level

Hi-Z

Hi-Z

4 pins

Data bus

RD (Port F)

– 8 –

CXP81840A/81848A

A

A

Pin

PF4/AN8

to

PF7/AN11

4 pins

PG0

to

PG5

6 pins

PG6/EXI0
PG7/EXI1

Port F

Data bus

Port G

Port G

Port F data

RD (Port F)

Note) For PG4 and PG5, CMOS schmitt input or TTL schmitt input can be
selected with the mask option.

Circuit format

Port F selection

Schmitt input

IP

IP

RD (Port G)

IP

A/D converter

Input multiplexer

Data bus

FRC capture unit

Data bus

When reset

Hi-Z

Hi-Z

Hi-Z

2 pins

PH0

to

PH7

8 pins

PI2/PWM
PI3/TO/ADJ

Port H

Port I

Data bus

Port H data

Data bus

PI2: From 14-bit PWM

From timer/counter,

PI3:

32kHz timer

Port I data

Port I I/O direction

RD (Port H)

Port I selection

RD (Port G)

MPX

A
A

Middle tension proof 12V

Hi-Z

High current
12mA

Hi-Z

IP

2 pins

RD (Port I)

– 9 –

CXP81840A/81848A

A

A

PIn

PI1/RMC
PI4/INT1/NMI
PI7/SI1

3 pins

PI5/SCK1
PI6/SO1

2 pins

Port I

Data bus

PI1: To remote control circuit
PI4: To interruption circuit
PI7: To serial CH1

Port I

Port I function
select

From serial CH1

Port I data

Port I direction

Data bus

RD (Port I)

Circuit format

Port I data

Port I direction

RD (Port I)

MPX

A

MPX

A

Note)
PI5 is schmitt input
PI6 is inverter input

To serial CH1

Schmitt input

When reset

IP

Hi-Z

Hi-Z

IP

PJ0

to

PJ7

8 pins

CS0

SI0

2 pins

SO0

1 pin

Port J

Port J data

Port J direction

Data bus

RD
(Port J)

Standby release

SO0 from SIO

SO0 output enable

Edge detection

Schmitt input

IP

To SIO

Hi-Z

IP

Hi-Z

Hi-Z

– 10 –

CXP81840A/81848A

PIn

SCK0

1 pin

EXTAL
XTAL

2 pins

TEX
TX

2 pins

EXTAL

XTAL

TEX

TX

Internal serial clock
from SIO

SCK0 output enable

External serial clock to SIO

IP

IP

Circuit format

Schmitt input

32kHz
timer counter

IP

• Shows the circuit
composition during
oscillation.

• Feedback resistor is
removed during stop.
XTAL becomes "H"
level.

• Shows the circuit
composition during
oscillation.

• Feedback resistor is
removed during 32kHz
oscillation circuit stop
by software.
At this time TEX pin
outputs "L" level and TX
pin outputs "H" level.

When reset

Hi-Z

Oscillation

Oscillation

RST

1 pin

MP

1 pin

Mask option

Pull-up resistor

Schmitt input

OP

IP

IP

CPU mode

L level

Hi-Z

– 11 –

CXP81840A/81848A

Absolute Maximum Ratings (Vss = 0V)

Item Symbol Rating Unit Remarks

–0.3 to +7.0

AVss to +7.0

–0.3 to +0.3
–0.3 to +7.0
–0.3 to +7.0

–0.3 to +15.0

–5

–50

15

∗1

∗2
∗2

Supply voltage

Input voltage
Output voltage
Medium withstand output voltage
High level output current
High level total output current

VDD
AVDD
AVSS
VIN
VOUT
VOUTP
IOH
∑IOH

IOL

Low level output current

20

130

–20 to +75

–55 to +150

Low level total output current
Operating temperature
Storage temperature

IOLC
∑IOL
Topr
Tstg

600

Allowable power dissipation

∗1

AVDD and VDD should be set to a same voltage.

∗2

VIN and VOUT should not exceed VDD + 0.3V.

∗3

The high current operation transistors are the N-CH transistors of the PD and PH ports.

PD

380

V
V
V
V
V

V
mA
mA

mA
mA

mA

°C
°C

mW

PH pin

Total of output pins
Other than high current output

pins: per pin
High current port pin∗3: per pin
Total of output pins

QFP package type
LQFP package type

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.

– 12 –

CXP81840A/81848A

Recommended Operating Conditions (Vss = 0V)

Item Symbol Min. Max. Unit Remarks

Guaranteed range
during high speed
mode (1/2 dividing
clock) operation

∗3

∗4, ∗7

TEX pin
TEX pin

∗6, ∗7
∗6, ∗8

∗3

∗4, ∗7

TEX pin
TEX pin

∗6, ∗7
∗6, ∗8

Supply voltage

Analog power supply

HIgh level
input voltage

Low level
input voltage

VDD

AVDD
VIH
VIHS
VIHTS

VIHEX

VIL

VILS
VILTS

VILEX

4.5

3.0

2.7

2.7

2.5

3.0

0.7VDD

0.8VDD

2.2
VDD – 0.4
VDD – 0.2

0
0
0

0
–0.3
–0.3

5.5

5.5

5.5

5.5

5.5

5.5
VDD
VDD
VDD

VDD + 0.3
VDD + 0.2

0.3VDD

0.2VDD

0.2VDD

0.8

0.4

0.2

fc = less than 16MHz

V

fc = less than 12MHz
Guaranteed range during low speed mode

V

(1/16 dividing clock) operation
Guaranteed operation range by TEX clock

V

Guaranteed data hold operation range

V

during STOP

∗1

V

∗2

V

CMOS schmitt input

V

TTL schmitt input

V

EXTAL pin

V

EXTAL pin

V

∗2, ∗7

V

∗2, ∗8

V

CMOS schmitt input

V

TTL schmitt input

V

EXTAL pin

V

EXTAL pin

V

∗5, ∗7
∗5, ∗8

∗5, ∗7
∗5, ∗8

Operating temperature

∗1

AVDD and VDD should be set to a same voltage.

∗2

Normal input port (each pin of PC, PD, PE0, PE1, PF0 to PF3, PG, PI and PJ), MP pin.

∗3

Each pin of CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PG (For PG4 and PG5, when CMOS schmitt

Topr

–20

+75

°C

input is selected with mask option), PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1.

∗4

Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)

∗5

It specifies only when the external clock is input.

∗6

It specifies only when the event count clock is input.

∗7

This case applies to the range of 4.5 to 5.5V supply voltage (VDD).

∗8

This case applies to the range of 3.0 to 3.6V supply voltage (VDD).

– 13 –

Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)

CXP81840A/81848A

(Ta = –20 to +75°C, Vss = 0V)

Item Symbol Pins Conditions Min.

High level
output voltage

Low level
output voltage

VOH

VOL

IIHE

PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0

PD, PH

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V

EXTAL

Input current

IILE
IIHT

VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V

TEX

IILT
IILR

RST

∗1

VDD = 5.5V,
VIL = 0.4V

PA to PG,

I/O leakage
current

IIZ

PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST

VDD = 5.5V,
VI = 0, 5.5V

∗1

Open drain
output leakage
current (N-CH

ILOH

PH

VDD = 5.5V
VOH = 12V

Tr OFF in state)

4.0

3.5

0.5

–0.5

0.1
–0.1
–1.5

Typ.

Max. Unit

V
V

0.4

0.6

1.5
40

–40

10

–10

–400

±10

50

V
V

V
µA
µA
µA
µA
µA

µA

µA

IDD1

VDD = 5V ± 0.5V

∗3

24

45

SLEEP mode

16MHz crystal oscillation (C1 = C2 = 15pF)

IDDS1

1.3

8

VDD = 5V ± 0.5V

32kHz crystal oscillation (C1 = C2 = 47pF)

Supply
current

∗2

IDD2

VDD

VDD = 3V ± 0.3V

35

100

SLEEP mode

IDDS2

6

30

VDD = 3V ± 0.3V

STOP mode

IDDS3

(EXTAL and TEX pins oscillation stop)

10

VDD = 5V ± 0.5V

Other than VDD,
Vss, AV

Input capacity

∗1

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

CIN

DD

AVss

Clock 1MHz

, and

0V other than the measured pins

10

20

when non-resistor is selected.

∗2

When entire output pins are open.

∗3

When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).

mA

mA

µA

µA

µA

pF

– 14 –

CXP81840A/81848A

DC Characteristics (VDD = 3.0 to 3.6V) (Ta = –20 to +75°C, Vss = 0V)

Item Symbol Pins Conditions Min.

High level
output voltage

Low level
output voltage

VOH

VOL

IIHE

PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0

PD, PH

VDD = 3.0V, IOH = –0.15mA
VDD = 3.0V, IOH = –0.5mA
VDD = 3.0V, IOL = 1.2mA
VDD = 3.0V, IOL = 1.6mA
VDD = 3.0V, IOL = 5mA
VDD = 3.6V, VIH = 3.6V

EXTAL

Input current

IILE
IIHT

VDD = 3.6V, VIL = 0.3V
VDD = 3.6V, VIH = 3.6V

TEX

IILT
IILR

RST

∗1

VDD = 3.6V,
VIL = 0.3V

PA to PG,

I/O leakage
current

Open drain
output leakage
current

IIZ

ILOH

PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST

PH

VDD = 3.6V,
VI = 0, 3.6V

∗1

VDD = 3.6V,
VOH = 12V

2.7

2.3

0.3

–0.3

0.1
–0.1
–0.9

Typ.

Max. Unit

V
V

0.3

0.5

1.0
20

–20

10

–10

–200

±10

50

V
V

V
µA
µA
µA
µA
µA

µA

µA

IDD1

VDD = 3.3V ± 0.3V

∗3

11

25

SLEEP mode

12MHz crystal oscillation (C1 = C2 = 15pF)

Supply
current

∗2

IDDS1

VDD

VDD = 3.3V ± 0.3V

0.5

2.5

STOP mode

IDDS3

(EXTAL and TEX pins oscillation stop)

10

VDD = 3.3V ± 0.3V

Other than VDD,

Input capacity

∗1

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

CIN

Vss, AV
AVss

DD

Clock 1MHz

, and

0V other than the measured pins

10

20

when non-resistor is selected.

∗2

When entire output pins are open.

∗3

When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).

mA

mA

µA

pF

– 15 –

A

A

A

AC Characteristics
(1) Clock timing

CXP81840A/81848A

(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)

Item Symbol Pins Conditions Unit

System clock frequency

System clock input pulse width

System clock input
rise and fall times

Event count clock input
pulse width

Event count clock input
rise and fall times

System clock frequency
Event count clock input

pulse width
Event count clock input

rise and fall times

∗

tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2

bits (CPU clock selection).

fC

tXL,
tXH

tCR,
tCF

tEH,
tEL

tER,
tEF

fC

tTL,
tTH

tTR,
tTF

XTAL
EXTAL

EXTAL

EXTAL

EC

EC
TEX

TX
TEX

TEX

Fig. 1,
Fig. 2

Fig. 1,
Fig. 2 (External clock drive)

Fig. 1, Fig. 2
(External clock drive)

Fig. 3

Fig. 3
Fig. 2 VDD = 2.7 to 5.5V

(32kHz clock applied condition)
Fig. 3

Fig. 3

VDD = 4.5 to 5.5V

VDD = 4.5 to 5.5V

Min.

1
1

28

37.5

tsys × 4

32.768

10

Max.

16
12

200

∗

20

20

tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11")

MHz

ns

ns

ns

ns

kHz

µs

ms

Fig. 1. Clock timing

EXTAL

Fig. 2. Clock applied condition

Crystal oscillation
Ceramic oscillation

EXTAL

AA

C

1 C2

XTAL

1/fc

XH tXLtCF tCR

t

32kHz clock applying condition

External clock

EXTAL

AA

74HC04

XTAL

crystal oscillation

TEX

AA

1

C

TX

DD – 0.4V

V

0.4V

C2

– 16 –

Fig. 3. Event count clock timing

CXP81840A/81848A

TEX
EC

t

EH tELtEF tER

tTH tTLtTF tTR

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

CS0 ↓→SCK0
delay time

CS0 ↑→SCK0
floating delay time

CS0 ↓→SO0
delay time

CS0 ↑→SO0
floating delay time

Symbol Pin Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

SCK0

SCK0

SO0

SO0

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode

Chip select transfer mode

0.8VDD

0.2VDD

Max. UnitCondition

tsys + 200

tsys + 200

tsys + 200

tsys + 200

ns

ns

ns

ns

CS0
high level width

SCK0
cycle time

SCK0
high and low level widths

SI0 input setup time
(against SCK0 ↑)

SI0 input hold time
(against SCK0 ↑)

SCK0 ↓→SO0 delay time

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

CS0

SCK0

SCK0

SI0

SI0

SO0

Chip select transfer mode
Input mode

Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode

tsys + 200

2tsys + 200

16000/fc

tsys + 100

8000/fc – 50

100
200

tsys + 200

100

tsys + 200

100

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns

tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11")

Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.

– 17 –

CXP81840A/81848A

Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)

Item

CS0 ↓→SCK0
delay time

CS0 ↑→SCK0
floating delay time

CS0 ↓→SO0
delay time

CS0 ↑→SO0
floating delay time

CS0
high level width

SCK0
cycle time

SCK0
high and low level widths

SI0 input setup time
(against SCK0 ↑)

SI0 input hold time
(against SCK0 ↑)

SCK0 ↓→SO0 delay time

Symbol Pin Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0

SCK0

SO0

SO0

CS0

SCK0

SCK0

SI0

SI0

SO0

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode

Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode

tsys + 200

2tsys + 200

16000/fc

tsys + 100

8000/fc – 100

100
200

tsys + 200

100

Max. UnitCondition

tsys + 250

tsys + 200

tsys + 250

tsys + 200

tsys + 250

100

ns

ns

ns

ns

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11")

Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF.

– 18 –

Fig. 4. Serial transfer CH0 timing

CXP81840A/81848A

tWHCS

CS0

SCK0

0.2V

DD

tKCY

tDCSK tDCSKF

tKL tKH

0.8VDD

0.2VDD

tKSI

SIK

t

0.8VDD

0.8VDD

SI0

SO0

0.8VDD

Input

data

0.2VDD

t

DCSO tKSO tDCSOF

Output

data

0.8V

DD

0.2VDD

– 19 –

CXP81840A/81848A

Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pins Min. Max. UnitConditions

SCK1 cycle time

SCK1 high and low
level widths

SI1 input setup time
(against SCK1 ↑)

SI1 input hold time
(against SCK1 ↑)

SCK1 ↓→SO1 delay time

Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)

Item Symbol Pins Min. Max. UnitConditions

SCK1 cycle time

tKCY

tKH
tKL

tSIK

tKSI

tKSO

tKCY

SCK1

SCK1

SI1

SI1

SO1

SCK1

Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode

Input mode
Output mode

1000

16000/fc

400

8000/fc – 50

100
200
200
100

1000

16000/fc

200
100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns
ns

SCK1 high and low
level widths

SI1 input setup time
(against SCK1 ↑)

SI1 input hold time
(against SCK1 ↑)

SCK1 ↓→SO1 delay time

Note) The load of SCK1 output mode and SO1 output delay time is 50pF.

tKH
tKL

tSIK

tKSI

tKSO

SCK1

SI1

SI1

SO1

Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode

400

8000/fc – 100

100
200
200
100

250
100

ns
ns
ns
ns
ns
ns
ns
ns

– 20 –

Fig. 5. Serial transfer CH1 timing

KCY

t

tKL tKH

CXP81840A/81848A

SCK1

SI1

SO1

tKSO

tSIK tKSI

Input data

0.8VDD

0.2VDD

0.8VDD

0.2V

Output data

0.8VDD

0.2VDD

DD

– 21 –

CXP81840A/81848A

(3) A/D converter characteristics

Item Symbol Pins

Resolution
Linearity error
Absolute error
Conversion time
Sampling time
Reference input voltage
Analog input voltage

tCONV
tSAMP

VREF
VIAN

IREF

AVREF current

IREFS

(Ta = –20 to +75°C, V

Item Symbol Pins

Resolution

(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V)

Conditions

Min.

Typ. Max.

8

Ta = 25°C

±1±2LSB
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V

∗

∗

AVDD

0

0.6

1.0

10

AVREF

AN0 to AN11

AVREF

VDD = AVDD = 4.5 to 5.5V

Operating mode

SLEEP mode
STOP mode

160/fADC

12/fADC

AVDD – 0.5

32kHz operating mode

DD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V)

Conditions

Min.

Typ. Max.

8

Unit

Bits

LSB

µs
µs

V
V

mA

µA

Unit

Bits
Linearity error
Absolute error
Conversion time
Sampling time
Reference input voltage
Analog input voltage

tCONV
tSAMP

VREF
VIAN

AVREF

AN0 to AN11

IREF

AVREF current

AVREF

IREFS

Fig. 6. Definitions of A/D converter terms

FFH
FEH

Digital conversion value

01H
00H

Linearity error

Analog input

Ta = 25°C
VDD = AVDD = AVREF = 3.3V
VSS = AVSS = 0V

VDD = AVDD = 3.0 to 3.6V

Operating mode

SLEEP mode
STOP mode
32kHz operating mode

∗

The value of fADC is as follows by selecting ADC
operation clock (MSC: Address 01FFH bit 0).
When PS2 is selected, fADC = fc/2
When PS1 is selected, fADC = fc

V

FTVZT

160/fADC

12/fADC

∗

AVDD – 0.3

0

±1±2LSB

LSB

∗

µs
µs

AVDD

V
V

0.4

0.7

10

mA

µA

– 22 –

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)

Item Symbol Pin Condition Min. Max. Unit

INT0

External interruption
high and low level widths

tIH
tIL

INT1
INT2
NMI

1

µs

PJ0 to PJ7

CXP81840A/81848A

Reset input low level width

Fig. 7. Interruption input timing

INT0
INT1
INT2
NMI
PJ0 to PJ7
(During standby release input)
(Falling edge)

Fig. 8. Reset input timing

RST

tRSL

RST

tIH tIL

0.8VDD

tRSL

0.2VDD

32/fc

µs

0.2VDD

(5) Others (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)

Item

EXI input high
and low level width

Symbol Pin Min.

tEIH
tEIL

EXI0
EXI1

Condition

tsys = 2000/fc

tsys + 200

Max. Unit

ns

Note) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11")
tFRC [ns] = 1000/fc

Fig. 9. Other timings

tEIH tEIL

EXI0
EXI1

0.8VDD

0.2VDD

– 23 –

Supplement

A

A

Fig. 10. Recommended oscillation circuit

(i) (ii)

CXP81840A/81848A

EXTAL

AAA

C

1 C2

Manufacturer

RIVER
ELETEC
CO., LTD.

KINSEKI LTD.

XTAL

Rd

Model

HC-49/U03

HC-49/U (-S)

P3

C

fc (MHz)

8.00

10.00

12.00

16.00

8.00

10.00

12.00 12

16.00

32.768kHz

TEX

AA

1

C1 (pF) C2 (pF) Rd (Ω)

10

16

16 12

12

30

TX

Rd

2

C

10

5

5

12

12
12
18 470k

Circuit

example

0

0

(i)

(i)

(ii)

Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).

Mask option table

Item

Reset pin pull-up resistor
Input circuit format

∗

The input circuit format can be selected each for PG4 pin and PG5 pin.
However, TTL schmitt can not be selected when the supply voltage (VDD) ranges from 3.0V to 5.5V.

∗

Non-existent

CMOS schmitt

Content

Existent

TTL schmitt

– 24 –

Characteristics Curve

CXP81840A/81848A

(fc = 16MHz, Ta = 25°C, Typical)

IDD vs. VDD

20.0

10.0

5.0

1.0

0.5

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

3

DD – Supply voltage [V]

V

45

1/2 dividing mode
1/4 dividing mode

1/16 dividing mode

SLEEP mode

32kHz mode
(instruction)

32kHz
SLEEP mode

6

72

(VDD = 5V, Ta = 25°C, Typical)

20

15

– Supply current [mA]

10

DD

I

5

0

5

fc – System clock [MHz]

IDD vs. fc

10

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

16

IDD vs. VDD

(fc = 12MHz, Ta = 25°C, Typical)

20.0

10.0

5.0

1.0

0.5

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

3

V

DD – Supply voltage [V]

45

1/2 dividing mode
1/4 dividing mode

1/16 dividing mode

SLEEP mode

6

72

(VDD = 3.3V, Ta = 25°C, Typical)

20

15

– Supply current [mA]

10

DD

I

5

0

510 16

fc – System clock [MHz]

IDD vs. fc

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode
SLEEP mode

– 25 –

Package Outline Unit: mm

100PIN QFP (PLASTIC)

23.9 ± 0.4
+ 0.4

20.0 – 0.1

+ 0.4

17.9 ± 0.4

14.0 – 0.01

+ 0.1

0.15 – 0.05

15.8 ± 0.4

CXP81840A/81848A

A

SONY CODE
EIAJ CODE

JEDEC CODE

75

76

0.65

0° to 15°

∗ 14.0 ± 0.1

±0.12

M

0.15

(16.3)

DETAIL A

QFP-100P-L01
∗QFP100-P-1420-A

0.8 ± 0.2

100PIN LQFP (PLASTIC)

16.0 ± 0.2

51

50

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL
PACKAGE WEIGHT

EPOXY RESIN
SOLDER PLATING

COPPER / 42 ALLOY

1.4g

+ 0.35

2.75 – 0.15

100

0.5 ± 0.08

SONY CODE
EIAJ CODE
JEDEC CODE

(15.0)

A

26

1

+ 0.08

0.18 – 0.03

(0.22)

25

+ 0.2

1.5 – 0.1

+ 0.05

0.127 – 0.02

0.5 ± 0.2

0.1

0.1 ± 0.1

NOTE: Dimension “∗” does not include mold protrusion.

0° to 10°

DETAIL A

LQFP-100P-L01
∗QFP100-P-1414-A

0.5 ± 0.2

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT

EPOXY/PHENOL RESIN
SOLDER PLATING
42 ALLOY

– 26 –