Datasheet cx25840 Datasheet

CX25840/1/2/3

Video Decoder and Broadcast Audio Decoder

Data Sheet

Production Data Sheet

102284B

August 2005

Ordering Information

Model Number Description Package

CX25840 Worldwide Video and BTSC (Basic) Broadcast Audio Decoder 80-pin QFP lead-free

CX25841 Worldwide Video and BTSC (dbx) Broadcast Audio Decoder 80-pin QFP lead-free

CX25842 Worldwide Video and European Broadcast Audio Decoder 80-pin QFP lead-free

CX25843 Worldwide Video and Worldwide Broadcast Audio Decoder 80-pin QFP lead-free

Revision History

Revision Level Date Description

A February 16, 2005

B August 3, 2005

© 2005, Conexant Systems, Inc.

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Initial Release

Engineering changes

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Macrovision

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Production Data Sheet

ii



is a registered trademark of Macrovision Corporation.

and the Conexant C symbol. Product names or services listed in this

which is incorporated by

Conexant 102284B

8/3/05

CX25840/1/2/3

Video Decoder and Broadcast Audio Decoder

Conexant Systems’ CX25840, CX25841, CX25842, and CX25843 video decoders
provide fourth-generation video and second-generation broadcast audio decoding
technology in a highly integrated, single-chip analog audio/video capture solution.
The product is ideal for digital video systems that need to digitize analog audio/video
content.

With numerous input ports and configurable output ports for 4:2:2 digital video and
linear PCM audio, the CX25840/1/2/3 can be used to capture video and audio from TV
tuners, DVD players, video cameras, VCRs, game consoles, or any other sources of
composite, Y/C or interlaced component standard-definition video. The level of audio
and video integration offered by the CX25840/1/2/3 removes the need for any
additional broadcast audio decoding and processing chip.

Worldwide decoding for all common video and broadcast audio standards is included
along with processing functions such as high-quality, five-line adaptive comb
filtering, arbitrary horizontal and 5-tap vertical scaling, hue, brightness, saturation,
and contrast controls. The audio path includes two assignable stereo processing units
for control of volume, three-band equalization, balance, and an automatic volume
control function.

The CX25840/1/2/3 has multiple power-down modes to fit your application and power
budget. It is available in a lead-free 80-pin, 12x12 mm TQFP package.

Distinguishing Features

 Integrated video and audio decoding
 Worldwide video standards—NTSC (M, J,

4.43), PAL (B, D, G, H, I, M, N, Nc),
SECAM (K, L),PAL-60

 Worldwide audio standards—BTSC, EIAJ,

A2, NICAM, FM/AM, High-deviation FM

 Full 10-Bit ADCs and data path
 Flexible video input mux supporting

composite, S-Video, and component
inputs with integrated anti-alias filtering

 Five-line adaptive comb filter for NTSC and

PAL

 Flexible video output port—27 MHz ITU-R

BT.656; VIP1.1, VIP2, or SPI video with
separate syncs for square pixel rates

 Macrovision
 Programmable VBI data slicer for data

services such as closed caption, WSS, and
program guides

 Power-up configurable two-wire serial

command interface or two-wire VIP1.1 or
VIP2 host port interface

 Multiple audio outputs—serial audio

interface or embedded as ancillary data in
the video stream

 AC’97 Audio codec interface
 Flexible sample rate conversion on all

audio inputs and outputs

 Hardware interrupt to eliminate polling
 Auto-detection and configuration for audio

and video

 Fast locking mode for security camera

applications

 Auxiliary clock output—for providing an

oversample audio clock. The PLL can be
locked to the video or used as a general
purpose PLL output

 Infrared transmit and receive logic
 Internal voltage regulation for single

supply operation

 The CX25840/1/2/3 is pin-compatible with

the CX25837



1.0 detection compliant

Production Data Sheet

102284B Conexant iii
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Functional Block Diagram

XTI

XTO

CVBS1/Y1

CVBS2/Y2

CVBS3/Y3

CVBS4/Y4/SIF1/Pb

CVBS5/C1/SIF2/Pb

CVBS6/C2/SIF3/Pb

CVBS7/C3/SIF4/Pr

CVBS8/C4/SIF5/Pr

BCLK_IN

WCLK_IN

SDIN

Master

Clock

Input

10-Bit

CVBS/

LUMA

ADC

10-Bit

Chroma/

Sound IF

Input MUX, Anti-alias Filter and AGC

Serial Audio In -

32, 44.1, 48,

16 - 24 Bit Samples

Master or Slave

ADC

96 kHz

VBI Data Slicer and Decoder

Video

Decoder -

NTSC, PAL,

SECAM

with 5-Line

Adaptive

Comb

Filter

Broadcast

Audio

Decoder -

BTSC, SAP,

EIAJ, A2,

NICAM,
FM, AM

Stereo Audio

Processing -

Tone, Volume,

Balance

Arbitrary

Horizontal

and Vertical

Multi-tap

Polyphase

Scaler

Stereo

Audio

Processing -

Tone,
Volume,
Balance

Stereo Audio Out -

32, 44.1, 48, 96 kHz

16 - 24 Bit Samples

Master or Slave

SDOUT

Audio Over -

Generic Clock

WCLK_OUTBCLK_OUT

Video

Output

Por t:

BT.656,

SPI,

VIP1.1,

VIP2.

I/O Pin

MUX

2-Wire

Serial

Command

or

VIP Host

I/F

Sample or

PIXCLK

VID_DATA[7:0]

VRESET/PRGM3
HRESET/PRGM2
FIELD/PRGM1
DVALID/PRGM0

IR_RX/PRGM5
IR_TX/PRGM6

GPIO1/PRGM9
GPIO0/PRGM8

SER_CLK/HAD[0]
SER_DATA/HAD[1]

CHIP_SEL/VIPCLK
HCTL/PRGM3
IRQ_N/PRGM4

PLL_CLK/PRGM7

GENERAL NOTE:

1. PRGMx pins are labeled with their default reset functions; however, they can be programmed to provide any of the
following internal functions: horizontal active, vertical active, Cb flag, 10-bit video data bits[1:0],
GPIO, or AC'97 link signals.

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Contents

Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1.1 Video Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.1.2 Audio Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.1.3 Communication and General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

3 Detailed Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Analog Subsystem Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 Video Mux Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2.1 General Muxing Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2.2 Configuring for Composite Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.3 Configuring for S-Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2.4 Configuring for Component Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2.5 Configuring for S-Video and Sound IF Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.3 Analog Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.3.1 Input Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.3.2 Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.3.3 Negative Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.3.4 Variable Gain Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.3.5 Anti-Alias Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.3.6 Channel Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.3.7 Analog to Digital Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.4 Digital Video Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.4.1 Video Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.4.2 AFE and Video Auto-Config. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.4.3 Video Standard Auto-Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

3.4.4 Signal Level Adjust in the Digital Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.4.5 Sample Rate Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.4.6 Source Locked Pixel Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.4.7 Vertical Sync Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

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CX25840/1/2/3 Data Sheet

3.4.8 Luma and Chroma Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22

3.4.9 Luma Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

3.4.10 Chroma Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

3.4.11 Copy Protection Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

3.4.12 Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

3.4.13 Fast Channel Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

3.4.14 Temporal Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34

3.5 Scaling and Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35

3.5.1 Horizontal Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35

3.5.2 Vertical Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37

3.5.3 Interpolation Filter and PAL Line Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

3.5.4 Chrominance Interpolation Filter and Resampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

3.5.5 Image Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

3.5.6 Horizontal Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

3.5.7 Vertical Cropping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

3.5.8 Scaling and Cropping Effects on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-41

3.6 VBI Data Slicer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42

3.6.1 VBI Data Slicer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42

3.6.2 VBI Standards Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42

3.6.3 VBI Waveform Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43

3.6.4 VBI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44

3.6.5 Preprogrammed VBI Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-46

3.6.6 Custom Data Transmission of VBI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47

3.6.7 Miscellaneous VBI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47

3.6.8 VBI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48

3.6.9 Clock Run-In Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48

3.6.10 VBI Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

3.6.11 Raw Mode VBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

3.7 Video Output Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

3.7.1 Output Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

3.7.2 Synchronous Pixel Interface Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-51

3.7.3 Control Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54

3.7.4 Ancillary Data Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55

3.7.5 Blue Field Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56

3.8 Infrared Remote Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57

3.8.1 Architecture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57

3.8.2 IR Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58

3.8.3 IR Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61

3.8.4 IR FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62

3.8.5 IR Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63

3.8.6 IR Status and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63

3.9 Auxiliary PLL, Video-Locked Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64

3.10 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66

3.11 Two-Wire Communications Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

3.11.1 Serial Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

3.11.2 Starting and Stopping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

3.11.3 Chip Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

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CX25840/1/2/3 Data Sheet

3.11.4 Reading and Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69

3.12 VIP 2 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70

3.12.1 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70

3.12.2 VIP Power-Up Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70

3.12.3 VIP Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71

3.13 Hardware Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72

3.14 I/O Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72

3.14.1 Output Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72

3.14.2 Input Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74

3.15 PLL Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76

3.16 Device Reset and Startup/Sleep Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77

3.17 Quick-Start Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80

3.18 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80

3.19 Audio Decoder Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81

3.20 Broadcast Audio Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83

3.20.1 Automatic Gain Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83

3.21 Broadcast Audio Demodulation and Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84

3.21.1 De-Emphasis Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84

3.21.2 Dematrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-86

3.22 Automatic Audio Detection and Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87

3.23 Embedded Microcontroller Audio Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88

3.23.1 Code Download Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88

3.23.2 Programming the Embedded Microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88

3.24 External Digital Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91

3.24.1 Serial Data Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92

3.24.2 Word Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93

3.24.3 Serial Audio Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93

3.24.4 Serial Audio Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94

3.24.5 AC’97 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94

3.25 Baseband Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99

3.25.1 Sample Rate Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100

3.25.2 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100

3.25.3 Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101

3.25.4 Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102

3.25.5 Tone Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102

3.25.6 AVC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104

3.25.7 Soft Clip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107

3.26 Quick Start Audio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108

4 Electrical Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Electrical Interface and Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.1 Board Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 Split Power Planes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.3 Latchup Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.4 Crystal Oscillator Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.4.1 On-Chip Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.5 Electrical Hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

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5 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 Register Type Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Register Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3 Serial Communications Host Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

5.4 VIP Communications Host Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

5.5 Chip Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

5.6 Video Decoder Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50

5.6.1 Basic User Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63

5.6.2 VBI Slicer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68

5.6.3 Autoconfiguration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85

5.6.4 Advanced Diagnostic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91

5.6.5 Soft Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98

5.7 Audio Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-100

5.7.1 Configuration Registers for Embedded Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-100

5.7.2 Registers 0x81C to 0x8CB for Analog and NICAM Demod: for Internal Microcontroller

Access Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108

5.7.3 Registers for Baseband Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108

5.7.4 AC’97 Codec Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-129

5.8 Autoconfiguration Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-133

6 Electrical/Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1

6.1 DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.3 Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

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Figures

Figure 2-1. SA_SDIN and SA_SDOUT Pin Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Figure 2-2. CHIP_SEL/VIPCLK/VIPCLK Pin Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Figure 2-3. CX25843, CX25842, CX25841, and CX25840 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Figure 3-1. AFE Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Figure 3-2. S-Video and Sound IF Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Figure 3-3. A Transfer Function of the Realized Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Figure 3-4. Video Decoder Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Figure 3-5. YC Separation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

Figure 3-6. Luma Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

Figure 3-7. Peaking Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

Figure 3-8. Chroma Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

Figure 3-9. SECAM Chroma Demod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

Figure 3-10. Horizontal Scaling Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35

Figure 3-11. Vertical Scaling Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37

Figure 3-12. Interpolation Filter Tap Selection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

Figure 3-13. Effect of the Cropping and Active Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40

Figure 3-14. Typical VBI Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43

Figure 3-15. Blanking Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45

Figure 3-16. Output Stream Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

Figure 3-17. SPI Mode External Field Timing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52

Figure 3-18. SPI Mode External Line Timing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53

Figure 3-19. SPI Mode VALID and CBFLAG Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53

Figure 3-20. Ancillary Region and Raw VBI Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56

Figure 3-21. Infrared System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57

Figure 3-22. IR Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58

Figure 3-23. IR Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61

Figure 3-24. Serial Start and Stop Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

Figure 3-25. Serial Communications Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69

Figure 3-26. Output Signals Connection and Routing to Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73

Figure 3-27. Reading the VACTIVE Signal on Pin 23 (DVALID/PRGM0) . . . . . . . . . . . . . . . . . . . . . . . 3-74

Figure 3-28. Input Signals Connection and Routing to Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75

Figure 3-29. Reading the Value of Pin 22 (FIELD/PRGM1) on Register 0x126 (GPI0) . . . . . . . . . . . . . 3-75

Figure 3-30. Audio Decoder Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82

Figure 3-31. De-Emphasis Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84

Figure 3-32. NICAM De-emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85

Figure 3-33. Serial Audio Interface Master and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91

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Figure 3-34. AC_LINK Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92

Figure 3-35. Right-Justified Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94

Figure 3-36. AC_LINK Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95

Figure 3-37. Slot Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95

Figure 3-38. Baseband Audio Processing Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99

Figure 3-39. Volume Control and Stereo Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-101

Figure 3-40. Shelving Filters Used for Boosting or Cutting Treble or Base . . . . . . . . . . . . . . . . . . . . 3-102

Figure 3-41. Peaking Filters Used for Boosting or Cutting Midtones . . . . . . . . . . . . . . . . . . . . . . . . . 3-103

Figure 3-42. 3-Band Tone Control Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103

Figure 3-43. Automatic Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104

Figure 3-44. Example of Compressor Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104

Figure 3-45. Effects of Compression on the Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105

Figure 4-1. Third Overtone Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Figure 4-2. Fundamental Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Figure 4-3. Single-Ended Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Figure 4-4. Analog Pin Hookups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Figure 6-1. Video Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Figure 6-2. Serial Audio Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Figure 6-3. 80-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

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Tables

Table 1-1. Part Number Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Table 2-1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Table 2-2. Common Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Table 3-1. Muxing Scheme for CH{1} . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Table 3-2. Muxing Scheme for CH{2} . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Table 3-3. Muxing Scheme for CH{3} . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Table 3-4. Example Composite Mux Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Table 3-5. Example S-Video Mux Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Table 3-6. Example Component Video Mux Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Table 3-7. Example S-Video and 2nd IF Mux Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Table 3-8. AFE Configuration for S-Video and Sound IF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Table 3-9. Clamping Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Table 3-10. Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Table 3-11. Anti-Alias Filter Characteristics Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Table 3-12. Analog Channel Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Table 3-13. ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Table 3-14. Video Format Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

Table 3-15. AFE Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

Table 3-16. AFE Control Auto-Config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

Table 3-17. Pixel Frequency Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

Table 3-18. Video PLL Auto-Config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

Table 3-19. Auto Format Detection Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

Table 3-20. Pixel Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

Table 3-21. Luma Output Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

Table 3-22. Chroma Saturation Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

Table 3-23. Chroma Coring Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

Table 3-24. Common Scaling Resolutions: HSCALE and VSCALE Values . . . . . . . . . . . . . . . . . . . . . . . 3-36

Table 3-25. Vertical Scaler Tap Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

Table 3-26. Available Preprogrammed VBI Slice Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

Table 3-27. Example 10-Byte Ancillary Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55

Table 3-28. 43 Locking Register Values for Common Audio Sample Rate . . . . . . . . . . . . . . . . . . . . . . 3-65

Table 3-29. Register Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66

Table 3-30. Chip Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

Table 3-31. VIP Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70

Table 3-32. Default PRGM[0:7] Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72

Table 3-33. Alternate PRGM[0:7] Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73

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Table 3-34. Alternate GPI0 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74

Table 3-35. PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76

Table 3-36. Video PLL Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76

Table 3-37. Reset Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79

Table 3-38. AFE Configuration for Sound IF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83

Table 3-39. Analog De-Emphasis Filtering for Audio Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85

Table 3-40. Dematrix Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-86

Table 3-41. Supported Audio IF Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87

Table 3-42. Parameters and Ranges for All Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100

Table 3-43. Available AVC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106

Table 3-44. Available Soft Clip Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107

Table 4-1. External Crystal Circuit Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Table 4-2. Voltage Regulator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Table 5-1. Register Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Table 5-2. Address Space Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Table 5-3. Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Table 5-4. Autoconfig Values for BT.656 Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-133

Table 5-5. Autoconfiguration Values for Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-133

Table 6-1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

Table 6-2. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

Table 6-4. Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Table 6-3. Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Table 6-5. Control Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Table 6-6. Serial Audio Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Table 6-7. Power Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

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1

Functional Overview

1.1 Introduction

Conexant Systems’ CX25840, CX25841, CX25842, and CX25843 video decoders
provide fourth-generation video and second-generation broadcast audio decoding
technology in a highly integrated, single-chip analog audio/video capture solution,
which removes the need for any additional broadcast audio decoding and processing
chips.

Worldwide decoding for all common video standards is common among all of the
models, along with processing functions such as high-quality, five-line adaptive comb
filtering, arbitrary horizontal and 5-tap vertical scaling, hue, brightness, saturation,
and contrast controls.

The part number differences provide affordable options for providing regional audio
support. The CX25840 (with no DBX), and CX25841 (with DBX), support both the
North American (BTSC) and Japanese (EIA-J) markets, respectively. The CX25842
supports the European market. And finally, for the customer who wants a single chip
to address all worldwide broadcast standards, there is the CX25843. This device
provides highly integrated, single-chip analog, A/V capture solutions ideal for digital
video systems that support worldwide broadcast analog A/V content. Tabl e 1 -1
provides part number definitions.

Table 1-1. Part Number Definitions

Part Number

CX25840 X

CX25841 X

CX25842 X

CX25843 X

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Worldwide Audio

Decoding

All are pin-to-pin compatible with each other, and are available in a lead-free 80-pin,
12x12 mm TQFP package.

A2, NICAM, FM, AM

Audio Decoding

BTSC (with DBX), EIA-J

Audio Decoding

BTSC (without DBX),

EIA-J Audio Decoding

Functional Overview CX25840/1/2/3 Data Sheet

1.1.1 Video Features

1.1.1.1 Analog Video Inputs

The CX25840/1/2/3 integrates two high-performance 10-bit Analog-to-Digital
Converters (ADCs) and provides a full 10-bit data path through the video decoder to
maintain optimum end-to-end video quality. Eight analog inputs are provided with
flexible analog muxing that can be configured for one or a combination of the
following audio and video inputs:

 Eight composite inputs
 Four Y/C inputs
 Two composite with one Y/C, one YPbPr, and one sound IF
 Four composite with four sound IF
 One composite with two YPbPr and one sound IF

Time multiplexing the various inputs to the chroma/sound ADC allows for the
simultaneous digitalization of Pb and Pr inputs in component mode, or chroma with
sound-IF for supporting Y/C sources with broadcast audio. All video inputs have
integrated anti-alias filters, eliminating the need for external filter components.

1.1.1.2 Integrated Clamping and Automatic Gain Control

DC restoration and Automatic Gain Control (AGC) are provided to compensate for
sources with differing average picture levels. Manual gain control is also supported.
Gain values can be read from and written to the device, allowing for the calibration of
each input and facilitating fast switching from one source to another.

1.1.1.3 Flexible Decoder Rates

The video data path includes a sample rate converter to enable multiple pixel rates and
to track any timing fluctuations that may be present within the video source. With the
sample rate converter, the user can program the device to decode video at output pixel
rates of either 13.5 MHz for an ITU-R BT.656 compliant output stream or at

12.27 MHz and 14.75 MHz for NTSC and PAL/SECAM square pixel rates,
respectively. The sample rate converter with internal FIFO monitors the horizontal
timing of the input source to create a fixed number of samples per line. It controls a
PLL to slowly adjust the FIFO level such that short-term jitter in the input source is
filtered out of the digitized video stream. This provides stable video data and output
clocks, even with sources like VCRs that can have inherently unstable timing.

1.1.1.4 High Performance Filtering

Luma/chroma separation of composite video sources is accomplished through a 5-line
adaptive chroma comb filter for NTSC and PAL standards. The adaptive comb filter
looks across five lines of incoming video and determines which of the five lines are
appropriately correlated enough to average together. Depending on the amount of
correlation among the lines, two or three lines are averaged together to form the
resulting combed filtered line. In the case where no correlation exists between lines,
the decoder automatically falls back to chroma band-pass and luma notch filtering.
The output of the chroma comb filter is also remodulated and fed back into the luma
channel. The result is a high quality image with reduced cross-chrominance and cross­luminance artifacts—such as dot crawl, hanging dots, rainbow effects—that restore
full bandwidth to luminance data from composite sources. Additionally, we have a

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CX25840/1/2/3 Data Sheet Functional Overview

SECAM “Bell” filter to improve SECAM luminance and chroma separation. This is
because SECAM uses an FM modulated signal carrier that is always present,
regardless of whether or not there is color information being broadcast. This results in
a visible artifact in the luminance at the carrier frequency. To eliminate this effect, an
“Inverse Bell” filter is applied at the encoder to attenuate color frequencies near the
Dr and Db carriers. Thus, if little or no color information is present in the signal, the
carriers will be reduced in amplitude.

1.1.1.5 Video Processing Functions

Back-end video processing functions include contrast, brightness, hue, saturation, and
scaling. In addition, the luma data path provides white crush compensation for sources
that exceed sync tip to white level ratios. The decoder also provides four sets of
selectable peaking filters for sharpening the image. The luma data output range is
selectable so that luma codes can be limited to the nominal ITU-R BT.656 code range,
or can support values below black level, or can use the entire 10-bit range of values
where 0 is black level, and 1023 is nominal white. Additional chroma functions
include AGC to compensate for attenuated color subcarriers, a color killer for true
black and white sources, and coring for limiting low-level chroma noise.

1.1.1.6 High Quality Scaling

Arbitrary horizontal and vertical scaling is available, from full resolution down to an
8:1 ratio (icon size). Scaling can be accomplished in both VIP and BT.601 square
pixel formats. To maintain a high quality scaled image, multi-tap polyphase
interpolation is used. The horizontal luma scaler uses 6-tap, 63-phase FIR
interpolation between horizontal source samples, while the horizontal chroma scaler
uses 4-tap, 63-phase interpolation. Line store memory is integrated into the decoder
so that the vertical scaler—depending on the horizontal scaling ratio—can use from
2-tap to 5-tap, seven-phase interpolation between lines.

1.1.1.7 Configurable Pixel Output Interface

The pixel output format is user-configurable and can conform to 4:2:2 ITU-R BT.656
with embedded timing codes, VIP1.1 or VIP2 with embedded timing codes, or SPI­coded video samples with separate sync signals. The pixel output interface can also be
set up for 8-bit or 10-bit sample widths, where 8-bit data is derived from the rounded
10-bit value. In addition to providing decoded video data during the active region, raw
sample data can be obtained during the horizontal region of the vertical blanking
interval. The raw data is from the luma/composite ADC after it has been sample-rate
converted and 2x upsampled. This data can be used for capturing high-bit rate VBI
services like Teletext for later use by software decoders. The pixel output port also
makes use of ancillary data streams by inserting sliced VBI data during the horizontal
blanking interval.

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Functional Overview CX25840/1/2/3 Data Sheet

1.1.1.8 Vertical Blanking Interval Data Slicing and Decoding

An integrated VBI data slicer supports a variety of data standards: WST, Closed
Caption, WSS, VITC, as well as programming guide information like Gemstar 1x,
Gemstar 2x, and VPS. Decoded data for closed caption, WSS, and Gemstar services is
available through either a register read or can be inserted as ancillary data within the
ITU-R BT.656 data stream. For high-bit rate services such as WST, NABTS, VPS,
and VITC, data is provided on the pixel output port and can be inserted as ancillary
data as well. There is independent control of what data service is to be sliced/decoded
for every line of each field in the vertical interval. Programmability is also provided
such that custom data slicing can be accomplished for data services that do not
comply with one of the standards already supported.

1.1.2 Audio Features

1.1.2.1 Stereo Broadcast Audio Decoding

The CX25843, CX25842, CX25841, and CX25840 integrate a stereo broadcast audio
decoder capable of demodulating all of the most common worldwide audio standards:
BTSC, EIAJ, A2, NICAM, FM (standard and high-deviation modes), and AM. The
sound IF output from the tuner interfaces directly with the CX25840/1/2/3,
eliminating the need for external sound demodulation chips. Dual language,
subchannel, and Secondary Audio Formats (SAP) are also supported for broadcasts
that transmit multilingual capability. Simultaneous dual language can be supported
with different languages on each channel of the stereo left/right pair. The audio
decoder has automatic standard detection and configuration through an on-board
microprocessor so that no user intervention is necessary to set up the decoder for the
various standards. This is especially useful in geographic regions where different
audio standards may be received on a channel-by-channel basis.

1.1.2.2 Audio Interfaces

Demodulated broadcast audio is available through two interfaces, serial audio output
or embedded in the ITU-R BT.656/VIP pixel port as ancillary data. The serial audio
output port can supply audio samples from the broadcast decoder or from the serial
audio input port. An internal sample rate converter allows for selection of 32 kHz,

44.1 kHz, 48 kHz, or 96 kHz sample rate for easy system integration. This sample rate
conversion is available for both the serial audio (input and output) and BT.656/VIP
interfaces, independent of one another. In the BT.656/VIP mode, audio samples are
embedded into the video stream and are tagged as ancillary data during the horizontal
blanking interval. This allows for the capture of audio samples on systems that do not
provide serial audio interfaces. The CX25840/1/2/3 also provides a serial audio input
and an AC’97 link interface for extensible baseband audio capture and playback.
Adding an AC’97 audio codec provides support for multiple audio inputs and outputs
for systems that require a broad range of audio interfaces. The serial audio interfaces
support programmable master/slave modes and 16- to 32-bit sample widths.

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CX25840/1/2/3 Data Sheet Functional Overview

1.1.2.3 Audio Processing

In addition to the demodulation of broadcast audio in the CX25840/1/2/3, premium
functions such as three-band equalization, volume, balance, mute, and automatic
volume control are independently available on both the broadcast audio and serial
audio data streams. The audio samples can also be locked to the incoming video
stream to ensure that the audio samples are rate-matched to the video, eliminating the
need for MPEG encoders to drop or repeat frames in order to keep the video and audio
in sync. The entire audio data path is a minimum of 16 bits wide to maintain CD
quality performance levels throughout the audio signal chain.

1.1.3 Communication and General Features

Communication with the device is configurable through a pin strap option at power-up
reset. Two methods of communication are available: either a 400 kHz two-wire serial
command interface or a 2-bit VIP host port interface. A hardware interrupt pin is
available along with a maskable interrupt status register so that the device can notify
the system when internal events occur without the need to implement polling
schemes.

Other convenience features consist of the following:

 Programmable infrared transmitter/receiver logic, able to modulate or demodulate

low data rate consumer remote control protocols

 General purpose I/O pins
 Power-down pin or register-controlled power-down levels
 Single 3.3 V power supply configuration available with an external pass transistor
 PLL output for either supplying a video locked 256x/384x oversample audio clock

or a general purpose user programmable clock for minimizing PCB component
count

 Small package size: a 80-pin, 12x12 mm TQFP
 All parts are only available in a lead-free package, beginning with -23. Starting

with -24, this is indicated with a “Z” following the dash number, i.e., “-24Z.”

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Functional Overview CX25840/1/2/3 Data Sheet

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2

Pin Descriptions

2.1 Pin Descriptions

See Table 2 -1 for pin descriptions.

Table 2-1. Pin Descriptions (1 of 4)

Pin Name Pin Dir Type Description: {20} ADC Analog

CVBS{1:3}/Y{1:3} 58, 60, 61I As Composite or Luma signal input to ADC1. The signal passes through on-chip

analog multiplexers before passing through a gain stage, an anti-alias filter stage,
and into ADC1. Unused inputs should be left floating.

CVBS{4:6}/Y4/C{1:2}/
SIF{1:3}/Pb{1:2}

CVBS{7:8}/C{3:4}/
SIF{4:5}/Pr{1:2}

IREF 66 I/O Ar Current reference pin. Connect 30 kΩ, 5% precision resistor to ground.

VAA_ADC{1:2} 53, 56 I Ap ADC core power, one for each ADC. VAA_ADC = 3.3 V nominal.

VSS_ADC{1:2} 54, 55 I Ap ADC core ground, one for each ADC.

VAA_CH{1:2} 62, 70 I Ap Analog channel 1 and 2 (clamp, single-to-diff, VGA, filter) power. VAA_CH = 3.3 V

VSS_CH{1:2} 64, 72 I Ap Analog channel 1 and 2 (clamp, single-to-diff, VGA, filter) ground.

ASUB 57 I Ap ADC core substrate ground.

S2D_NEG{1:2} 59, 68 I Ar Negative input of single-to-differential converter. Tie to analog ground through AC

63, 65, 67I As Chroma, Sound IF, or Pb signal input to ADC2 or Luma, Composite signal input to

ADC1. This signal passes through on-chip analog multiplexers before passing
through a gain stage, an anti-alias filter stage, and into either ADC1 or ADC2. In
color component (Pb, Pr) input mode, the Pb component should be connected to
one of these pins, and the Pr component should be connected to the Pr{1:2} pins.
Unused inputs should be left floating.

69, 71 I As Chroma, Sound IF or Pr signal input to ADC2 or Luma, Composite signal input to

ADC1. This signal passes through on-chip analog multiplexers before passing
through a gain stage, an anti-alias filter stage, and into either ADC1 or ADC2. In
color component (Pb, Pr) input mode, the Pr component should be connected to
this pin, and the Pb should be connected to a Pb{1:2} pin. Unused inputs should be
left floating.

nominal.

coupling capacitor for common mode noise rejection. The capacitor should match
the value used on the analog inputs.

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Pin Descriptions CX25840/1/2/3 Data Sheet

Table 2-1. Pin Descriptions (2 of 4)

Pin Name Pin Dir Type Description: {10} Crystal and PLLs

XTI 74 I As 28.63636 MHz crystal oscillator input, or single-ended clock oscillator input. Used

for PLL clock reference and ADC sample clock.

XTO 75 I/O As Crystal buffer return, or DC reference input for single-ended clock oscillator mode.

VAA_XTAL 76 I Ap Crystal oscillator power. VAA_XTAL = 3.3 V nominal. Couple to VAA.

VSS_XTAL 73 I Ap Crystal oscillator ground. Couple to VSS_A.

VPP{0:1} 48, 49 O Ap Internal PLL power decoupling node. Decouple through 0.1uF capacitor to ground.

VSS_PLL 50 I Ap Shared PLL ground. Couple to VSS_A.

VDDO_PLL 47 I Dp Output pad ring power for PLL_CLK/PRGM7 pad. Isolated from the rest of the pad

ring for noise immunity. VDDO_PLL = 3.3 V nominal. VDDO_PLL should be
connected to analog supply if PLL_AUX_CLK pin is providing a sample clock for an
external ADC or DAC. If PLL_CLK/PRGM7 pin is used as a digital output, then
VDDO_PLL should be connected to a digital supply. Refer to footnote (1) of

Section 4.5 for more information.

VSSO_PLL 45 I Dp Output pad ring ground for PLL_CLK/PRGM7 pad. Isolated from the rest of the pad

ring for noise immunity. Couple to VSS_A. VSSO_PLL should be connected to
analog ground if PLL_AUX_CLK is providing a sample clock for an external ADC or
DAC. If PLL_CLK/PRGM7 is used as a digital output, then VSSO_PLL should be
connected to digital ground.

PLL_CLK/PRGM7 46 O D General purpose output clock from a second PLL or can also be used for 256x (or

384x) oversampled clock for external Sigma-Delta Audio ADCs and DACs. This PLL
can optionally be locked to the video pixel rate for video-locked audio clock.

Pin Name Pin Dir Type Description: {12} Digital Power Supply

REG_IN 51 I As Regulator In. An internal regulator monitors this voltage level from the emitter/drain

of an external voltage drop transistor.

REG_OUT 52 O As Regulator Out. An internal 1.2 V regulator drives this signal out to control the base/

gate of an external voltage drop power transistor. When using an externally
provided 1.2 V for VDD tie REG_OUT to REG_IN.

VDD {1:6} 6, 14,

20, 31,
38, 80

VSS {1:6} 5, 13,

19, 30,
37, 79

VDDO{1:3} 11, 28, 77I Dp I/O pad ring power, VDDO = 3.3 V, nominal.

VSSO{1:3} 12, 29, 78I Dp I/O pad ring ground.

I Dp Digital core power. VDD = 1.2 V, nominal. Connect to regulator-generated voltage

REG_IN pin or external power supply.

I Dp Digital core ground.

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CX25840/1/2/3 Data Sheet Pin Descriptions

Table 2-1. Pin Descriptions (3 of 4)

Pin Name Pin Dir Type Description: {4} Control interface: Serial or VIP Host Port

SER_CLK/HAD[0] 16 I/O Od Serial communications clock or VIP host address/data bit 0. Used for accessing

internal registers.

SER_DATA/HAD[1] 15 I/O Od Serial communications data or VIP host address/data bit 1. Used for accessing

internal registers.

CHIP_SEL/VIPCLK/
VIPCLK

VRESET/HCTL/
PRGM3

Pin Name Pin Dir Type Description: {12} Video Output Signals

PIXCLK 36 O D Pixel clock. Operates at 27.0 MHz and for square pixel formats, 29.5 MHz (625-line)

VID_DATA[7:0] 24 25,

HRESET/PRGM2 21 I/O D Horizontal reset timing indication is the default pin function. Alternatively, the pin can

FIELD/PRGM1 22 I/O D Field indication is the default pin function. Alternatively, the pin can be programmed

DVALID/PRGM0 23 I/O D Data valid indication is the default pin function. Alternatively, the pin can be

17 I D Serial communications mode chip select. Selects 7-bit serial chip address:

0: 1000100 (0x88 write, 0x89 read)
1: 1000101 (0x8A write, 0x8B read)
VIP host port clock in VIP host mode.
Can also be configured for GPIO and video timing control if interrupt not needed. In

VIP Host port mode, this also acts as the VIRQ_N signal. Also acts as a pin strap
option during reset. If the IRQ_N pin is low during the deassertion of RESET_N the
device will respond to the alternate two-wire serial communications address:

0x8C/0x8D when CHIP_SEL/VIPCLK/VIPCLK pin is low
0x8E/0x8F when CHIP_SEL/VIPCLK/VIPCLK pin is high
If the pin is high during the deassertion of RESET_N the device will respond to the

default two-wire serial communications addresses:
0x88/x89 when CHIP_SEL/VIPCLK/VIPCLK pin is low
0x8A/0x8B when CHIP_SEL/VIPCLK/VIPCLK pin is high

18 I/O D, R In VIP host port mode acts as control pin that is used to begin, end, or throttle data

transfers. VIP host port available only on CX25837. When the device is in serial
communications mode the pin acts as VRESET or can be configured for alternate
pin functions.

and 24.545 MHz (525-line).

O D Eight most significant bits of rounded video data. Data is output in a YCrCb 4:2:2
26, 27,
32, 33,
34, 35

format. For 10-bit mode, the fractional, least significant two bits can be programmed
to be output on any of the PRGMx pins

be programmed to function as a different video timing control; least significant video
data bits or GPIO. See Ta ble 2 -2 and Figures 2-1 and 2-2 for the available
programmable alternative functions.

to function as a different video timing control; least significant video data bits or
GPIO. See Table 2 -2 and Figures 2-1 and 2-2 for the available programmable
alternative functions.

programmed to function as a different video timing control; least significant video
data bits or GPIO. See Ta ble 2 -2 and Figures 2-1 and 2-2 for the available
programmable alternative functions.

Pin Name Pin Dir Type Description: {2} Infrared

IR_TX/PRGM6 8 O D, R Infrared remote control transmit output. Can also be configured for GPIO and video

timing control if infrared control is not needed. Also acts as a pin strap option during
reset. If the pin is low during the deassertion of RESET_N the device will boot-up in
VIP host port communications mode. If the pin is high during the deassertion of
RESET_N the device will boot-up in two-wire serial communications mode.

IR_RX/PRGM5 9 I D Infrared remote control receive input. Can also be configured for GPIO and video

timing control if infrared control is not needed.

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Pin Descriptions CX25840/1/2/3 Data Sheet

Table 2-1. Pin Descriptions (4 of 4)

Pin Name Pin Dir Type Description: {4} Chip Control

IRQ_N/PRGM4 10 O D, R Interrupt output, active low. Can also be configured for GPIO and video timing

control if interrupt not needed. In VIP Host port mode, this also acts as the VIRQ_N
signal. Also acts as a pin strap option during reset. If the pin is low during the
deassertion of RESET_N the device will respond to the alternate two-wire serial
communications address:

0x8C/0x8D when CHIP_SEL/VIPCLK/VIPCLK pin is low
0x8E/0x8F when CHIP_SEL/VIPCLK/VIPCLK pin is high
If the pin is high during the deassertion of RESET_N the device will respond to the

default two-wire serial communications addresses:
0x88/x89 when CHIP_SEL/VIPCLK pin is low
0x8A/0x8B when CHIP_SEL/VIPCLK pin is high

RESET_N 2 I D Global chip reset, active low.

SLEEP 3 I D A logic high state on this pin puts the chip in power-down mode.

TEST 1 I D Puts chip in test mode. Pin is tied low for normal operation.

Pin Name Pin Dir Type Description: {6} Serial Digital Audio

SA_BCLK_IN 43 I/O D Serial audio bit clock for input data.

SA_WCLK_IN 42 I/O D Serial audio word/framing clock for delineating input sample boundaries.

SA_SDIN 44 I D Serial audio data input.

SA_BCLK_OUT 41 I/O D Serial audio bit clock for output data.

SA_WCLK_OUT 40 I/O D Serial audio word/framing clock for delineating output sample boundaries.

SA_SDOUT 39 O D Serial audio data output.

Pin Name Pin Dir Type Description: {2} GPIO

GPIO{0:1}/
PRGM{8:9}

R
Od
As
Ap
Dp
Ar
D

GENERAL NOTE:

1. All signal I/O are LVTTL compatible.

2. All inputs are Schmitt unless otherwise noted.

3. All outputs have drive capability I

7, 4 I/O D Configurable Multifunction Status/Control Pins.

Legend for Pin Type

Active resistive pullup
Open-drain pads with glitch filters
Analog signal
Analog power or ground
Digital power or ground
Analog reference, for connection to external component
Digital Signal

= 4 mA unless otherwise noted.

OL

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CX25840/1/2/3 Data Sheet Pin Descriptions

The following set of common pins are multifunctional and can have signals routed in
and out. Tabl e 2-2 lists these common pins. Figure 2-1 shows the registers to which
any signal can be routed. In addition, the SA_SDIN and SA_SDOUT pins can be
routed to the registers in Figure 2-1.

Figure 2-1 shows the signals that can be routed to any pin in the common list. The

CHIP_SEL/VIPCLK/VIPCLK pin can also be routed to the signals in Figure 2-2.
Refer to Section 3.14, I/O Pin Configuration, for details.

Table 2-2. Common Pins

DVALID/PRM0

FIELD/PRGM 1

HRESET//PRGM2

VRESET/HCTL/PRGM3

IRQ_N/PRGM4

IR_TX/PRGM6

IR_RX/PRGM5

GPIO[0]/PRGM8

GPIO[1]/PRGM9

Figure 2-1. SA_SDIN and SA_SDOUT Pin Routing

Common Pins

Extra Pins:

SA_SDIN

SA_SDOUT

PLL_CLK/PRGM7

GPI Input Registers

GPI0
GPI1
GPI2
GPI3

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Pin Descriptions CX25840/1/2/3 Data Sheet

Figure 2-2. CHIP_SEL/VIPCLK/VIPCLK Pin Routing

Output Signals

ACTIVE
VACTIVE
CBFLAG
VID_DATA_EXT[0]
VID_DATA_EXT[1]
GPO[0]
GPO[1]
GPO[2]
GPO[3]
IRQ_N
AC_SYNC
AC_SDOUT
PLL_CLK
VRESET

Common Pins

CHIP_SEL/VIPCLK

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CX25840/1/2/3 Data Sheet Pin Descriptions

Figure 2-3. CX25843, CX25842, CX25841, and CX25840 Pinout

VDD

VSS

VSSO

VDDO

VAA_XTAL

XTO

XTI

VSS_XTAL

VSS_CH2

CVBS8/C4/SIF5/Pr2

VAA_CH2

CVBS7/C3/SIF4/Pr1

S2D_NEG2

CVBS6/C2/SIF3

IREF

CVBS5/C1/SIF2/Pb2

VSS_CH1

CVBS4/Y4/SIF1/Pb1

VAA_CH1

CVBS3/Y3

TEST

RESET_N

SLEEP

GPIO[1]/PRGM9

VSS

VDD

GPIO[0]/PRGM8

IR_TX/PRGM6

IR_RX/PRGM5

IRQ_N/PRGM4

VDDO

VSSO

VSS

VDD

SER_DATA/HAD[1]

SER_CLK/HAD[0]

CHIP_SEL/VIPCLK

VRESET/HCTL/PRGM3

VSS

VDD

80797877767574737271706968676665646362

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21222324252627282930313233343536373839

VID_DATA[7]

FIELD/PGRM1

HRESET/PRGM2

VID_DATA[6]

DVALID/PRGM0

80-Pin TQFP

12 x 12 x 1 mm Body Size

0.5 mm Pin Pitch

VSS

VDD

VSSO

VDDO

VID_DATA[5]

VID_DATA[4]

VID_DATA[3]

VID_DATA[2]

VID_DATA[1]

PIXCLK

VID_DATA[0]

VSS

VDD

61
60

59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40

SA_SDOUT

SA_WCLK_OUT

CVBS2/Y2
S2D_NEG1
CVBS1/Y1
ASUB
VAA_ADC1
VSS_ADC1
VSS_ADC2
VAA_ADC2
REG_OUT
REG_IN
VSS_PLL
VPP0
VPP1
VDDO_PLL
PLL_CLK/PRGM7
VSSO_PLL
SA_SDIN
SA_BCLK_IN
SA_WCLK_IN
SA_BCLK_OUT

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3

Detailed Functional Description

3.1 Analog Subsystem Overview

The CX25840/1/2/3 integrate all Analog Front-end (AFE) functions required for
filtering, gaining, clamping, and digitizing an analog video signal. The AFE is
comprised of the following blocks:

 Three analog muxes
 Clamping and impedance boosting circuitry
 Three single-ended to differential converters
 Three Variable Gain Amplifiers (VGA)
 Three anti-alias filters
 A bandgap reference
 Two Analog-To-Digital Converters (ADC)
 A crystal oscillator amplifier
 Two Phase Locked Loops (PLL)

A block diagram of the signal flow through the analog subsystem is shown in

Figure 3-1.

Figure 3-1. AFE Overview

IN1
IN2
IN3

IN4

IN5

IN6

IN7

IN8

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CH1

-12dB ... +6dB 0dB ... +6dB

CH2

-12dB ... +6dB 0dB ... +6dB

CH3

-12dB ... +6dB 0dB ... +6dB

Filter

Tuning

Filter

Tuning

Filter

Tuning

11

ADC1

11

ADC2

102267_001

Detailed Functional Description CX25840/1/2/3 Data Sheet

The AFE receives eight video inputs that are multiplexed to produce inputs for the
three analog channels: CH1, CH2, or CH3. Each analog channel has a variable gain
amplifier and anti-alias filter that can be independently configured. The CH1 signal is
routed through ADC1, while CH2 and CH3 can be statically shared or time­multiplexed on Miscellaneous Chip Control.

After the input mux, the video signal is clamped to the midpoint of the single-to­differential amplifier for DC restoration. Next, the signal is converted from single­ended to differential, and then amplified or attenuated through the two gain stages.
The gain settings for the VGA come from the video decoder feedback loop, although
this can be disabled and a manual gain value set instead.

The output of the VGA is then low-pass filtered prior to the ADC to prevent high­frequency noise near the sampling frequency from being aliased back onto the signal
by the sampling process. The bandwidth of the anti-alias filter is programmable for
either 8 MHz, half this bandwidth, or completely bypassed.

ADC1 then samples the DC-restored and gained differential video waveform using
the external crystal frequency. Miscellaneous Chip Control also samples its
differential inputs at the crystal frequency, but the video input can be enabled to time
multiplex between the CH{2} and CH{3} inputs. An internal mux switches between
the two channels fast enough to support the sampling of the Pb and Pr chroma signals
of an interlaced component video input through one ADC.

The clock for the video decoder’s digital domain comes from a fractional PLL that
converts the crystal frequency to a clock that is a multiple of the video pixel rate. For
example, in ITU-R BT.656 mode, the internal clock runs at 8 times the 13.5 MHz
pixel rate, 108 MHz. The digital logic adjusts the frequency in small increments to
track the field rate of the decoded video signal, producing a video-locked clock.

Additionally, a second PLL output, AUX_CLK, is provided and can be used as a
video-locked oversample audio clock reference for any external audio components.
This clock would usually be programmed to be either 384 or 256 times the audio
sample rate, but may be any desired multiple of the audio sample rate. The PLL can
also be used as a general clock source, unlocked to the video input and programmable
to any arbitrary frequency.

A bandgap design is used as an internal voltage reference generator. Its output is
connected to a pin for external filtering. Another circuit converts this bandgap
reference voltage to a precision current reference. This circuit relies upon an external
high-precision resistor connected to the IREF pin to generate this current.

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CX25840/1/2/3 Data Sheet Detailed Functional Description

3.2 Video Mux Inputs

3.2.1 General Muxing Scheme

The analog front-end of the decoder supports up to eight composite video inputs (In1–
In8), four S-Video inputs, or two component inputs. Analog muxes connect the inputs
to CH{1}, CH{2}, or CH{3} so that any one of eight inputs can be connected to
CH{1}, any one of inputs In4, In5, or In6 can be connected to CH{1} or CH{2}, and
any one of inputs In7 or In8 can be connected to CH{1} or CH{3}. The muxes are
controlled through the Video Input Control register (0x103) with bits CH{1}_SRC,
CH{2}_SRC, and CH{3}_SRC, as shown in Tables 3 -1 through 3-3.

Table 3-1. Muxing Scheme for CH{1}

Video Input Control (0x103)

CH{1}_SRC Bits [2:0]

000 In1

001 In2

010 In3

011 In4

100 In5

101 In6

110 In7

111 In8

Table 3-2. Muxing Scheme for CH{2}

Video Input Control (0x103)

CH{2}_SRC Bits [5:4]

00 In4

01 In5

10 In6

Input Connected to CH{1}

Input Connected to CH{2}

11 None

Table 3-3. Muxing Scheme for CH{3}

Video Input Control (0x103)

CH{3}_SRC Bits [7:6]

00 In7

01 In8

10 None

11 None

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Input Connected to CH{3}

Detailed Functional Description CX25840/1/2/3 Data Sheet

Although it is possible to connect inputs In4–In8 to two channels simultaneously, this
is not recommended.

When an internal input is not connected to any channel, it is connected to a voltage
approximately one half of the supply voltage through a high resistance. The maximum
allowed input signal amplitude is 2.0 Vp-p.

3.2.2 Configuring for Composite Inputs

In this usage scenario, up to eight composite inputs can be connected to the decoder.
As shown in Figure 3-1, it is possible to connect all eight composite inputs to CH{1}
so that only one ADC is being used. Since Miscellaneous Chip Control is not being
used, it can be turned off to conserve power. It is important to note that although
inputs IN1 through IN8 can be connected, only one input can be active at any one
time.

To configure the decoder to accept one of eight possible composite video inputs using
just one ADC, the Video Input Control (0x103) register must be programmed as
described in Tab le 3-4.

Table 3-4. Example Composite Mux Configuration

Active Input Control Bits Bit Value

CVBS {1}

CVBS {2} 001

CVBS {3} 010

CVBS {4} 011

CVBS {5} 100

CVBS {6} 101

CVBS {7} 110

CVBS {8} 111

CH{1}_SRC

CH{3}_SRC 10 OR 11

CH{2}_SRC 11

000

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3.2.3 Configuring for S-Video

It is possible to configure the input mux to accept an S-Video input source. In this
case, two channels of the AFE must be used. The luma portion of the S-Video input
must be routed to CH{1} and the chroma signal routed to CH{2} or CH{3}. There are
enough inputs and analog channels to support multiple S-Video inputs. For example,
up to four S-Video inputs can be connected at the same time by using inputs In1 to In4
as luma inputs and In5 to In8 as chroma inputs, as shown in Table 3-5.

Table 3-5. Example S-Video Mux Configuration

Active Input Control Bits Bit Value

Y1 CH{1}_SRC 000

C1 CH{2}_SRC 01

Y2 CH{1}_SRC 001

C2 CH{2}_SRC 10

Y3 CH{1}_SRC 010

C3 CH{3}_SRC 00

Y4 CH{1}_SRC 011

C4 CH{3}_SRC 01

To configure the rest of the AFE for S-Video mode, see Section 3.4.1.

3.2.4 Configuring for Component Video

In this scenario, the input mux is used to route component video, YPbPr signals to
each of the analog channels. To support component video, all three channels of the
AFE are used. CH{1} handles the luma (Y) signal, and CH{2} and CH{3} handle the
Pb and Pr color-difference signals. The chroma inputs are time-multiplexed to carry
out dual sampling using Miscellaneous Chip Control. A total of two component inputs
can be supported, although only one can be active at any time. For example, In1 and
In2 are Y inputs, In4 and In5 are Pr inputs, and In7 and In8 are Pb inputs. The Video
Input Control (0x103) register must be programmed as shown in Table 3 -6 .

Table 3-6. Example Component Video Mux Configuration

Active Input Control Bits Bit Value

Y1 CH{1}_SRC 000

Pr1 CH{2}_SRC 00

Pb1 CH{3}_SRC 00

Y2 CH{1}_SRC 001

Pr2 CH{2}_SRC 01

Pb2 CH{3}_SRC 01

To configure the rest of the AFE for component video mode, see Section 3.4.1.

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Detailed Functional Description CX25840/1/2/3 Data Sheet

3.2.5 Configuring for S-Video and Sound IF Audio

In this scenario, the input mux is used to route S-Video and the Sound IF audio
source. In this case, all three channels of the AFE are used. As shown in Ta bl e 3 -7 , the
luma portion of the S-Video input must be routed to CH{1}, the chroma portion of the
S-Video input must be routed to CH{3}, and the Sound IF audio of the tuner input
must be routed to CH{2}.

Table 3-7. Example S-Video and 2nd IF Mux Configuration

Active Input Control Bits Bit Value

Y1 CH{1}_SRC 000

C1 CH{3}_SRC 00

2nd IF 1 CH{2}_SRC 00

Y2 CH{1}_SRC 001

C1 CH{3}_SRC 01

2nd IF 2 CH{2}_SRC 01

Table 3 -8 summarizes the state of the AFE control bits for S-Video and Sound IF

operation. Figure 3-2 shows the S-Video and Sound IF Audio Interface.

Table 3-8. AFE Configuration for S-Video and Sound IF Input

Control Bits Value

INPUT_MODE 10

CLAMP_SEL_CH{1} 0

CLAMP_SEL_CH{2} 1

CLAMP_SEL_CH{3} 0

DUAL_MODE_ADC2 1

HALF_BW_CH{2}/3 CH{2} = 0 (Chroma input on analog CH3)

CH{3} = 0 (Sound IF input on analog CH2)

DROOP_COMP_CH{2}/3 CH{2} = 0 (Chroma input on analog CH3)

CH{3} = 0 (Sound IF input on analog CH2)

CLAMP_EN_CH{2}/3 CH{2} = 0 (Chroma input on analog CH3)

CH{3} = 0 (Sound IF input on analog CH2)

AUD_IN_SEL 1

VGA_SEL_CH{2}/3 CH{2} = 0 (Chroma input on analog CH3)

CH{3} = 0 (Sound IF input on analog CH2)

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CX25840/1/2/3 Data Sheet Detailed Functional Description

Figure 3-2. S-Video and Sound IF Audio Interface

1 µF

Luma

75 Ω

1 µF

Chroma

75 Ω

120 pF

Sound IF

Analog Channel 1

Analog Channel 2

Analog Channel 3

ADC 1

ADC 2

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Detailed Functional Description CX25840/1/2/3 Data Sheet

3.3 Analog Channel

The features described in this section are automatically configured by default, but
they can be manually configured as described below.

3.3.1 Input Impedance

Each of the video inputs should be AC-coupled to the source. The minimum size of
the coupling capacitor depends on the input resistance of the first circuit block of the
signal channel. This resistance is nominally 15 kΩ
capacitor values, an active impedance boosting circuit can be activated by setting
signal DROOP_COMP_CHx to logical 1 in the AFE Control 3 register (0x106). This
increases the resistance value to the 70 kΩ–200 kΩ range. It is not recommended that
impedance boosting be used without analog clamping, because the boosting circuit
may add an offset to the signal, and this offset voltage can be as high as 200 mV. The
offset can be eliminated with clamping. For most video applications, the
DROOP_COMP_CHx bit should be enabled to use the recommended 1 µF AC­coupling value. Impedance boosting should not be used in sound IF inputs.

. To allow smaller coupling

3.3.2 Clamping

Since the video inputs are AC coupled, the sync and back-porch levels of the signal at
the channel input varies with the overall average picture level. This requires extra­voltage head room, which reduces the maximum achievable signal-to-noise ratio, both
in the ADC and the analog signal processing blocks before it. Therefore, the analog
subsystem provides a clamping feature to force the sync voltage to a predefined level.

The clamping circuit is by default enabled, but can be disabled by setting the
CLAMP_EN_CHx bit in the AFE Control 2 and 3 (0x105 and 0x106) registers to 0.
When the clamp is enabled, it pulls the input voltage toward the desired level. A clamp
strobe from the digital logic is activated during the sync pulse and remains clamped
for a minimum of 1 µs per line. Since the channel gain is variable, the clamping level
seen at the ADC output depends on the gain settings. To provide a suitable clamping
level across different gain settings, the clamping level can be set with signal
CLAMP_LEVEL_CHx[2:0] according to Ta ble 3 -9 .

Table 3-9. Clamping Levels

CLAMP_LEVEL_CHx

000 –1.05 V –160 (out of ADC range)

001 –0.80 V 0

010 –0.606 V 124

Clamp Voltage (relative to

mid-level)

Clamp Code (when gain is

set to 0 dB)

011 –0.460 V 218

100 –0.348 V 289

101 –0.264 V 343

110 –0.2 V 384

111 0 V 512

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3.3.3 Negative Reference Input

The signal inputs are single-ended, but to reduce the effect of board-level noise, the
negative input terminal of the first gain stage can be taken out of the chip and
grounded on the PCB. This external board connection must be AC coupled.

3.3.4 Variable Gain Amplifiers

The variable gain is realized in two stages. The first stage has a gain range from
–12 dB to +6 dB in 6 dB steps, and the second stage covers the 6-dB range between
the first stage steps by providing 16 linear steps. In addition, the digital control can
enable an extra 12 dB of gain by setting the signal EN_12DB_CHx to 1 in the AFE
Control (0x104) register. Normally, the video decoder automatically chooses the
correct gain value, depending on the amplitude of the input signal. However, if manual
control over the gain is desired, the value can be programmed through the
VGA_GAIN bits in the VGA Gain Control (0x488) register. It is also necessary to
disable the automatic function of the VGA by setting the VGA_AUTO_EN bit in the
Digital Front-End (DFE) Control (0x48B) register to 0. The possible gain settings are
shown in Tab le 3 -1 0.

Table 3-10. Gain Settings (1 of 3)

Gain[5:4] Gain[3:0] Gain

000.25

0 1 0.265625

0 2 0.28125

0 3 0.296875

0 4 0.3125

0 5 0.328125

0 6 0.34375

0 7 0.359375

0 8 0.375

0 9 0.390625

0 10 0.40625

0 11 0.421875

0 12 0.4375

0 13 0.453125

0 14 0.46875

0 15 0.484375

100.5

1 1 0.53125

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Table 3-10. Gain Settings (2 of 3)

Gain[5:4] Gain[3:0] Gain

1 2 0.5625

1 3 0.59375

1 4 0.625

1 5 0.65625

1 6 0.6875

1 7 0.71875

180.75

1 9 0.78125

1 10 0.8125

1 11 0.84375

1120.875

1 13 0.90625

1 14 0.9375

1 15 0.96875

201

2 1 1.0625

2 2 1.125

2 3 1.1875

241.25

2 5 1.3125

2 6 1.375

2 7 1.4375

281.5

2 9 1.5625

2101.625

2 11 1.6875

2121.75

2 13 1.8125

2141.875

2 15 1.9375

302

3 1 2.125

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Table 3-10. Gain Settings (3 of 3)

Gain[5:4] Gain[3:0] Gain

322.25

3 3 2.375

342.5

3 5 2.625

362.75

3 7 2.875

383

3 9 3.125

3103.25

3113.375

3123.5

Anti-alias Filtering

3.3.5 Anti-Alias Filtering

Anti-aliasing filtering is integrated within the analog input channels of the device.
The anti-alias filter is designed to reject frequencies within 6 MHz of the sampling
frequency to prevent these frequencies from producing aliases in the pass band. The
cutoff frequency is set to 8 MHz to provide the flattest possible response for PAL, and
the stop band is defined as 22.0 MHz and above where the signal is attenuated at least
25 dB. Although not shown, the time-domain impulse response avoids ringing so that
sharp luma transitions do not create ringing in the filter output. Furthermore, the
delay through this filter differs by no more than 6 ns across the range from 3.0 MHz to

5.0 MHz.

The filter is automatically tuned to the correct –3 dB frequency by using the ADC
clock as a reference. Nominally, this is about 1/3 times the ADC clock frequency. To
allow sampling at half-rate, the filter bandwidth can be halved by setting
HALF_BW_CHx to 1 in the AFE Control 1 register (0x104). Alternatively, the filter
can be completely bypassed by setting BYPASS_CHx to 1 in the AFE Control 3
(0x106) register.

3133.625

3143.75

3153.875

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Detailed Functional Description CX25840/1/2/3 Data Sheet

Table 3 -1 1 provides a summary of the anti-alias filter characteristics. Figure 3-3

illustrates a transfer function of the realized filter.

Table 3-11. Anti-Alias Filter Characteristics Summary

Parameter Requirement

Cutoff Frequency (3 dB) 8.0 MHz

Differential Delay, 3.0 MHz to 5.0 MHz 6 ns

Ripple below 3 MHz +

Figure 3-3. A Transfer Function of the Realized Filter

5

0

–5

–10

–15

Gain

–20

–25

–30

–35

0.1 dB

–40

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6

7

10

Frequency

10

8

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3.3.6 Channel Performance

The RMS noise voltage in the ADC input depends on the f ilter bandwidth, gain
setting, and temperature. The worst-case noise voltages (not including the ADC noise)
for different bandwidth settings are shown in Table 3 -1 2.

Table 3-12. Analog Channel Performance

EN_12DB_CHx Filtering RMS Noise Voltage RMS Noise (dBFS)

0Normal750 µV –57.5

0 Half bandwidth 700 µV –58

0 Bypass 1.0 mV –55

1 Normal 2.7 mV –46.5

1 Half bandwidth 1.9 mV –49

1 Bypass 3.9 mV –43

The total harmonic distortion in the ADC input is always smaller than –65 dBFS.

3.3.7 Analog to Digital Converter

Specifications for the ADC are listed in Ta ble 3 -1 3.

Table 3-13. ADC Specifications

Parameter Symbol Minimum Typ

Sample Frequency Fs 27.0 29.5 MHz

Differential Input Voltage
Range

Input Bandwidth Fb 12 MHz

Output Word Width R 11 bits

Integral Linearity INL +

Differential Linearity DNL +

SINAD 55 dB

Input Capacitance Ci TBD pF

The second ADC (Miscellaneous Chip Control) can be configured to sample either
CH{2} or CH{3} at nominal clock rate, or it can be put in dual mode, in which
samples are alternated between CH{2} and CH{3}. Channel selection is controlled by
signal CH_SEL_ADC2: 0=CH{2}, 1=CH{3}, and dual mode is enabled by setting
DUAL_MODE_ADC2 to 1. These control bits are found in the Miscellaneous Chip
Control Configuration (0x102) register.

The ADC is fed a buffered version of the crystal frequency, where it then generates a
clock that is 5 times the crystal clock. This clock is generated using a DLL-based
clock multiplier.

Maximu

m

Vin 1.6 V p-p

1.0 LSB

0.7 LSB

Units

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3.4 Digital Video Processing

The CX25840/1/2/3 integrate all mixed-signal integrated circuit functions required for
decoding broadcast video television standards. They decode all common broadcast
analog video formats—(all NTSC, PAL, and SECAM variations) in addition to the
nonbroadcast NTSC-4.43 and PAL-60 formats.

The devices decode standard-definition baseband video, formatted as either a
composite video baseband signal (CVBS), S-Video (Y/C) format, or as component
(YPbPr) format.

For composite video inputs, excellent luma/chroma separation is achieved through the
use of an adaptive 5-line comb filter.

All video formats are decoded to either a 10-bit or 8-bit ITU-R BT.656 digital video
stream with embedded sync bytes, VIP 2 scalable digital video stream, or as SPI­coded video stream with separate sync pins.

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Figure 3-4 illustrates the video decoding functions and data flow.

Figure 3-4. Video Decoder Functional Block Diagram

Audio Samples

VBI FIFO I/F

VBI

Slicer

Luma AdjustBack Porch

Low Pass Filter

(Scaling Dependent)

Luma Datapath

Back Porch Removal

Adjust

Discrete Timing

Control (SPI)

Brightness

Contrast

Peaking

White Crush

Luma

Output Formatter

Vertical Scaling

Horizontal Scaling

Chroma Datapath

SECAM Bell Filter

656/VIP

Output

Saturation

Chroma Killer/AGC

SECAM

Demodulator

U/V

NTSC/PAL
Hue Adjust

U/V

Sync, Field

Strobes

Clocks

Resets

.

Test Bus

.

Muxing

.
.

Macrovision

Detect

and

Frame

Store

Interface

PLL Freq.

Control

Default

PLL Freq.

Luma/Composite

Chroma Remod

Luma Comb Filter

Y/C Separation

Line Store

Sample Rate Convert, Horizontal Timing Loop

Digital Front End (AGC, DC-Restore)

From

Luma ADC

Clamp Control

Chroma Comb Filter

Chroma Demod/SC Gen

Chroma/UV

VGA Gain,

From

Chroma ADC

Misc. Control

Misc. Status

VBI FIFO I/F

vsync

Global Timing Control

Video

Registers

Timing
Regs

Video

Timing

Generator

APB+

IRQ

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3.4.1 Video Signal Format

The input waveform to the video decoder can be in either composite (CVBS), S-Video
(Y/C), or component (YPbPr) format. For any of the composite video inputs, only
ADC1 and ACD2 can be used to sample the video waveform. If desired, the analog
front-end of channel 2 can be powered down in situations that do not require S-Video
or component video decoding. When an S-Video signal is applied, ADC1 samples the
luma signal, and ADC2 samples the chroma signal. When a component waveform
signal is applied, the Pb and Pr values are interleaved on ADC2.

The selection of the type of video format to decode is made by programming the
appropriate value to the INPUT_MODE bits of the Video Mode Control 2 register
(0x401). Once INPUT_MODE is programmed, the video format registers in

Table 3 -1 2 are auto programmed. These registers can be manually programmed as

well. In cases where S-Video or component formats are to be decoded, the VGA for
the chroma channels must be programmed to clamp at the mid-code of the input
waveform. This is programmed through the CLAMP_SEL_CHx bits in the AFE
Control 2 register (0x105). Additionally, for decoding component signals, the second
ADC must be programmed for dual sampling mode. The DUAL_MODE_ADC2 bit
of the Miscellaneous Chip Control Configuration register (0x102) should be set high
to enable multiplexed sampling for the Pb and Pr inputs.

For reducing the integrated anti-alias filter bandwidth on chroma channels, the
HALF_BW_CH{1}/2/3 bits are provided. Setting this bit high halves the input
bandwidth for that particular channel and prevents the occurrence of any anti-aliasing
artifacts. This bit should be set when the channels are used for the chroma waveforms
in component video format.Tab le 3 -1 4 lists the video format register settings.

Table 3-14. Video Format Register Settings

Video

Format

Composite 00 0 0 0 0 0

S-Video0101100

Component1101111

For power savings measures, the analog front-end associated with chroma inputs can
be powered down when decoding only composite input signals. Control over powering
down the second ADC and its associated VGAs can be found in the Power Control 1
register (0x130).

INPUT_M

ODE

CLAMP_S

EL_CH{1}

CLAMP_S

EL_CH{2}

CLAMP_S

EL_CH{3}

DUAL_MO

DE_ADC2

HALF_BW

_CH{2}/3

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3.4.2 AFE and Video Auto-Config

AFE and Video Auto-Config are enabled by default, but can be overridden in the
Miscellaneous Chip Control register (0x102) by setting bit 4 to a 1.

3.4.2.1 AFE Control Auto-Config

Several control ports to the AFE from the digital core must be adjusted based on the
input mode, that is, the content received into the dual ADCs.

To provide some background, the chip contains the two ADCs, but three pre-ADC
channels. The pre-ADC channels contain conditioning circuits, Variable-Gain
Amplifiers (VGAs), and anti-alias filters. ADC1 is fed by one channel, Channel 1,
and Miscellaneous Chip Control is fed by two channels (Channel 2 and Channel 3).
Either Channel 2 or Channel 3 can be selected to drive Miscellaneous Chip Control
statically, but the AFE also supports a dual mode in which the Miscellaneous Chip
Control alternates between samples from Channel 2 and Channel 3 on each sample
clock. This supports component video mode, where it is acceptable to digitize the Pb/
Pr input streams at half the normal bandwidth. It also supports a mode which allows
us to support S-Video and audio IF simultaneously, by digitizing the chroma stream
and the audio stream at half of the normal bandwidth.

Table 3 -1 5 shows the supported input formats. Naturally, the chip supports mapping

of any given input stream to either ADC1 or Miscellaneous Chip Control, but when
auto-config mode is enabled, default assumptions are made according to Table 3 -1 5.
To reverse the input streams between ADC1 and Miscellaneous Chip Control
channels, the auto-config bit should be disabled.

Table 3-15. AFE Input Modes

Video Mode Control 2 (0x401)

INPUT_MODE (Bits 2:1)

00 Composite Video/Audio CVBS Audio

01 Y/C, S-Video Luma Chroma

10 Y/C/A, S-Video with half-rate chroma and half-rate audio Y Chroma/Audio

11 Y/Pb/Pr, Component Video Y Pb/Pr

Each input mode requires that several AFE control ports be adjusted, either to achieve
the required functionality, or to optimize performance. The register f ields that control
these ports are not register bits that the user generally needs to adjust. Therefore, the
auto-config feature is designed to allow the user to just specify the input mode,
without having to develop software that knows how to fine-tune the AFE controls.
The register logic will automatically adjust the register fields upon writing the
INPUT_MODE field in the Video Mode Control 2 register (0x0401). The auto-config
will happen immediately upon writing the INPUT_MODE field. If desired by the
customer, software may overwrite any fields that were set by the auto-config logic by
directly writing to that field. However, the auto-config logic will again modify the
register fields if software again writes the INPUT_MODE field. To disable the auto­config features altogether, write the CHIP_ACFG_DIS (Miscellaneous Chip Control
Configuration register, 0x102) bit.

Mode Description ADC1

Miscellaneous

Chip Control

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Table 3 -1 6 shows how the register field in the Miscellaneous Chip Control

Configuration and AFE Control (N) registers will be configured based on the
INPUT_MODE field of the Video Mode Control 2 register (0x0401).

Table 3-16. AFE Control Auto-Config

Field Name Register Bits

INPUT_MODE 0x401 2:1 00 01 10 11

DUAL_MODE_ADC2 0x102 2 0 0 1 1

DROOP_COMP_CH3 0x106 4 0 0 0 1

DROOP_COMP_CH2 0x106 3 0 0 1 1

CLAMP_EN_CH3 0x106 1 0 0 0 1

CLAMP_EN_CH2 0x106 0 0 0 0 1

VGA_SEL_CH3 0x105 0 1 0 1 0

VGA_SEL_CH1 0x104 6 1 0 0 0

HALF_BW_CH30x10450001

HALF_BW_CH20x10440001

3.4.2.2 Video PLL Auto-Config

Similar to the AFE Control Auto-Config feature, the Video PLL frequency is also
automatically configured based on the video operating mode. The Video PLL must be
programmed to eight times the pixel rate. The pixel rate in turn depends on whether
the chip is in square pixel mode, and if so, whether it is currently decoding a 525-line
format or a 625-line format.

CVBS

(Default)

Y/C Y/C/A Y/Pb/Pr

Table 3-17. Pixel Frequency Modes

Mode Pixel Frequency (MHz) 8x Video PLL Frequency (MHz) Sq_pixel bit Lines-per-frame

BT.656 13.5000 108.0000 0 Don’t-care

525-line square pixel 12.2727 98.1818 1 525

625-line square pixel 14.7500 118.0000 1 625

When auto-config is enabled, the video PLL frequency will be automatically
configured based on whether the chip is in square pixel mode, and if so, whether the
decoder is decoding a 525-line or 625-line format. The auto-config logic will
immediately re-program the video PLL frequency controls whenever either of the
following events happens:

1. The SQ_PIXEL bit 4 in Video Mode Control 1 (address = 0x400) is written;

2. The video format changes, whether due to a register write to the VID_FMT_SEL

field bits 3:0 of Video Mode Control 1, or due to a format change while in auto­detection mode.

If desired by the customer, software may overwrite any fields that were set by the
auto-config logic by directly writing to that field. However, the auto-config logic will
again modify the register fields if one of the auto-config events listed above happens.
To disable the auto-config feature altogether, write the CHIP_ACFG_DIS

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(Miscellaneous Chip Control Configuration, 0x102) bit. This is the same bit described
above, that disables the AFE Control Auto-Config.

Table 3 -1 8 shows how the registers are configured based on the pixel frequency mode.

Table 3-18. Video PLL Auto-Config

Field Name Register Bit(s)

VID_PLL_POST

VID_PLL_INT

VID_PLL_FRAC1

VID_PLL_FRAC2

VID_PLL_FRAC3

VID_PLL_FRAC4

0x109 5:0 0x04 0x04 0x04

0x108 5:0 0x0F 0x0D 0x10

0x10C 7:0 0xFE 0xE6 0xB7

0x10D 7:0 0xE2 0xB6 0x0F

0x10E 7:0 0x2B 0x6D 0xF7

0x10F 0 0x0 0x1 0x0

BT.656 timing

(Default)

3.4.3 Video Standard Auto-Detection

The CX25840/1/2/3 automatically detect and configure themselves to decode a
variety of video standards found throughout the world. The auto-format detection
logic uses information about the subcarrier frequency, number of video lines, and
whether or not the video is alternating phase in order to determine the input standard.
For cases where two standards are differentiated by the presence or absence of a
pedestal (or setup), two user-programmable register bits, AFD_PAL_SEL and
AFD_NTSC_SEL, are required to differentiate the standards. Table 3-19 illustrates
how this information is used to automatically determine the video standard.

Table 3-19. Auto Format Detection Parameters

525-line Square Pixel 625-line Square Pixel

NTSC-M NTSC-J

Video Lines

Subcarrier

Frequency

AFD_PAL SEL

AFD_NTSC_SEL

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525 525 625 625 525 625 625 525 525

3.58 3.58 4.43 4.43 3.58 3.58 4.25/

N/A N/A 0 1 N/A N/A N/A N/A N/A

0 1 N/A N/A N/A N/A N/A N/A N/A

Video standards supported include NTSC-M, NTSC-J, NTSC-4.43, PAL-BDGHI,
PAL-M, PAL-N, PAL-N combination, PAL-60, and SECAM. After a device reset, the
video decoder comes up in auto-detect mode and automatically configures the
Vertical Blanking, Vertical Active, Horizontal Blanking, Horizontal Active, Burst
Gate Delay, Band-pass Filter, Comb Error Limit, SRC Decimation Ratio, Subcarrier
Step Size, and VBI Offset registers based upon the active input and whether the
SQ_PIXEL bit is set in the VIDEO MODE CONTROL 1 register (0x400).

PAL-

BDGHI

PAL-N PAL-M PAL-NC SECAM PAL-60

4.43 4.43

4.40

NTSC-

443

Detailed Functional Description CX25840/1/2/3 Data Sheet

Refer to Table s 5 -4 and 5-5, which show the register values when auto-detect mode is
selected for BT.656 decoding and square-pixel rate decoding.

Two video standards, NTSC-J and PAL-N, require additional configuration to discern
between NTSC-M and PAL-BDGHI, respectively. For properly decoded black levels
with NTSC-J and PAL-N, the AFD_NTSC_SEL or AFD_PAL_SEL bit in the VIDEO
MODE CONTROL 1 register (0x400) must be set high to indicate to the decoder that
no pedestal is present on the input waveform.

The auto detection can also be manually overridden by programming the
VID_FMT_SEL bits in the VIDEO MODE CONTROL 1 register (0x400) to the
desired video standard to be decoded. Writing these VID_FMT_SEL bits to a forced
standard still enables automatic configuration of the registers to their respective
values but disables the function to automatically switch should a different video
standard be input. To completely disable the automatic register conf iguration, the
ACFG_DIS bit in Video Mode Control 1 (0x400) register should be set high.

3.4.4 Signal Level Adjust in the Digital Front End

When a video signal is first applied, the Digital Front End (DFE) block receives 8x
NTSC subcarrier, oversampled waveforms from the ADCs that have unknown
amplitude and offsets. The block then applies offset and gain to the input such that the
output of the DFE is aligned with expected levels for black and white. The DFE
controls the amplitude of the signal into the ADCs by implementing an AGC
algorithm to gain the signal based on the reference sync-tip amplitude. This AGC
algorithm coarsely controls the signal amplitude by adjusting the VGA gain in
discrete steps. Next, fine adjustment of the amplitude is accomplished by applying a
digital multiplier to the incoming signal.

Since some video equipment provides a less-than-standard sync tip, the decoder must
also adapt the gain accordingly. If the input signal contains white levels that exceed
the expected normal level, the luma processing block detects the occurrence of these
excursions past the normal peak white and updates the sync-tip height reference.

The DFE is also responsible for aligning the back porch to a standard level. It
measures the average level of the back porch level in the incoming signal, and then
adds an offset to the ADC data after it has passed through the gain stage.

For S-Video and component formats, the chroma and Pb/Pr ADC data must have their
own gain and offset applied. For these cases, the DFE uses the same gain value that
was determined from the luma channel for the chroma and Pb/Pr channels. However,
for the offset, different assumptions apply. In the case of S-Video, it assumes that the
chroma signal is balanced around the ADC’s mid-code value of 0x200. Any DC offset
from this ideal value should not matter once the AC waveform is passed through the
chroma demodulation stage. In the case of YPbPr video format, the offset is such that
the chroma value during the sync tip is clamped to the mid-code value of 0x200
(which is logically equivalent to U/V = 0).

The DFE is also partly responsible for determining when the input waveform is
clamped. The AFE attempts to clamp the sync tip to a level such that after passing
through the VGA stage, it is roughly the correct level. This requires the DFE to
provide both the clamping strobe during the sync pulse and a clamping level to the
AFE. The clamping level is provided through mapping based on the VGA setting.
These functions also serve to maximize the dynamic range of the ADC.

Alternatively, the automatic function of the VGA and AGC can be disabled by setting
the auto enable bits, VGA_AUTO_EN and AGC_AUTO_EN, in the DFE CONTROL
register (0x48B) low and manually setting the gain values through the VGA Gain

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Control register (0x488) and AGC Gain Control registers (0x489 and 0x48A). The
auto clamping function can be disabled as well through the CLAMP_AUTO_EN bit in
the DFE Control register (0x48B). Manual control of the VGA, AGC, and clamp can
be useful for specialized applications such as security cameras, but is not
recommended for applications where the sources, formats, and standards of the video
equipment providing the signal can vary from one use to another.

3.4.5 Sample Rate Conversion

After the levels of the ADC samples are adjusted, the sample points must be adjusted
in time. The Sample Rate Conversion (SRC) blocks convert the signal from the ADC
crystal clock domain to the pixel clock rate. Three pixel clock rates are supported. as
shown in Tab le 3 -2 0.

Table 3-20. Pixel Sample Rates

Pixel Rate Usage

13.5 MHz ITU-R BT.656 Pixel Frequency

14.75 MHz PAL and SECAM 625-line Square Pixel Frequency

12.272715 MHz NTSC 525-line Square Pixel Frequency

This conversion is more involved than a static sample rate conversion. The sample
points must be adjusted so the SRC provides not only the same number of pixels per
line (for example, 858 in 13.5 MHz mode), but sample points placed such that the first
sample is aligned with the leading horizontal sync edge.

VCRs often have timing glitches during the vertical blanking interval caused by head
switches, and camera sources can have inter-field and intra-field drift in their line
timing due to the manner in which their video timing is derived. The SRC is designed
to maintain pixel alignment with these types of nonstandard timing sources by quickly
locking to these line-to-line timing variations and smoothing out these variations so
that a consistent amount of pixels is output from the decoder.

3.4.6 Source Locked Pixel Clock Generation

The sample rate conversion stage also controls the pixel clock generated by the video
PLL. This PLL should be programmed to generate a clock that is 8 times the pixel
rate. The internal video decoder logic is clocked with either this 8x clock, or a
divided-down 2x version of the same clock.

An important aspect of the SRC and video PLL is that these two blocks work together
to provide an internal clock that is locked to the video source. The BT.656 output
format requires a fixed number of clocks per field, which is the driving requirement
for a pixel clock that is locked to the video source. Not only must there be a constant
number of clocks per field, but the PLL-generated clock must be stable. This is
required to support MPEG video codec devices connected to the pixel output
interface. Similarly, analog video encoders that derive their time base from the pixel
clock that we provide can result in inaccurate hue if there is substantial clock drift over
the short term.

The video PLL clock directly controls the post-SRC pipeline of the video decoder all
the way to the output pixel interface. The frequency creates an exact data rate

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requirement from the SRC, although the data rate out of the polyphase decimation
filter rate is generated independently of the PLL pixel clock. The polyphase filter
output rate and the PLL frequency are nevertheless locked, because both the SRC
filter and the PLL are both locked to a constant number of pixels per line. The
difference is that the SRC has a locking time constant of a few lines, while the PLL
has a locking time constant of hundreds to thousands of lines. This means that the
PLL- and SRC-effective sample rates can deviate from each other over the short term.

To accommodate these short-term clock rate deviations, a synchronization FIFO large
enough to hold a line’s worth of pixels is implemented. The nominal FIFO level is
half-full. The FIFO level can rise above the midpoint as the SRC quickly outputs more
sample points to keep up with short lines. The FIFO level can fall below midpoint as
the SRC slows down to accommodate longer lines, but the rate at which samples are
read from the FIFO is relatively constant.V

3.4.7 Vertical Sync Detection

The sample rate converter has one more task. It detects transitions in the data that
indicate vertical sync pulses (VSYNC). The timing generator circuitry uses the
VSYNC pulse to synchronize its vertical counters, and determine what field is
currently being decoded.roma

3.4.8 Luma and Chroma Separation

After the data passes through the DFE level adjust and sample rate converter stages,
the next step is to separate the luma from the chroma for composite signal sources
(see Figure 3-5). For S-Video and component signal source, the chroma is already
separated out, and these ADC samples simply bypass the separation stage and go to
the chroma demodulator.

Figure 3-5. YC Separation Block Diagram

YC_IN

2H Line

Store

4H Line

Store

CUV_IN

x8PCLK

svideo-

mode

Chroma

BPF/Notch

Chroma

Demod

Comb

Filter

Chroma

Remod

+

–

Y_OUT

C_OUT

102284_005

A digital PLL is used to track the color subcarrier frequency, F
decoded. It is the responsibility of the subcarrier tracking loop logic to exactly match
the phase frequency of the subcarrier in order to properly decode the color

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as each line is

sc,

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CX25840/1/2/3 Data Sheet Detailed Functional Description

information. The 2ωt components of the U and V are then removed by a low-pass
filter, resulting in baseband chroma components.

The Y/C separation block implements a 5-line adaptive comb filter, with adaptive
fallback to a chroma notch filter. The comb filter implements two algorithms, one for
NTSC and one for PAL. The two algorithms are required because the NTSC color
carrier has a 180-degree phase shift between adjacent lines, while the PAL color
carrier has only a 90-degree phase shift. However, the comb filter takes advantage of
these phase shifts in the color subcarrier from line to line to recover luminance data
from the bandwidth occupied by the chrominance data.

The CX25840/1/2/3 separates luminance and chrominance components of the
composite video signal with a flexible combination of a luma comb, chroma comb
and notch filter. A total of five lines are used in the chroma comb filter algorithm.
Four lines are stored in on-chip memory, and the fifth line is the currently decoded
line. The adaptation algorithms take advantage of the two additional lines to provide
pixels that are in phase with the current pixel in NTSC mode, or to provide additional
comb filter options in PAL mode. The luma comb uses only three lines, but which
three depends on whether the signal is NTSC or PAL.

The chroma comb filter uses addition and subtraction to determine the lines with the
highest degree of correlation with the current pixel and extract the chrominance from
these pixels. Since any sample consists of both luma and chroma components, the
difference between two pixels could be due to either luminance or chrominance
difference, and there is not enough information to tell them apart. In other words,
since on any adjacent line, the chroma is out of phase with the current line, subtracting
the two pixels is not the difference between the pixels, but rather chroma plus the
difference. For NTSC systems, the addition of another pair of lines above the usual
three gives access to two lines that are in phase with the current line, making a true
comparison possible. In PAL systems, the additional lines are 180 degrees out of
phase with the current line, making it similar to NTSC with three lines. However,
using a combination of all five lines, a comparison between the current line and the
outer lines is possible. So the comb filter finds the combination of lines in which this
difference is the smallest. If all the differences are above the programmed
CCOMB_ERR_LIMIT threshold in the Chroma Comb Error Limit Max (0x49E)
register, the chroma is passed through unaltered and the luminance is notch filtered.

The luma comb uses only the lines which have chroma 180 degrees out of phase, but it
first low pass filters the signal to remove the chroma, then compares the remaining
luma components. In addition, the chroma comb feeds the difference it has computed
to the luma comb. If both errors are acceptably low (below LCOMB_ERR_LIMIT)
the luma comb averages the pixels over the entire signal bandwidth. This greatly
reduces cross luma in color transitions and high-frequency chroma sources such as
DVD players.

In SECAM mode, or when the adaptation algorithm determines that an unacceptable
error would be created by the comb filter algorithm, it simply notch-filters the color
subcarrier out of the luma. Since SECAM uses an FM modulated signal, a carrier is
always present, regardless of whether or not there is color information being
broadcast. This results in a visible artifact in the luminance at the carrier frequency. To
minimize this effect, an “inverse bell” filter is applied at the encoder to attenuate color
frequencies near the Dr and Db carriers. Thus, if little or no color information is
present in the signal, the carriers will be reduced in amplitude. In order to properly
decode the color information, a “bell” filter is applied to the chroma data when in
SECAM mode.

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Detailed Functional Description CX25840/1/2/3 Data Sheet

3.4.9 Luma Processing

The luma data path logic processes the luma waveform that comes from the Y/C
separation module to produce SPI luma samples. These decoded luma samples are
then sent through logic blocks that can perform post-processing functions such as
white crush, peaking for sharpness control, contrast, and brightness adjustment before
they are passed along to the scaling block.

White Crush

The “white crush” term refers to Conexant’s algorithm for adapting to luma overflow
in the presence of nonstandard sync-tip-to-white ratios. The luma samples are first
passed through the white crush circuitry, which works with the front-end to
automatically fine-tune the video levels. This circuitry adjusts the overall gain of the
input signal such that excursions above nominal 100 or 110 IRE peak white-level are
compensated for to reduce video-blooming artifacts. The white crush processing is by
default enabled but can be disabled by writing a 0 to the WCEN bit of Mode Control
register 2 (0x401). The 110 IRE threshold can be enabled by setting the WTW_EN bit
high in the White Crush Control 3 register (0x4A2).

Following white crush, the back porch of the luma waveform is removed, and for some
video formats, the setup (or pedestal) value is removed as well. The luma samples are
then multiplied by scale factors to match SPI def ined luma levels. Setup removal is
determined by the video standard.

Luma Low-Pass Filtering

Next, the luma is optionally low-pass filtered to remove any high frequency content
that could cause alias artifacts associated with horizontal scaling. The filter has four
different transfer functions based upon the desired horizontal scaling factor. The
appropriate transfer characteristic is automatically selected by deriving from the value
that is programmed in the Horizontal Scaling registers (0x418 to 0x41A). One of
these four transfer functions is nothing more than a filter bypass. This is automatically
chosen when no scaling is enabled.

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Figure 3-6 shows the luma filter responses for the other three transfer characteristics

when scaling is performed.

Figure 3-6. Luma Filter Responses

Luma Low-Pass Response @ NTSC Square Pixel Rate (12.27 MHz)

0

–10

–20

–30

Magnitude (dB)

–40

01 23

Frequency (Hz)

Luma Low-Pass Filter Response @ 656 Pixel Rate (13.5 MHz)

0

–10

–20

Magnitude (dB)

–30

–40

0123

Frequency (Hz)

CIF
QCIF
ICON

456

x 10

CIF
QCIF
ICON

456

6

x 10

6

Luma Low-Pass Filter Response @ PAL Square Pixel Rate (14.75 MHz)

0

–10

–20

Magnitude (dB)

–30

–40

01 2 3

Frequency (Hz)

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4567

CIF
QCIF
ICON

x 10

6

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Detailed Functional Description CX25840/1/2/3 Data Sheet

Luma Peaking

Following the low-pass filter is another filter, the peaking or sharpness filter. The
peaking filter can be used to improve the high frequency response of the luma near its
corner frequency. As with the luma low-pass filter, this filter has multiple response
functions. There is a bypass mode and four modes with non-0 gains, increasing from
+2.0 dB to +6.0 dB. The larger the programmed gain of the filter, the greater the luma
high frequency adjustment. The filter is enabled through the PEAK_EN bit in the
Luma Control register (0x416). The gain of the filter is selected through the
PEAK_SEL bits, which selects between the four positive gain values, +2.0 dB,
+3.5 dB, +5.0 dB, and +6.0 dB. Figure 3-7 shows the peaking filter characteristics for
the various pixel rates.

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CX25840/1/2/3 Data Sheet Detailed Functional Description

Figure 3-7. Peaking Filter Responses

Peaking Filter Response @ NTSC Square Pixel Rate (12.27 MHz)

6

5

4

3

2

Magnitude (dB)

1

0

1 1.5 2 2.5 3 3.5 4 4.5

Frequency (Hz)

Peaking Filter Response @ 656 Pixel Rate (13.5 MHz)

6

5

4

3

2

Magnitude (dB)

1

0

1234

Frequency (Hz)

56

5 5.5 6

x 10

x 10

6

6

Peaking Filter Response @ PAL Square Pixel Rate (14.75 MHz)

6

5

4

3

2

Magnitude (dB)

1

0

1234

Frequency (Hz)

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567

6

x 10

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Detailed Functional Description CX25840/1/2/3 Data Sheet

Contrast

Contrast adjustment follows the peaking filter. This block multiplies the luma samples
by the contrast value that is programmed into the Contrast register (0x415). The
multiplication value is represented by a 2s complement number, thus values above
0x80 increase the contrast, and values below 0x80 decrease the contrast. This is
followed by color-space conversion, which converts the luma from YUV color space
to YCrCb color space. The function involves multiplying the incoming luma data by
the color-space conversion factor. The incoming video standard and the desired output
range of luma codes determine the multiplication factor. The RANGE bits of the
Luma Control register (0x416) determine the number of 10-bit codes, out of 1024,
that are allowed for the nominal luma range. This does not mean that the luma is
limited to this range. It just means that this range is used in the color space conversion
process.

Brightness

Following the contrast and color-space conversion multiplication operations, the
brightness adjustment is performed, which is an addition of the luma samples with 8
times the value found in the BRIGHTNESS register (0x414). This register value is
represented by a 2s complement number, allowing the overall video level to be
adjusted down by as much as 1024, or up by as much as 1016 on a 10-bit scale. This
results in a luma signal that has been offset by an amount equal to the brightness
value.

The next step is the coring operation, which serves to remove low-level noise by
zeroing-out any values whose magnitude is below a user-selected threshold. This
threshold is selected through the LUMA_CORE_SEL bits in the Luma Control
register (0x416). This coring threshold can range from 0, which would have no effect,
to 64, which would zero-out the 7 LSBs of the luma output.

The final process of the luma data path is the range saturation. The range adjustment
enables the user to select one of three allowed luma output ranges. The first range is
compliant to the SPI specification that allows for a nominal 64–940 range with
excursion up to 1016 but not below 16-black level. The second range is similar in that
it allows for a nominal 64–940 with excursions up to 1016 but in addition it allows for
excursions below 16. This is to support blacker-than-black values which are possible
on systems with a pedestal. The final range places no restrictions on the data in that it
allows all value from 0 to 1023 to pass. Table 3 -2 1 illustrates the output range of the
luma data for the various RANGE bits in the Luma Control register (0x416).

Table 3-21. Luma Output Ranges

Nominal Range

After Color-

RANGE[5:4]

00 64–940 16–235 64–1016 Nominal range with excursions allowed but

01 64–940 1–235 4–1016 Nominal range with excursions and blacker

1x 0–1023 0–255 0–1023 0–1023 nominal with no limiting

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Space

Conversion

(decimal)

Allowed 8-bit
Output Range

(decimal)

Allowed 10-bit

Output Range

(decimal)

Description

no blacker than black levels

than black allowed

8/3/05

CX25840/1/2/3 Data Sheet Detailed Functional Description

3.4.10 Chroma Processing

The Chroma Data Processing (CDP) block receives chrominance U/V data from the
Y/C Separation (YCS) block. Although the SECAM demodulator is located in the
CDP, the demodulator for NTSC and PAL is located in the YCS because of the comb
filtering in these formats. The U/V input is also used to support component video
(YUV) formats. The component format U/V data is merged into the U/V data path in
the YCS block.

Figure 3-8 illustrates the major components of the CDP. When in SECAM mode, the

CDP must demodulate the SECAM chroma to obtain the Db/Dr baseband
components. Otherwise, hue adjustment is done for the NTSC and PAL formats. The
CDP performs AGC on the signals, for NTSC and PAL formats, based on the value of
the U component during the color burst. Adjustments are made for saturation, color
space conversion for the Cb/Cr space, and finally chroma coring. The chroma data
path also contains a programmable delay of +
relative to the luma data path.

Figure 3-8. Chroma Processing

2 pixels to allow alignment adjustments

UV_IN

Figure 3-9. SECAM Chroma Demod

NTSC/PAL
Hue Adjust

SECAM

Demodulator

Some amount of SECAM preprocessing is performed in the YCS block. The SECAM
complex down converter or frequency mixer and the Bell filter function is performed
in the YCS block. The CDP processing for SECAM is shown in Figure 3-9.

Demod

FM

Offset

Adjust

Chroma

AGC

Deemphasis

Chroma

Adjust

CBCR_OUT

102284_049

DRDB_OUTUV_IN

102284_050

The first step is to perform FM demodulation. FM demodulation is implemented with
a CORDIC rotator followed by a differentiator filter. Next, an adjustment is made to
the output of the FM demod to account for the frequency offset introduced by using
the fixed frequency mixer. A fixed de-emphasis filter is then applied according to the
SECAM standard.

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Hue can be adjusted for NTSC video standards through the Hue register (0x422). The
register value represents a signed 8-bit value that is used to rotate the subcarrier phase
in increments of 0.35 degrees with a range of –45 degrees to +45 degrees.

Chroma AGC

The chroma AGC logic is used to correct for nonstandard chrominance information in
NTSC and PAL, typically found in VCRs, by multiplying the chrominance
information by a computed gain value. The chroma AGC logic is a feedback loop that
continually adjusts the gain applied to the chrominance data to produce the standard
level for the given television format. Each horizontal line, the value of the U data
during the color burst is compared to the standard value, and the difference
accumulated over four samples. If the error is greater than or equal to –8, or less than
or equal to 7 for 32 consecutive lines, the chroma AGC enters an idle state. Once in
this idle state, the chroma AGC does not make any gain corrections until the
accumulated error is greater than or equal to 32, or less than or equal to –32 for 32
consecutive lines. At this point, corrections are made until the idle state is entered
once again. This gain update only occurs once per line. The chroma AGC is enabled
by default but can be disabled by setting the CAGCEN bit of the Video Mode Control
2 register (0x401) to 0. The chroma AGC is also disabled automatically if the video
input format is component, YPrPb, or if the video standard is SECAM.

Chroma Kill

The chroma kill function disables the chroma demodulation function if the color burst
is detected to be below a certain threshold. This allows for the case in which either no
color exists or a greatly attenuated color subcarrier exists on the video input. This
prevents the chroma AGC loop from falsely detecting noise as chroma and amplifying
it.

The NTSC and PAL chroma killer is accomplished by logic that detects a low color
burst value for 127 consecutive lines. The chroma killer state machine monitors
chroma samples that are accumulated during the color burst. If the accumulated
chroma samples have a magnitude smaller than 7 percent of the nominal NTSC burst
amplitude, or 10 percent of the nominal PAL burst amplitude, the color kill function is
asserted. If the accumulated chroma sample value has a greater magnitude than
14 percent of nominal NTSC burst amplitude, or 19 percent of nominal PAL burst
amplitude for 127 consecutive lines, the color killer function is automatically
disabled. The SECAM chroma killer is accomplished by using the subcarrier
frequency detect information from the DFE. If no subcarrier exists for 127
consecutive lines, the chroma killer logic is activated. To permanently disable the
color killer function, the CKILLEN bit in the Video Mode Control 2 register (0x401)
should be set low.

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Saturation

Saturation can be adjusted through the Saturation-U (0x420) and Saturation-V
(0x421) registers. These register values are doubled internally and then multiplied
with the U and V data. The result is then rounded and clamped to a 10-bit value. To
maintain proper U and V saturation ratios, these registers should be written in tandem
with the same value. Tab le 3 -22 illustrates the range of saturation adjustment
available.

Table 3-22. Chroma Saturation Range

Decimal Value Hex Value Percent of Original Signal

255 0xFF 199.22

254 0xFE 198.44

.
.
.

129 0x81 100.78

128 0x80 100.00

127 0x7F 99.22

.
.
.

10x01 0.78

00x00 0.00

Chroma Coring

Chroma

values whose magnitude is below a user-selected threshold. This threshold is selected
through the C_CORE_SEL bits in the Chroma Control register (0x423). This coring
threshold can range from 0, which would have no effect, to ±31, which would zero out the
6 LSBs of the chroma output. Ta ble 3- 23 shows the range of possible chroma coring
values.

coring can be enabled to remove low-level chroma noise by zeroing out any

Table 3-23. Chroma Coring Range

.
.
.

.
.
.

.
.
.

.
.
.

C_CORE_SEL[1:0] Coring Range

00 No coring

01 –7 <= x <= +7

10 –15 <= x <= +15

11 –31 <= x <= +31

Lastly, the chroma data can be delayed by ± 2 pixels relative to the luma data. The
CHR_DELAY bits of Chroma Control register (0x423) specify the delay. The values
can be thought of as signed 3-bit numbers that represent the pixel delay. Positive
values mean the chroma data will be delayed more than the 0 value. Negative values
mean the chroma data will be delayed less than the 0 value.

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3.4.11 Copy Protection Detect

The copy protection logic detects the presence of the pseudo-sync pulses and color
striping in the video waveform according to the Macrovision copy protection
detection specification. If more than a minimum specified number of pseudo-sync
pulses (PSP) in a field are detected, the MV_PSP status bit is set in the Copy
Protection Status register (0x40C). If Macrovision color striping is detected for more
than a specified minimum number of lines, the logic sets a status bit indicating that
color striping has been detected and additional status bits indicating what type of color
striping is detected, type 2 or type 3. The MV_CS bit indicates the presence of color
striping, the MV_T3CS bit indicates the presence of type 3 color striping, and
MV_TYPE2_PAIR indicates a type 2 pair detected. These status bits can be found in
the Copy Protection Status register (0x40C).

Additionally, the pseudo-sync pulse and color striping status indicators are encoded to
form a 2-bit Macrovision Copy Control status as described in the Macrovision
detection specification. This code is represented by the MV_CDAT bits in the Copy
Protection Status register (0x40C). The host processor can be automatically informed
of changes in the presence of copy protection on the source material through the
interrupt pin. A MV_CHANGE_STAT interrupt status with mask is available in the
Interrupt Status 2 and Interrupt Mask 2 registers (0x411 and 0x413), respectively. If
the MV_CHANGE_STAT mask is 0, any change to the status bit is reflected on the
interrupt pin. This alleviates the host processor from having to continually poll the
status register to see if copy protection is present on the incoming video waveform.

3.4.12 Timing Generator

The timing generator provides all the timing control strobes for video decoder paths
that follow the sample rate converter block. It outputs both horizontal and vertical
timing control, including blanking and burst gate control. The SRC module provides
vertical sync (VSYNC) and horizontal sync (HSYNC) reference pulses to
synchronize the timing generator.

In auto-detect mode, the timing generator is also responsible for controlling the
format search. Based on the lines-per-frame count, the subcarrier frequency, and the
presence of phase alternation, the mode is selected. When video lock is lost and re­acquired, the default assumption is that the video broadcast standard remains
unchanged. It is only when differences in the key format metrics are detected that the
format selection is changed.

Upon selecting a mode, the timing generator automatically sets all of the timing
parameters required for the selected video broadcast standard. There is also a manual
mode where the timing parameters are produced directly from the programmable
register set.

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3.4.13 Fast Channel Switching

Fast channel switching is when you grab a field (or frame) from an input and then
switch to another input and try to grab the first correct field available, and then switch
again to another input, and so on.

To determine if the decoder can grab a field after a channel switch, the decoder must
lock on the signal. To lock on the new input signal, it is necessary to have Horizontal
Lock, Vertical Lock, and Color lock on the video input.

The CX25840/1/2/3 uses optimized hardware to reduce the time needed to switch
between different signal sources. This new technology now achieves much higher
frame rates when switching inputs continuously.

This is achieved through the following:

 Fast Horizontal Lock
 Fast Vertical Lock
 Fast Col or Lock
 Fast adjustment of gain for input signal

Fast Horizontal Lock (HLOCK) is a feature that is already optimized in the decoder.
There are no registers to enable. The General Status 2 (0x40E) register has an
HLOCK bit that notifies the application that horizontal lock has been achieved. Even
under line length variations fast horizontal locking is achieved.

Fast Vertical Lock (VLOCK) can be achieved by setting FAST_LOCK_MD bit of the
Video Mode Control 3 (0x402) register to high to enable the fast locking algorithm.
The fast locking algorithm locks onto the first vertical sync it encounters, regardless
of where the internal timing counters expect a vertical sync to occur. It also disables
the hysteresis that is used for the field detection logic. As soon as the even/odd field is
detected, the field signal is updated to reflect that status. Vertical lock can be
determined by reading the VLOCK and VPRES status bits in the General Status 2
(0x40E) register.

To achieve Fast Color Lock (CSC_LOCK), the chroma subcarrier lock speed must be
set to fast mode. To do this, the auto mode of the subcarrier lock must first be disabled
by setting the AUTO_SC_LOCK bit low and then setting the subcarrier lock speed to
“fast” by setting the MAN_SC_FAST_LOCK bits in the Video Mode Control 2
(0x401) and Interrupt Status 1 (0x410) registers, respectively. Status of subcarrier
lock can be determined by reading the CSC_LOCK and
CSC_LOCK_CHANGE_STAT bits in the General Status 2 (0x40E) and Interrupt
Status 1 (0x410) registers, respectively.

To achieve a fast adjustment of gain for the input signal (AGC_LOCK), enable the
AGC_AUTO_EN and VGA_AUTO_EN functions in the Digital Front-End Control
(0x48B) register. By doing so, the decoder has the ability to automatically acquire
gain value for all eight composite inputs. This is particularly useful because the AGC
presents a problem for doing fast channel switching. Since all sources require
different gain values when we switch from one video input to another, it takes time for
the gain to adjust. The adjustment time can prevent how fast the application can
switch between inputs. After enabling the AGC_AUTO_EN and VGA_AUTO_EN
functions, the application would then enable each input, read the AGC_GAIN and
VGA_GAIN values for that source, and save the values for later use. Next, the
application would set AGC_AUTO_EN and VGA_AUTO_EN bits to manual mode,
and write the saved AGC value that is associated with a particular input to the
AGC_GAIN and VGA_GAIN fields. This technique of restoring predetermined gain
values eliminates the amount of time needed to adjust the AGC for the new video
input. The General Status 2 (0x40E) register has an AGC_LOCK bit that notifies the
application that the correct gain has been selected.

Finally, auto format detection should be disabled for fast channel switching. This is
accomplished by setting the VID_FMT_SEL bits in the Video Mode Control 1
register (0x400) to the appropriate video standard to be decoded.

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3.4.14 Temporal Decimation

Temporal decimation provides a solution for video synchronization during periods
when full frame rate cannot be supported due to bandwidth and system restrictions.

The device provides temporal decimation on either a field or frame basis. The
temporal decimation register (TDEC) is loaded with a value from 1 to 60 (NTSC) or 1
to 50 (PAL/SECAM). This value represents the number of fields or frames skipped by
the chip during a sequence of 60 for NTSC, or 50 for PAL/SECAM. Skipped fields
and frames are considered inactive, indicated by the ACTIVE pin remaining low.
Consequently, if QCLK is programmed to depend on ACTIVE, QCLK becomes
inactive as well.

Examples:

 TDEC = 0x02 Decimation is performed by frames. Two frames are skipped per 60

frames of video, assuming NTSC decoding.

 Frames 1–29 are output normally, then ACTIVE remains low for one frame.

Frames 30–59 are then output, followed by another frame of inactive video.

 TDEC = 0x9E Decimation is performed by fields. Thirty fields are output per 60

fields of video, assuming NTSC decoding.

 This value outputs every other field, or every odd field of video, starting with

field one in frame one.

 TDEC = 0x01 Decimation is performed by frames. One frame is skipped per 50

frames of video, assuming PAL/SECAM decoding.

 TDEC = 0x00 Decimation is not performed. Full frame rate video is output by the

device.

When changing programming in the temporal decimation register, 0x00 should be
loaded first, and then the decimation value. This ensures the decimation counter is
reset to zero. If zero is not first loaded, the decimation may start on any field or frame
in the sequence of 60 (or 50 for PAL/SECAM). On power-up, this preload is not
necessary because the counter is internally reset. When decimating fields, the
FLDALN bit in the TDEC register can be programmed to choose whether the
decimation starts with an odd field or an even field. If the FLDALN bit is set to
logical 0, the first field dropped during the decimation process will be an odd field.
Conversely, setting the FLDALN bit to logical 1 causes the even field to be dropped
first in the decimation process.

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3.5 Scaling and Cropping

The scaling engine consists of both horizontal and vertical scalers. The purpose of the
scaling engine is to scale down the image by a programmable factor. This is useful
when viewing video on a PC desktop and when saving video to disk. The scaling
engine supports arbitrary and independent downscaling only with vertical and
horizontal scaling factors that are controlled through separate registers to allow
different scaling values—anamorphic scaling.

The horizontal scaler supports the following requirements:

 Supports scaling from 1 to 15.999755859375 in 1/4096 steps.
 Supports 63 phases between source samples. The filter rejects aliases by 60 dB.

The vertical scaler supports the following requirements:

 Supports scaling from 1 to 7.998046875 in 1/512 steps.
 Supports 7 phases between horizontal lines.

3.5.1 Horizontal Scaling

The horizontal scaling function is shown in Figure 3-10. The primary purpose of this
block is to scale down horizontally or reduce the number of pixels in each line.
Horizontal scaling is implemented through multitap, polyphase interpolation. Six taps
of luma and four taps of chroma, each with 64 different phases, are used to accurately
interpolate the value of a scaled pixel. In simple pixel- and line-dropping algorithms,
noninteger scaling ratios introduce a step function in the video signal that effectively
introduces high-frequency spectral components. Polyphase interpolation accurately
interpolates to the correct pixel and line position, providing more accurate
information. This results in more aesthetically pleasing video and higher compression
ratios in bandwidth-limited applications. In addition, the chroma path has a YCrCb
4:4:4 to 4:2:2 conversion block. It is important to note that prior to horizontal scaling
the luma data path pre-f ilters the data to prevent aliasing artifacts

Figure 3-10. Horizontal Scaling Block Diagram

LUMA_YDP[9:0]

HSCALE[23:0]

HACTIVE

CBCR_HSC[9:0]

CBFLAG

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Phase

Generation

Luma

Coefficient

Generation

Chroma

Coefficient

Generation

Luma

Interpolation

Filter

Chroma

Interpolation

Filter

YCbCr

4:4:4 to

4:2:2

Conversion

LUMA_HSC[9:0]

HSC_HACTIVE

CBCR_HSC[9:0]

HSC_SKIP

HSC_OBFLAG

102284_011

Detailed Functional Description CX25840/1/2/3 Data Sheet

The amount of horizontal scaling performed is based on two factors, the number of
active pixels in a line entering the scaler along with the desired number of pixels
leaving the scaler. The ratio of these two values determines the scaling ratio to be used
in the following HSCALE formula:

Horizontal Scale Value (HSCALE) = (Scaling Ratio–1) x 2

For example, to achieve horizontal scaling of a BT.656 full-resolution (720 active
pixels) image down to a half-resolution (360 active pixel) image, the scaling ratio
would simply be 2, Scaling Ratio = 720/360. Using this value in the horizontal scaling
equation yields a value of HSCALE = 2
would be 4, Scaling Ratio = 720/180. Thus, the HSCALE register (0x418 to 0x41A)
value must be set to 3 x 2
horizontal scale factor.

For square pixel scaling, the same calculation is involved, except in this case, full
resolution has 640 active pixels for NTSC and 768 active pixels for PAL and SECAM.
The scaling ratios and the HSCALE values are the same as in the BT.656 calculations
(see Table 3 -2 4).

Table 3-24. Common Scaling Resolutions: HSCALE and VSCALE Values

Resolution HSCALE (0x418 to 0x41A) Value VSCALE (0x41C to 0x41D) Value

Full-resolution Square Pixel 1:1 0x000000 0x0000

20

, 0x300000. Always round up when calculating a

20

(0x100000). For 4:1 scaling the scale factor

20

CIF 2:1 0x100000 0x1E00

QCIF 4:1 0x300000 0x1A00

Icon 8:1 0x700000 0x1200

Note that there is no dependence on the horizontal blanking delay (HBLANK) value
that is programmed, as there have been in some previous generation video decoders.

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3.5.2 Vertical Scaling

The vertical scaling function is shown in Figure 3-11. The primary purpose of this
block is to scale down vertically by reducing the number of lines. In addition, special
functions are performed during SECAM mode for Dr/Db line-store and during PAL
mode for line averaging.

Figure 3-11. Vertical Scaling Block Diagram

VSCALE[12:0]

VTG_HRESET_N

VS_INTRLACE

VTG_FIELD

VBLANK0

VTG_AFD[3:2]

VFILT[2:0]

HSC_SKIP

LUMA_HSC[9:0]

CBCR_HSC9:0]

HSC_CBFLAG

CDP_DBLINE

VTG_VRESET_N

VTG_VACTIVE

HSC_HACTIVE

VSKIP

Phase

Generator

Line Store

and

SECAM

Dr/Db Line

Store

PHASE[2:0]

PA L

SECAM

CL_LUMA[9:0]

PL_LUMA9:0]

CL_CHROMA[9:0]

PL_CHROMA[9:0]

Chroma

Coefficient

Generator

Luma

Coefficient

Generator

CCLC[7:0]

CPLC[7:0]

YCLC[7:0]

YPLC[7:0]

Luma/Chroma

Interpolation

Filter and
PAL Line

Averaging

LUMA_VSC[9:0]

CBCR_VSC[9:0]

VSC_VALID

VSC_FIELD

VSC_CBFLAG

VSC_HRESET

VSC_VRESET

VSC_HACTIVE

VSC_VACTIVE

102284_012

Valid video data does not start until line 21 for NTSC and line 33 for PAL/SECAM. In
autoconfiguration mode, the default value for the vertical blanking delay, VBLANK
(0x474 an 0x475) is set to 22 and 34, respectively, for each video standard. This
register value, VBLANK, represents the number of half lines between the trailing
edge of a vertical reset (after the first nine lines, which contain equalization and
serration pulses) and the start of active video, while the VACTIVE (0x475 and 0x476)
registers represents the number of half lines in the vertical active region that enter the
vertical scaler.

As in the horizontal scaler, the two factors that determine the scaling process are the
number of active lines going into the vertical scaler and the number of desired lines
out of the scaler. The ratio of these two values determines the scaling ratio to be used
in the VSCALE formula below:

Vertical Scale Value (VSCALE) = (2

16

– (Scaling Ratio–1) x 29) & 0x1FFF

NOTE:

Only the 13 LSBs are used (& = logical AND).

Thus, the vertical scaling ratio is determined by VACTIVE, the number of half lines
coming into the scaler and desired number of half lines output from the scaler. For
example, to achieve vertical scaling of an NTSC BT.656 full-resolution (487 active
half lines) image down to a half-resolution (244 active pixel) image, the scaling ratio
would simply be 2, Scaling Ratio = 487/244. Using this value in the vertical scaling
equation yields a value of VSCALE = 2

16

– 29 (0x1E00). For 4:1 vertical scaling, the

scale factor would be 4, Scaling Ratio = 487/122. Thus, the VSCALE register (0x41C

16

and 0x41D) value must be set to 2

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– 3 x 29, 0x1A00.

Detailed Functional Description CX25840/1/2/3 Data Sheet

For square pixel scaling, the same calculation is involved, except in this case, full­resolution has 480 active lines for NTSC and 576 active lines for PAL and SECAM.
The scaling ratios and the VSCALE values are the same as in the BT.656 calculations
(see Table 3 -2 4).

There are two modes to the vertical scaler: interlaced and noninterlaced vertical
scaling. In interlaced mode, the two fields are treated as part of a whole image to be
displayed. Since the lines are interlaced, the scaling coefficients are set to reflect this
by resetting the coefficients to 0 and VSCALE/2 to generate that offset. In
noninterlaced mode, each field is treated independently and the scaling coefficients
are always reset to 0. Control of these modes is accomplished through the
VS_INTRLACE bit in the Vertical Scaling Control (0x41E) register.

3.5.3 Interpolation Filter and PAL Line Averaging

A multitap, polyphase filter is provided for vertical scaling of both luma and chroma
data. The number of vertical taps is programmed by the user through the VFILT bits in
the Vertical Scaling Control (0x41E) register. Care should be taken when selecting the
number of taps for the vertical filter. The user may select 2, 3, 4, or 5 taps. The
number of taps must be chosen in conjunction with the horizontal scale factor to
ensure that the needed data can fit in the internal line-store memory.

The line-store contains enough memory for 768 active pixels per line. When
horizontally scaling, not all of the line-store memory needs to be used. This left-over
memory can be used to store up to three additional lines of data, for a total of five
lines worth. The amount of excess memory is determined by the horizontal scaling
ratio. When there is no horizontal scaling, the line-store can hold one line, and provide
for 2-tap filtering. When a horizontal ratio of 2:1 or greater is used, the line-store can
hold two lines, allowing 3-tap filtering. When a horizontal ratio of 3:1 or greater is
used, the line-store can hold three lines, allowing a 4-tap filtering.

Finally, when a horizontal ratio of 4:1 or greater is used, the line-store can hold four
lines, allowing 5-tap filtering. Figure 3-12 illustrates this selection. Ta ble 3 -2 5 defines
the vertical scaler tap selection.

Figure 3-12. Interpolation Filter Tap Selection Diagram

HSC_SKIP

CLC

CL[9:0]

IFMult

PL[9:0]

PLC

VFILT[1:0]

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PCLK_EN PCLK_EN PCLK_EN

EEE

2'b11
2'b10
2'b01

IF[9:0]

2'b00

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Table 3-25. Vertical Scaler Tap Selection

Resolution VFILT[2:0] Bits Description

Full Resolution and Below 000 2-Tap Interpolation

½ Resolution (less than 384 active pixels per line) or below 001 3-Tap Interpolation

¼ Resolution (less than 193 active pixels per line) or below 010 4-Tap Interpolation

1/8 Resolution 011 5-Tap Interpolation

Two other functions take advantage of the line-store memory. There is line averaging
in PAL mode and Dr/Db line-storage in SECAM mode. In SECAM mode, Dr/Db
values are passed through the chroma channel on alternating lines, thus a line-store is
necessary so that Cr/Cb pairs can be obtained from combining the demodulated Dr/
Db values.

In PAL mode, line averaging is done to enhance the color accuracy by averaging the
chroma values of adjacent lines. The PAL line averaging and vertical scaling are done
in the same filter. The coefficient generator for the chroma module has an input that
indicates PAL operation and sets the coefficients to the 50 percent point. Line
averaging can be disabled for sharper vertical transitions by setting the
LINE_AVG_DIS bit in the Vertical Line Control register (0x41F).

3.5.4 Chrominance Interpolation Filter and Resampling

A 4-tap, 64-phase chroma interpolation filter is applied to YCbCr 4:4:4 chroma data.
The output of the filter is offset by 512 (for 10-bit chroma data) and passed to the
chroma resampling block. The chroma input to the scaler block is in 4:4:4 YCbCr
format and is downsampled to 4:2:2 YCbCr after the data has been scaled. The
resampling at half the rate can be done without a downsample filter because Cr and
Cb signals are typically limited to approximately 1.3 MHz.

3.5.5 Image Cropping

Cropping enables the user to output any subsection of the video image. The
HACTIVE and VACTIVE values can be programmed to start and stop at any position
on the video frame, as illustrated in Figure 3-13. The start of the active area in the
vertical direction is referenced to vertical reset, (the beginning of a new field). In the
horizontal direction, it is referenced to horizontal reset (the beginning of a new line).
The dimensions of the active video region are defined by HBLANK, HACTIVE,
VBLANK, and VACTIVE. The vertical and horizontal blanking delay values
determine the position of the cropped image within a frame, while the horizontal and
vertical active values set the pixel dimensions of the cropped image.

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Figure 3-13. Effect of the Cropping and Active Registers

Video frame

VDELAY

VACTIVE

Rising Edge of VRESET

Video frame

VDELAY

Cropped image

HACTIVEHDELAY

VACTIVE

HACTIVEHDELAY

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Cropped image

scaled to

1/2 size

Falling Edge of HRESET

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CX25840/1/2/3 Data Sheet Detailed Functional Description

3.5.6 Horizontal Cropping

To horizontally crop an image, the values of HBLANK (0x470 and 0x471) and
HACTIVE (0x471 and 0x472) are adjusted. To maintain proper image location, the
cropped values of HBLANK and HACTIVE should sum to less than or equal to the
value of HBLANK + HACTIVE without cropping. To crop the left side of an image,
increase HBLANK by the number of pixels desired. To crop the right side of the
image, decrease HACTIVE by the number of pixels desired.

3.5.7 Vertical Cropping

To vertically crop an image, the values of VBLANK (0x474 and 0x475) and
VACTIVE (0x475 and 0x476) are adjusted. To maintain proper image location, the
cropped value of VACTIVE plus (VDELAY) should be less than or equal to the value
without cropping.

The units of VBLANK and VACTIVE are half lines. To crop the top of the image,
increase VBLANK by the number of desired lines multiplied by two. To crop the
bottom of the image, decrease VACTIVE by the number of desired lines multiplied by
two.

3.5.8 Scaling and Cropping Effects on SPI

The decoder has the following external timing signals available, which are affected by
scaling and cropping as described below:

 Vertical Sync: Not affected by scaling or cropping
 Horizontal Sync: Occurs at the beginning of each line and is not affected by

horizontal scaling

 Vertical Active: This signal is used to determine when the analog active video is

valid. When vertical scaling occurs, this signal goes to its inactive state for the
lines that should not be stored into the video memory. When image cropping is
taking place, the length of Vertical Active is adjusted to provide fewer lines per
field.

 Horizontal Active: This signal is used to determine when the analog active video is

valid. Since horizontal video is always scaled, Horizontal Active contains more
clocks than the pixels programmed into the Horizontal Active register. This signal
is affected by the value programmed into the scaling register. When image
cropping is taking place, the length of Horizontal Active is adjusted to provide
fewer valid pixels per line.

 Valid Pixel Indicator: To determine which clocks are valid for storage into a video

buffer, the Valid Pixel signal is high for valid pixels and low for invalid pixels. The
Valid Pixel Indicator toggles throughout the entire line time to include blanking
and synchronizing intervals even with cropping. This signal is affected by the
value programmed into the scaling register.

 Odd/Even Field Indicator: Not affected by scaling or cropping
 Cb/Cr Indicator: Informs the user whether the pixel is Cb or Cr. When invalid

pixels are encountered, the Cr, Cb order is therefore maintained from valid pixel to
valid pixel, as flagged by this signal pin. This signal is affected by the value
programmed into the scaling register.

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3.6 VBI Data Slicer

3.6.1 VBI Data Slicer Overview

The output of the SRC stage bypasses the Y/C separation block and passes data to the
VBI slicer block. Once in the VBI slicer, the ADC data can be VBI sliced or output
directly to the video output formatter in a raw mode.

From the SRC, the ADC samples are passed to the VBI block at the pixel rate, where
the data is upsampled to 2x the pixel rate. Here, the data is oversampled at a 4x rate
and then filtered with a –5.54 MHz to 5.54 MHz bandpass filter to reduce
quantization noise. Filtered data is then passed through the data bit slicer—which
detects VBI data according to the format for each standard. Finally, the data goes to a
FIFO for output on the 656 interface or can be read from the VBI data registers.

Note that the parameters described in this section can be manually controlled through
custom modes, but they are configured automatically in the autoconfiguration modes.

3.6.2 VBI Standards Supported

The VBI block is capable of slicing the world’s VBI data standards. All sliced data can
be inserted into the BT.656 or VIP video streams as an ancillary data stream. The
BT.1364 specification discusses the specific formatting of ancillary data. The
following VBI standards are available as ancillary data in BT.656 and VIP modes:

 Closed Caption/Extended Data Services (EIA-608)
 Wide Screen Signaling (625 line: ITU-R BT.1119, 525 line: EIAJ CPR-1204)

including the Copy Generation Management System (CGMS)

 Gemstar1x
 Gemstar2x

The following VBI standards are available as ancillary data on BT.656 mode only:

 World System Teletext (ITU-R BT.653)
 North American Basic Teletext Spec. (NABTS EIA-516)
 Video Programming System using Enhanced Teletext Standard (VPS ETS-300-

231)

 VITC/SMPTE (ITU-R BT.1366)
 Moji (ARIB STD-B5)

Where applicable, both 625-line and 525-line versions are supported.

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3.6.3 VBI Waveform Description

A detailed description of the incoming waveform will help to better understand the
VBI function blocks. The model that is being used for the VBI block implementation
is based on four basic input data formats: Closed Caption (CC), Wide Screen
Signaling (WSS), Teletext (TTX), and VITC. All other signaling standards should fit
into the format of these signals.

Figure 3-14 depicts a Closed Caption waveform. The main purpose of this figure is to

illustrate the various signaling formats and how the various sections of the signal play
a part into the VBI engine. The VBI engine starts when one of the following three
events occurs: a vertical reset, time-out of data run-in, or the end of the previous line’s
data capture mode.

There are exceptions to the typical VBI waveform shown in Figure 3-14. For example,
VBI standards such as WSS525, VITC525, and VITC625 do not have clock run-in
periods. Another VBI standard that differs from the example given is the WSS625
VBI standard. It is a biphase modulated signal.

Figure 3-14. Typical VBI Waveform

Slice Level

HDELAY

COLOR

BURST

Clock Run-in Data CaptureStar t/Frame

Code

S

T
A
R

T

D0-D6 D0-D6

P
A
R

I
T
Y

P
A
R

I
T
Y

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3.6.4 VBI Data Output

Low bit-rate VBI standards can be read back from the memory-mapped registers that
are accessible by either the two-wire serial communication or VIP host port. The VBI
data registers, which contain data for both even and odd fields, are updated every
frame during the vertical blanking interval after capturing and decoding the data. The
data standards available through the memory-mapped registers are the following:

 Closed Caption/Extended Data Services (EIA-608)
 Wide Screen Signaling (625 line: ITU-R BT.1119, 525 line: EIAJ CPR-1204)

including the Copy Generation Management System (CGMS)

 Gemstar1x
 Gemstar2x

There are four payload data FIFOs for Closed Caption, Gemstar 1x, Gemstar 2x, and
WSS standards. The CC and Gemstar 1x FIFOs are 10 bytes deep, the Gemstar 2x are
20 bytes deep, and the WSS FIFO are 6 bytes deep. By reading the Closed Caption
Data (0x445), Gemstar 1x Data (0x447), Gemstar 2x Data (0x449) and WSS Data
(0x44B) registers, the user can access the FIFOs for each of these standards.

After the data is read, the data FIFO pointer is automatically incremented to the next
byte of information. With each data byte loaded to a register for reading, a status byte
is updated accordingly. The status byte indicates whether a parity error has occurred
for CC, Gemstar 1x, Gemstar 2x. It also indicates if the byte was captured from the
odd or even field (CC or XDS), and the byte number. Two bits indicating FIFO
overflow or empty are also included in the status byte.

Both high bit-rate and low bit-rate sliced data can be inserted in the video output
stream during horizontal blanking intervals (areas labeled A in Figure 3-15) as
ancillary data. The VBI slicer uses a FIFO and related control signals to pass the data
to the video output formatter for insertion. Ancillary data insertion is enabled by
setting high the ANC_DATA_EN bit in the Video Out Control 1 (0x404) register.

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Figure 3-15. Blanking Regions

(1) (1)

H = 1

FF 00 00 XY FF 00 00 XY

(2) (3)

EAV SAVAB

(6)(6)(6)(6)

V = 1V = 0V = 1V = 0

(3)

A Field 0

H = 0

(4)

(5)

FOOTNOTES:

(1) H = Horizontal
(2) EAV = End of active video
(3) A = Ancillary data
(4) SAV = Start of active video
(5) B = Blanking
(6) V = Vertical

(3)

AB

(3)

A Field 1

(5)

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3.6.5 Preprogrammed VBI Standards

The VBI slicer block can operate in a predefined/autoconfiguration mode or in a user
defined custom mode. The VBI slicer provides access to 34 VBI lines in one frame of
video; 17 lines are provided per odd and even field. The VBI decoder block can be
assigned a VBI standard to be sliced on a line-by-line basis. Each VBI line can be
individually programmed to use either the predefined autoconfiguration VBI settings
or the user programmable custom settings.

There are eight preprogrammed settings of VBI decoding for 525-line mode and
six preprogrammed settings for the 625-line mode. Each line, in either odd or even
field, can be decoded for each of the modes listed in by programming the VBI Line
Control 1 to VBI Line Control 17 (0x424 to 0x434) registers. The VBI block can
decode any combination of the available 34 lines of VBI information and output the
information to the memory mapped data registers or through the BT.656/VIP data
stream. Due to the higher bit-rates of Teletext, this data is only available as ancillary
data within the BT.656/VIP stream.

There are a total of five configuration registers consisting of 17 total lines; each
fieldname in the configuration register is defined as an odd and even line. The
decoding of each line is defined by an 8-bit register value programmed by the user
through the VBI Line Control [1:17] registers. Available preprogrammed VBI slice
standards are listed in Table 3-26.

Table 3-26. Available Preprogrammed VBI Slice Standards

525 Line Modes

VBI Line Control Value

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

No VBI Data Slicing

WST525-B

WST525-C (NABTS)

WST525-D (Moji)

WSS525

VITC525

CC525

Gemstar 1x

Gemstar 2x

RESERVED

Custom VBI 1

Custom VBI 2

Custom VBI 3

625 Line Modes

VBI Line Control Value

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

No VBI Data Slicing

WST625-B

WST625-A

RESERVED

WSS625

VITC625

CC625

RESERVED

RESERVED

VPS

Custom VBI 1

Custom VBI 2

Custom VBI 3

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For each control register, the fieldname is defined as an 8-bit value with the most
significant nibble of the fieldname used to indicate the odd field and the least
significant nibble used define the even field. To program the VBI engine to decode a
specific standard or a particular line, both the odd and the even registers of the
fieldname must be programmed to decode that set standard.

For example, upon reset, VBI_LINE_CONTROL4 (0x427) register is set to a default
value of 0x00b or “No VBI data slicing” on line 4 for odd or even field. However, if
the user wished to decode line 4 from the odd video field with WST525 and the even
video field of line 4 with Gemstar 1x, then VBI_LINE_CONTROL4 would need to be
programmed as 0x47. For a complete list of options, refer to the description of the
various VBI registers in Section 5 of this document.

3.6.6 Custom Data Transmission of VBI Data

The VBI decoding block also provides the flexibility for the user to define each
parameter through various registers and fieldnames. Once programmed, the decoder
extracts the VBI information from the video stream and outputs the decoded data to
the video output formatter (VOF) block or to the memory-mapped registers. To
initiate custom program mode, the control register, VBI Line Control {1:17}, for a
particular line must be set to Custom VBIx mode.

Three programmable registers are available for customization and are autoconfigured
by default. These registers, VBI Custom{1:3} Horizontal Delay, VBI Custom{1:3}
Time-out, and VBI Custom{1:3} Increment, can be custom-configured individually to
support specif ic user-defined VBI requirements. In the default configuration, the VBI
Custom 1 registers are set to decode Closed Caption 525; VBI Custom 2 registers are
set to decode WSS625; and VBI Custom 3 registers are set to decode WST525,
System C.

Each of these registers can be custom-configured through the two-wire serial
communications port or VIP host interfaces. Refer to Section 5 for the Custom{1:3}
settings and their fieldnames. Each of these fieldname values is programmable and
allows the user to custom-modify the VBI decode engine. The other two custom
setting registers and fieldnames can be found in the register section.

3.6.7 Miscellaneous VBI Configuration

Additionally, there are miscellaneous configuration registers, VBI Miscellaneous
Config 1, TTX Packet Address {1:3} (0x43C to 0x43F), used to customize Teletext
decoding and reset the VBI FIFOs for Gemstar 1x/2x, WSS, and CC. In the case of
Teletext decoding, the upper and lower limits of the Teletext packet information can
be specified through these registers and fieldnames, as well as the programming of
alternative framing packets. Furthermore, the registers can be programmed to enable
hamming comparison.

Alternatively, the miscellaneous configuration registers can also be used for
modifying the parameters in the predefined or autoconfiguration modes. A different
frame code can be substituted for the autoconfiguration mode with little user effort.
For example, modifying the VBI Alternate Frame Code Type (0x439) register, bits
FC_ALT1_TYPE, with the same code as the VBIMODE, does this.

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3.6.8 VBI Controller

Control of the VBI engine is through a state machine, which monitors the incoming
video and nonvideo data and initiates the VBI decoding process based on user defined
parameters of HDELAY, CRILK, FCBIT, and VBx_BYTE_COUNT. Other inputs to
the VBI state machine are from the Vertical Timing Generator (VTG), which outputs
both the vertical and horizontal reset. See Ta ble 3 -1 4 in Section 3.6.3. The CC
waveform consists of four major sections: hdelay, clock run-in, data run-in, (start/
frame code) and data payload (data capture).

Through the state machine, the VBI engine starts when either one of three conditions
occurs: vertical reset, a time-out of data run-in, or at the end of the previous line’s data
capture mode. When a horizontal reset occurs, the VBI engine goes into BREEZE
state for HDELAY clock cycles. Once HDELAY counter expires, it goes into a Clock
run-in state (CRILK) for the number of programmed clock run-in cycles to be
captured. It then switches to data run-in state (FCBIT). The VBI engine stays in this
state for FCBIT to capture the start bits, or the framing code in case of the Teletext
format. Then it switches to Data Capture mode to capture as many bits or bytes
specified by VBIx_CAP_COUNT. Note that the parameters described here can be
manually controlled through the custom modes, but they are configured automatically
in the autoconfiguration modes.

A discrete time oscillator determines the sample rate and positioning of the sample
points for each of the various VBI standards. A 14-bit counter, incremented by
VBIx_BITINC with each VBI clock, generates a pulse to mark each sample point.
This is used to measure sample periods as the state machine sequences through the
different stages of the VBI waveform.

3.6.9 Clock Run-In Synchronization

During the clock run-in cycles, the logic performs three functions:

1. Measures the Slice Level

2. Synchronizes the slice timing to the clock run-in edges

3. Determines whether the clock run-in cycle has the expected frequency.

The slice level detector determines the “slice level” used to distinguish between a
logical 1 or 0 data sample. At the start of the clock run-in signal, an initial assumption
of 1.75 x the back-porch level is made for the initial slice level. This number is used as
a seed to the slice level calculation engine. Samples are taken at VBIx_SLCNT clocks
apart. Starting with the first zero crossing of the clock run-in, four samples are taken,
and the average of those samples is data and data run-in slice level.

During clock run-in, the logic detects the number of clock run-in cycles specified by
VBIx_CRILK. These clocks are detected in terms of rising edges on the input
waveform. At the end of this search, frequency lock is declared if the elapsed time lies
within the range specified by the VBIx_CKRGH and VBIx_CKRGL registers. These
registers specify time in terms of the VBI sample rate period. The DTO that is
controlled by the VBIx_BITINC parameter is used to count the sample periods. In
other words, the logic determines whether a defined number of clock run-in cycles
(VBIx_CRILK) elapsed in the expected time (VBIx_CKRGH and VBIx_CKRGL).

If frequency lock is determined, the sample period DTO is synchronized one more
time to the last negative edge of the clock run-in cycles. In the absence of frequency
lock, the state machine is reset to idle and waits for the next line.

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3.6.10 VBI Special Cases

There are some exceptions to the typical example of the CC VBI, as follows:

 For WSS525, VITC 525, and VITC625 VBIx_SKIP_DRI should be set to 1. This

implies that only one clock run-in cycle is detected, and the data run-in stage
should be skipped. Instantly, the VBI state machine switches to data capture
mode.

 WSS625 uses biphase modulation, where the VBI engine groups the decoded bits

into a 24-bit words, which are sent to the Output Formatter block. The detected
bits are decoded into a 1 or 0 bit, depending if 111000 or 000111, respectively.

 For Teletext, if Hamming checks are enabled through VBIx_HAM_EN, bits 3

through 0 of the framing code are used to match the odd bits of a byte detected in
transmission order. The packet address range is also checked, and if it is not valid,
the captured data is not stored into the FIFO.

3.6.11 Raw Mode VBI

In raw mode, data samples are sent through the VBI slicer without any processing
directly to the video output formatter. Raw VBI data is passed directly from the SRC
output to the output formatter during the active video region of the VBI lines for
decoding and or processing by an external processor or software. Within the VBI
block, the raw ADC samples are converted to a decoder sample rate of 2x
oversampled VBI samples of 2 bytes each. Raw mode VBI is enabled by setting the
VBIHACTRAW_EN bit high in the Video Out Control 1 (0x404) register. The order
of the raw samples presented on the 8 VID_DATA pins is configurable through the
SWAPRAW bit in the Video Out Control 2 (0x405) register.

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Production Data Sheet

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Detailed Functional Description CX25840/1/2/3 Data Sheet

3.7 Video Output Formatting

The Video Output Formatter (VOF) module is at the end of the data processing
pipeline. It is responsible for formatting the 10-bit luma and 10-bit chroma data into
one of the following video output stream formats:

 Synchronous Pixel Interface (SPI) mode where the video is SPI-coded, 4:2:2

subsampled, and timing information is provided through separate sync signals

 ITU-R BT.656 mode where timing control codes are embedded within the data

stream

 VIP1.1 and VIP2 modes, both a super set of ITU-R BT.656 that supports advanced

features such as square pixel sample rates and scaled video. VIP1.1 and VIP2 are
very similar, with minor differences in control code formatting.

3.7.1 Output Format Options

The OUT_MODE bits in the Video Out Control 1 register (0x404) select which of the
video output formats to enable. Also, the video data in the output stream can be
represented as either 8-bits or 10-bits wide depending on the setting of the MODE10B
bit in the same register. In 8-bit mode, the internal 10-bit video data is rounded to 8
bits and presented on the upper most significant bits of the VID_DATA pins. The
VOF is also responsible for inserting sliced and raw VBI data into the pixel stream
embedded as ancillary data. Figure 3-16 shows the various output formats along with
ancillary data.

Figure 3-16. Output Stream Formats

OUT_MODE[1:0]

1. SPI 00 -

2. 656 01 0

3. 656 01 1

4. VIP 1- 0

5. VIP 1- 1

Horizontal

Active

ANC_DATA-EN

Cb CrYCb CbCrYY

Cb CrYY

Cb CrYY

Cb CrYY

Cb CrYY

In the VBI, this is

Raw Data when

VBIHACTRAW_EN = 1.

YCrY Y Cb CrY Y Cb CrY Y Cb CrY Y Cb CrY Y Cb CrYY

10.0h 80.0h 10.0h 80.0h 10.0h 80.0h

3FF 000 000

EAV

3FF 3FF 3FF DID DCSDID000 000 000 3FFCS 000 000 XY

EAV SAV

3FF 000 000

EAV SAV

3FF 3FF DID DCSDID3FF000 000 000

EAV

80.0h

XY

00.0h 00.0h 00.0h 00.0h 00.0h 00.0h 00.0h 00.0h

RP

RP

10.0h 80.0h 10.0h 80.0h 80.0h10.0h

UDW0 UDW1 UDW2 UDW3 UDW4 UDWn

Ancillary Data

00.0h 00.0h 00.0h 00.0h 00.0h 00.0h 00.0h

UDW0 UDW1 UDW2 UDWnIDID1

IDID0

Ancillary Data SAV

...

...

...

80.0h 10.0h

80.0h 10.0h

00.0h 00.0h

3FF 000 000 XY

SAV

3FF 000 000 RP

3FF 000 000 RP

Cb...

CrYY

Cb CrYY

Cb CrYY

CbCSCrYY

In the VBI, this is

Raw Data when

VBIHACTRAW_EN = 1.

102284_009

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Production Data Sheet

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CX25840/1/2/3 Data Sheet Detailed Functional Description

3.7.2 Synchronous Pixel Interface Mode

In the Synchronous Pixel Interface (SPI) mode, the device outputs all pixels
synchronous with PIXCLK, both horizontal and vertical blanking interval pixels and
active pixels. Unlike the BT.656 or VIP output modes where timing control codes are
embedded in the digital data stream, SPI video timing information is conveyed
through the following external synchronization signals, available on separate output
pins:

 Vertical Sync
 Horizontal Sync
 Ve r t i c a l A c t iv e
 Horizontal Active
 Valid Pixel Indicator
 Odd/Even Field Indicator
 Cb/Cr Indicator

The polarity of each of these signals is independently selectable using the POLAR bit
in the Video Out Control 4 register (0x407).

Figure 3-17 illustrates the relationship of the external timing signals over fields.
Figure 3-18 illustrates the relationship of Horizontal Reset and the active portion of

the line. Figure 3-19 illustrates the operation of the VALID and CBFLAG indicators.

The VOF also provides the pixel clock output, PIXCLK, which can be inverted using
the CLK_INVERT register bit. The pixel clock output can be set to run continuously
or to be gated by either the VALID pixel indicator or by the logical AND of the
VALID pixel indicator with ACTIVE indicator. The clock-gating scheme is selected
using the CLK_GATING bits of the Video Out Control 2 register (0x405). Note that
the ACTIVE indicator in the same register can be set to represent either composite­active-vertical and horizontal-active, or simply horizontal-active. The VALID
indicator can similarly be configured to represent either nonscaled pixels or represent
the logical AND of the VALID indicator and the ACTIVE video indicator. This is
controlled by the VALIDFMT bit in the same Video Out Control 2 register (0x405).

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Detailed Functional Description CX25840/1/2/3 Data Sheet

Figure 3-17. SPI Mode External Field Timing Signals

Beginning of Fields 1, 3, 5, 7

HRESET

(1)

VRESET

FIELD

ACTIVE

2–6 Scan Lines VDELAY/2 Scan Lines

Beginning of Fields 2, 4, 6, 8

HRESET

VRESET

FIELD

ACTIVE

2–6 Scan Lines VDELAY/2 Scan Lines

GENERAL NOTES:

1. ACTIVE pin may be programmed to be composite ACTIVE or horizontal ACTIVE.

2. ACTIVE, HRESET, VRESET, and FIELD are shown here with their default polarity. the polarity is programmable via the
VPOLE register.

3. FIELD translations with the end of horizontal active video defined by HDELAY and HACTIVE.

FOOTNOTE:

(1)

HRESET Precedes VRESET by two clock cycles at the beginning of fields 1, 3, 5, and 7 to facilitate external field generation.

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CX25840/1/2/3 Data Sheet Detailed Functional Description

Figure 3-18. SPI Mode External Line Timing Signals

64 Clock Cycles

HRESET

HDELAY Clock Cycles

ACTIVE

HACTIVE Clock Cycles

102284_052

Figure 3-19. SPI Mode VALID and CBFLAG Indicators

VID_DATA[9:0]

DVALID

ACTIVE

PIXCLK

CBFLAG

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Detailed Functional Description CX25840/1/2/3 Data Sheet

3.7.3 Control Codes

For the BT.656 and VIP modes, Start of Active Video (SAV) and End of Active Video
(EAV) control codes are inserted into the output video stream. The 8-bit SAV/EAV
codes are comprised of four timing reference bits: Task (T), Field ID (F), Vertical
Blanking (V), and Horizontal Blanking (H). The T, F, and V bits only change during
EAV codes. The remaining four bits are Hamming-coded error protection and
correction bits in BT.656 mode or 0x0 in VIP modes. If 10-bit output mode is enabled,
0s are appended as LSBs to the end of the SAV/EAV codes.

The value of the task (T) bit depends on the output mode. In BT.656 mode, the T bit is

1. For VIP 2 mode, the T bit is determined by the TASKBIT_VAL bit in the Video Out
Control register (0x404). In VIP 1.1 mode, the T bit is 0 during the vertical blanking
interval if raw data is being substituted and is 1 otherwise.

The value of the field ID (F) bit toggles in the EAV code after an “end-of-field” signal
from the video timing generator is asserted.

The value of the vertical blanking (V) bit switches to 1 in the EAV code when the end
of vertical active is detected. The time at which the V bit switches to 0 in the EAV
code is dependant on whether the output formatter is in VIP or BT.656 mode. In VIP
mode, the line at which the V bit switches to 0 is determined by the Vertical Blanking
Delay registers (0x474 an 0x475). In BT.656 mode, the line at which the V bit
switches to 0 is determined by the Vertical 656 Blanking Delay register (0x477). The
values programmed into these registers must represent the number of half-lines after a
vertical reset. When the VIP_OPT_AL bit is set high in the Video Out Control 3
register (0x406), this forces the V bit to switch to 0 in the EAV code after the Vertical
656 Blanking Delay time when in VIP output mode.

The value of the horizontal blanking (H) bit is 0 in an SAV and 1 in an EAV.

In BT.656 or VIP modes, the video output formatter can limit the 8 MSBs of luma and
chroma samples to the range 1–254. This is done to ensure the upper eight bits do not
contain 0x00 or 0xFF, which are used in these modes to indicate the presence of
control codes. This is accomplished by setting the VIPCLAMP_EN bit of the Video
Out Control 3 register (0x406) high. Also, when VIPBLANK_EN is set high, the
output formatter will blank (Y=16, Cb and Cr=128) the luma and chroma samples for
the following conditions.

 During the horizontal blanking interval (i.e., between EAV and SAV)
 When V bit is 1 between SAV and EAV (if VBIHACTRAW_EN is not set)

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CX25840/1/2/3 Data Sheet Detailed Functional Description

3.7.4 Ancillary Data Insertion

Sliced vertical blanking data can be inserted into the pixel stream output during the
horizontal blanking interval as ancillary data. The ancillary data will be prepended by
the appropriate control codes for the output format that is enabled, BT.656 or VIP.

Table 3 -2 7 is an example of 10 bytes of ancillary data, along with the control codes

and headers that are used for each of the formats.

Table 3-27. Example 10-Byte Ancillary Data Packet

BT.656 / BT.1364 VIP

AB C DE F

MODE10B 0 (8-bit) 0 (8-bit) 1 (10-bit) 0 (8-bit) 0 (8-bit) 1 (10-bit)

DCMODE 0 1 n/a 0 1 n/a

1. ADF0 0x00 0x00 0x00.0 0x00 0x00 0x00.0

2. ADF1 0xFF 0xFF 0xFF.C 0xFF 0xFF 0xFF.C

3. ADF2 0xFF 0xFF 0xFF.C 0xFF 0xFF 0xFF.C

4. DID 0x55 or 0x91 0x55 or 0x91 0x55.0 or 0x91.0 0x55 or 0x91 0x55 or 0x91 0x55.0 or 0x91.0

5. SDID n,e,00,dt[3:0] n,e,00,dt[3:0] n,e,00,dt[3:0],00

n,e,00,dt[3:0] n,e,00,dt[3:0] n,e,00,dt[3:0],00

6. DC n,e,00 0011 n,e,00 1010 n,e,00 0010 10

7.

8. UDW1 UDW1 UDW1 IDID1 IDID1 IDID1

9.

10.

11. UDW4 UDW4 UDW4 UDW2 UDW2 UDW2

12.

13.

14. UDW7 UDW7 UDW7 UDW5 UDW5 UDW5

15.

16.

17.

18.

19. Checksum — —

20. — — — Fill Byte — Fill Byte

UDW Clamp: 1–254 1–254 1–254.75 Not Required Not Required Not Required

Key:
n: not e
e: even parity of remaining bits
dt: data type of ancillary data (sent from VBI slicer)

UDW0 UDW0 UDW0 IDID0 IDID0 IDID0

UDW2 UDW2 UDW2 UDW0 UDW0 UDW0

UDW3 UDW3 UDW3 UDW1 UDW1 UDW1

UDW5 UDW5 UDW5 UDW3 UDW3 UDW3

UDW6 UDW6 UDW6 UDW4 UDW4 UDW4

UDW8 UDW8 UDW8 UDW6 UDW6 UDW6

UDW9 UDW9 UDW9 UDW7 UDW7 UDW7

Fill Byte CS CS UDW8 UDW8 UDW8

Fill Byte — — UDW9 UDW9 UDW9

n,e,00 0011 n,e,00 1010 n,e,00 0011 00

Checksum CS Checksum

The ancillary data insertion can be enabled by setting high the ANC_DATA_EN bit of
the Video Out Control 1 register (0x404). For the VIP modes, the IDID0 and IDID1
values that are embedded within the stream can be customized by programming the
Ancillary IDID0 and IDID1 registers (0x408 to 0x40A) with the desired value.

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Detailed Functional Description CX25840/1/2/3 Data Sheet

Alternatively, the VBI slicer line count can be used as the IDID0 bytes by setting the
IDID0_SOURCE bit high in the Video Out Control 3 register (0x406). The data count
(DC) byte can be configured to represent either 4-byte blocks of UDWs—with byte
padding to remain DWORD aligned or the actual number of UDWs. This option is
selected through the DCMODE bit of the Video Out Control 3 register (0x406).

In addition to providing sliced VBI data as ancillary packets, raw VBI sample data can
be substituted into the horizontal active region of the vertical blanking interval.

Figure 3-20 shows the ancillary region along with the raw VBI regions.

Figure 3-20. Ancillary Region and Raw VBI Regions

H = 1

FF 00 00 XY FF 00 00 XY

EAV

V = 1V = 1 V = 0V = 0

This raw data is from the luma/composite output of the ADC after it has been sample­rate converted to 13.5 MHz and 2x upsampled by the VBI decoder/slicer. Raw data
substitution is selected by setting the VBIHACTRAW_EN bit high in the Video Out
Control 1 (0x404) register. In the SPI mode, the raw data is substituted when
VACTIVE is 0 and HACTIVE is 1. In BT.656 or VIP modes, the raw data is
substituted between SAV and EAV codes when the V bit is 1.

By default, the even samples are placed where the chroma samples would occur, and
the odd samples are placed where the luma samples would occur. If the SWAPRAW
bit of the Video Out Control 2 (0x405) register is set high, odd raw samples are placed
where chroma samples would occur, and the even raw samples are placed where the
luma samples would occur.

Anc.

Available

A Field 0

Anc.

Available

H = 0

SAV Raw VBI Available

Raw VBI Available

Field 1A

102284_010

3.7.5 Blue Field Generation

The video output formatter also contains a blue field generator. This function replaces
the input luma and chroma samples with a field of blue pixels, Y=35, Cb=212,
Cr=114. The blue field generator can be set to automatically output these pixels’ value
when the video decoder determines that there is no lockable signal on the input. This
is configured by setting high the BLUE_FIELD_EN bit in the Video Out Control 1
(0x404) register. The blue field generation can be forced on by setting the
BLUE_FIELD_ACT bit in the same register, regardless of the state of the input video
waveform.

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CX25840/1/2/3 Data Sheet Detailed Functional Description

3.8 Infrared Remote Controller

3.8.1 Architecture Overview

The Infrared Remote (IR) controller, shown in Figure 3-21, is a generic interface that
can be used to communicate with a wide variety of commercial infrared remote
control units. This interface provides modulation and demodulation logic, a set of
programmable pulse timers, and a set of FIFOs. Enough hardware support is provided
to off-load the microprocessor from performing individual bit modulation and
demodulation and data transmission and reception. However, individual infrared
protocols are not decoded or encoded by the hardware, such as Sharp ASK or
Universal Remote. Instead, this task is left to the device driver software that controls
the port. This division between hardware and software alleviates the microprocessor
from performing the time-consuming bit manipulation.

Figure 3-21. Infrared System Diagram

Microprocessor

Device-Driver

Serial Programming

Interface

CX2584x (3,2,1,0)

IRQ

IR Rx

IR Tx

IR Receiver

Module

IR Transmitter

Circuit

102284_017

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Detailed Functional Description CX25840/1/2/3 Data Sheet

3.8.2 IR Receiver

The IR receiver block, shown in Figure 3-22, captures bits and timing information
from the IR receiver module. Data can either be in the form of a modulated or an
unmodulated signal. For modulated signals, the IR port contains a demodulator which
can be enabled. The demodulated signal is then used to start and stop a counter which
measures the width of the pulse. The frequency of the clock which drives the pulse
width counter can be varied, depending on the total duration of the longest pulse
which must be measured. Next the timing value from the pulse width counter is stored
to the receive FIFO, along with the level of the pulse just measured and a tag to
indicate the data is valid. When data stops being received, the input no longer
transitions, and the pulse width counter overflows. This overflow signals the end of
the transmission.

Figure 3-22. IR Receiver Block Diagram

2-Wire Serial

(SER_DAT, SER_CLK)

Bus

Serial Programming

Interface from

Microprocessor

CX2584x (3,2,1,0)

2-Wire Serial

Bus

Register

Access

IR Rx

FIFO

IR Rx

Capture

3.8.2.1 Receive Data Demodulation

A modulated signal encodes 1s and 0s through the use of a carrier which either
transitions at a high frequency (compared to the rate of the incoming data stream), or
does not transition. In most circumstances, a high frequency transition, called a mark,
represents a logical 1, while the absence of any input signal transitions, called a space,
represents a logical 0. The IR port is programmable such that both a mark and a space
can represent either a 0 or a 1. An unmodulated signal is simply represented by the
logic level received on the IR_RX/PRGM5 pin. As with modulated signals, the
polarity of an unmodulated signal is programmable and can be programmed for
inverse sense.

A programmable clock is used for all receive logic. The frequency ranges from
27 MHz down to 823.97 Hz. If the demodulation logic is used, this programmable
clock rate must be 16 times the frequency of the input carrier. All incoming data is
first synchronized to the IR port’s internal clock. This 16-bit Receive Clock Divider
bit field is used to control the IR port’s receive clock rate. The receive clock is used to
drive both the demodulation logic and the receive pulse width timer. The IR RX Clock
Divider (0x208 and 0x209) registers are used as the modulus for a 16-bit down
counter and is decremented at half the video clock rate (108 MHz/2). Each time the
counter reaches 0 or the IR RX Clock Divider registers are written, the contents of this
register are reloaded to the counter. Each time the counter wraps to 0, a receive clock
pulse is signaled to the demodulation logic and the RX pulse width timer. The IR RX

IR_Rx Pin

IR Receiver

Module

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CX25840/1/2/3 Data Sheet Detailed Functional Description

/

k

Clock Divider bit fields can be programmed with any value from 0x01 to 0xFFFF.
The RX clock rate, given a set Receive Clock Divider value, is calculated using the
equation below:

RxClkFreq

Next, the demodulation logic looks for rising edges on the input signal. Once a rising
edge is detected, the logic expects another rising edge every 16 RX clock cycles. To
compensate for jitter in the receive carrier, or if the carrier frequency is a noninteger
multiple of the RX clock, a programmable window function is implemented which
allows the next rising edge to fall within a range of 16 clock cycles plus or minus three
to four clocks. If the edge occurs within the programmed limits, the demodulator
passes the data to a persistence counter. The persistence counter ensures that the
receiver encounters four consecutive rising edges at the predicted time in order for a
mark to be output from the demodulator. Likewise, when the carrier burst stops, the
demodulator does not output a space until four time periods elapse and a rising edge
has not been detected. This filtering function makes the demodulator somewhat
resistant to noise if carrier transitions are occasionally missed. Marks and spaces are
then output to the low-pass filter.

3.8.2.2 Low-Pass Filter

Ambient light can cause high-frequency noise to be picked up by infrared receivers.
To eliminate this noise, a low-pass filter is used. A programmable 16-bit down
counter measures the duration of each demodulated or raw unmodulated pulse which
is input to the receiver.

The 16-bit IR Low-Pass Filter (0x218 and 0x219) registers are used to prevent pulses
under a minimum width from being measured by the receive pulse counter. These
registers are used as the modulus for a 16-bit down counter that is decremented at half
the video clock rate (108 MHz/2). The counter reloads using the value programmed to
this register each time a qualified edge is detected as programmed through the EDG
bits in the IR Control 1 (0x200) register. Once the reload occurs, the counter begins
decrementing. If the next programmed edge occurs before the counter reaches 0, the
pulse measurement value is discarded, the filter modulus value is reloaded, and the
next pulse measurement begins. Thus, any pulse measurement that ends before the
counter reaches 0 is ignored.

For pulses that are greater than the minimum selected, the filter counter decrements to
0, and remains at 0 until the next qualified edge is encountered. Pulse measurements
are only stored to the RX FIFO when the filter counter reaches 0. The equation below
is used to calculate the minimum pulse width that can be measured, given the filter
register modulus value. To enable the filter, the IR Low-Pass Filter register can be
programmed with any value from 0x0004 to 0xFFFF (4 to 65535), which filters
pulses using the equation below for minimum allowable pulse duration. Values of
0x0001 through 0x0003 are not allowed. This register is reset to 0 (0x0000), which
disables the filter function.

2/108

)1(

+=erRxClkDivid

Re

asuredMinPulseMe =

vcl

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Production Data Sheet

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gValueterLowPassFil

2

Detailed Functional Description CX25840/1/2/3 Data Sheet

3.8.2.3 Pulse Width Timer

The demodulated or nonmodulated raw data is then applied to an 18-bit pulse width
timer. The RX pulse width timer uses the same programmable clock used by the
demodulation logic to measure the duration between edge transitions on the incoming
demodulated signal. If the input signal is not modulated, meaning the RX clock does
not need to be 16 times the carrier frequency, it can be programmed such that the
longest symbol width does not cause the RX pulse width counter to overflow at the
given RX clock frequency. This allows each pulse to be measured at its greatest
resolution, using the full 18-bit range of the counter.

The IR port can be programmed to measure the time between rising edges, falling
edges, or both edge types. The pulse width timer starts when the first programmed
edge type is detected and stops when the next edge is detected. At this point, the most
significant 16 bits of the 18-bit timer value is transferred to bits 15–0 at the top of the
8-entry x 18-bit receive FIFO. The logic level of the pulse (as programmed by the
polarity bit) is stored in bit 16, and bit 17 is set in the next FIFO location to denote that
the next FIFO entry contains valid data. Next, the RX pulse width timer is cleared and
again begins to increment at the programmed clock rate to measure the width of the
next pulse.

When the demodulated input signal no longer transitions, the RX pulse width timer
overflows, which indicates the end of data transmission. When this occurs, the timer
value contains all 1s. This value can be stored to the RX FIFO, to indicate the end of
the transmission if the Rx FIFO load on Timer Overload disable is not set.
Additionally, a status bit is set which can interrupt the microprocessor, if it is enabled
within the IR port. The time duration of each pulse measured can be calculated using
the following equation (the multiplication by four takes place due to the use of the
most significant 16 bits of the pulse width timer):

ionPulseDurat

=

The RX FIFO load on Timer Overload Disable allows the user to choose whether to
store or not store Rx pulse with times overflows. Noise starts the Rx pulse width
Counter and can produce overloads when not desired as in a Com mode wakeup
operation.

tValueRxFIFOCoun

)4*(

qRxClockFre

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CX25840/1/2/3 Data Sheet Detailed Functional Description

3.8.3 IR Transmitter

The IR transmitter block, shown in Figure 3-23,accepts bits for transmission from the
microprocessor and is responsible for formatting the output data into a desired
transmission specification prior to placement into the TX FIFO buffer.

Figure 3-23. IR Transmitter Block Diagram

2-Wire Serial Bus

(SER_DAT, SER_CLK)

CX2584x (3,2,1,0)

2-Wire Serial

Bus

Register

Access

For IR transmission, pulse duration count values are calculated by the microprocessor
using the same equation,

Serial Programming

Interface from

Microprocessor

IR Tx

FIFO

IR Tx

Capture

ionPulseDurat

=

IR_Tx Pin

tValueTxFIFOCoun

IR Transmitter

Module

)4*(

qTxClockFre

and written to the transmit FIFO. The TX FIFO is 8 entries by 17 bits. Bits 15–0
contain the timer count value, and bit 16 contains the logic level that is to be output
during the duration of the pulse. These count values are taken from the bottom of the
FIFO one at a time and are loaded to the most significant 16 bits of the 18-bit TX
pulse width counter. The counter decrements using a separate TX clock which is
independent of the RX clock described above. Similarly, its frequency is
programmable with a range determined by the frequency of the host clock. If the
transmit modulation logic is enabled, this programmable clock rate must also be 16
times the frequency of the output carrier.

If the output is not modulated, a clock frequency can be selected such that the longest
pulse duration does not cause the 18-bit TX pulse width timer to overflow. Again, this
provides the best resolution for each pulse that is transmitted. Once a value is loaded
into the TX pulse width counter, the programmed logic level is either driven onto the
IR_TX/PRGM6 pin, if modulation is disabled, or is passed to the modulation logic, if
it is enabled. When the counter reaches 0, the next value is taken from the bottom of
the TX FIFO, and the whole process starts once again. When the counter reaches 0
and no more data is available within the TX FIFO, it is assumed that the end of the
data stream has been reached. At this point, the IR_TX/PRGM6 pin is forced to the
level which indicates a space, as programmed by the polarity bit.

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Detailed Functional Description CX25840/1/2/3 Data Sheet

3.8.3.1 Transmit Data Modulation

If modulation is enabled, marks are represented by bursts of high frequency carrier
transitions, and spaces are represented by the absence of carrier transitions. The duty
cycle of the high-frequency transitions is programmable. Again, if modulation is
enabled, the TX clock frequency must be 16 times the desired frequency of the carrier
transitions. This 16-bit IR Transmit Clock Divider bit field is used to control the IR
port’s transmit clock rate. The transmit clock is used to drive both the modulation
logic and the transmit pulse width timer. This bit field is used as the modulus for a 16­bit down counter, which is decremented at half the video clock rate (108 MHz/2).
Each time the counter reaches 0 or the IR TX Clock Divider registers (0x204 and
0x205) are written, the contents of this register are reloaded to the counter. Each time
the counter wraps to 0, a transmit clock pulse is signaled to the modulation logic and
the TX pulse width timer.

If modulation is enabled, this field must be programmed such that the TX clock rate is
16 times the desired carrier frequency when a mark is transmitted. If modulation is
disabled, a clock frequency can be selected such that the longest pulse duration does
not cause the 18-bit TX pulse width timer to overflow. This provides the best
resolution for each pulse that is transmitted. The IR TX Clock Divider bit fields can
be programmed with any value from 0x01 to 0xFFFF. The Transmit Clock Divider is
reset to a value of 0xFFFF. The TX clock rate, given a set Transmit Clock Divider
value, is calculated using the following equation:

The period of one carrier transmitting is broken into 16 time periods. The duty cycle
register provides a selection of one of 16 different carrier duty cycles. The carrier can
be one TX clock period high and 15 low, two TX clock periods high and 14 low, and
so on. The 4-bit IR TX Carrier Duty Cycle (0x20C) register selects the duty cycle
(high time, then low time duration) of the transmit carrier when signaling a mark. The
TX carrier frequency is established by programming the IR TX Clock Divider
registers as described above. Again, the TX clock must be programmed to be 16 times
the desired frequency of the TX carrier. The IR TX Carrier Duty Cycle value then
selects one of 16 possible duty cycles: one TX clock high and 15 TX clocks low, or
two TX clocks high and 14 TX clocks low, etc. This bit field is ignored if modulation
is disabled.

3.8.4 IR FIFOs

The IR FIFO (0x23C and 0x23D) registers provide access to the IR port’s transmit and
receive FIFOs. Writes to this register access the top of the transmit FIFO, allowing it
to be filled and count values to be transmitted. A write with a value of 0x0000 to the
Tx FIFO is effectively 0xFFFF+1, or maximum pulse width. Reads of this register
access the bottom of the receive FIFO, allowing incoming pulse width measurements
to be removed. The transmit FIFO is 17 bits wide x 8 entries deep. Bits 15–0 contain
the count value to be loaded to the TX pulse width counter, and bit 16 contains the
state which should be driven to the modulation logic. The receive FIFO is 18 bits wide
x 8 entries deep. Bits 15–0 contain the pulse width measurement from the RX pulse
width counter, bit 16 contains the state of the ir_in pin at the end of the measurement,
and bit 17 is a tag which indicates whether more valid data is present within the FIFO.

TxClkFreq

2/108

)1(

+=erTxClkDivid

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CX25840/1/2/3 Data Sheet Detailed Functional Description

3.8.5 IR Controls

General control of the IR functions is programmable through the IR Control 1 (0x200)
and IR Control 2 (0x201) registers. Features which are controlled using these registers
include the following:

 RX FIFO load on timer overflow
 Loopback operation
 Carrier polarity
 FIFO service request levels
 Enabling/disabling of both the IR port’s transmitter and receiver
 Enabling/disabling of the RX and TX FIFOs
 Selection of carrier modulation and demodulation
 Control of which type of edge to start and stop the pulse timer for demodulated

receive data

 Control of a window which is used to predict when the next receive carrier

transition is expected

The user can either program the IR port’s six control registers, in any order, then write
to the transmit FIFO to start operation, or first place data in the transmit FIFO, while
the IR port is disabled, then configure the six control registers, programming this
register last to enable the IR port. When changing any configuration in these registers,
always disable the IR’s transmitter and receiver first, then reprogram the mode of
operation and enable the receiver and transmitter.

3.8.6 IR Status and Interrupts

The IR Status (0x210) register contains six status bits, four that can interrupt the
microprocessor and two that can be polled. Bits 5, 4, 1, and 0 are set and cleared
automatically by hardware and signal when a hardware condition exists which must be
handled by software. Any one of these four status bits produces an interrupt when set
and its corresponding interrupt enable bit is set. Interrupt enable bits do not affect the
setting and clearing of status bits. The transmit and receive busy flags are also set and
cleared automatically by hardware, bits 2 and 3, but do not produce interrupts. They
are polled by software to query whether the IR port is currently transmitting and/or
receiving IR data. The Interrupt Enable Register (IR_IRQEN_REG) is programmed
to enable/disable the transmit and receive FIFO service requests to signal interrupts to
the interrupt controller. This register is read-only; writes have no effect.

The IR Interrupt Enable (0x214) register contains four bits which are used to mask or
enable individual interrupt requests. Refer to the above IR Status (0x210) register for
a description of each interrupt source. The interrupt enable bits do not effect the
setting and clearing of the interrupt status bits. Each enable bit is logically ANDed
with its corresponding status bit, and the resultant signals are all logically ORed to
produce a single interrupt request to the interrupt controller.

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Detailed Functional Description CX25840/1/2/3 Data Sheet

3.9 Auxiliary PLL, Video-Locked Master Clock

In addition to the PLL dedicated for clocking the video decoder data path, a second
auxiliary PLL is provided for general-purpose use. The user can program the auxiliary
PLL for any reference frequency desired. One intended use is to use this PLL as an
audio master clock, or OSR (oversampled ratio) clock, to clock the audio DACs or
ADCs in the system. If so, an optional feature is provided to enable the locking of this
clock to the video pixel rate.

Many applications require synchronization between the video pixel rate and the audio
sample rate. This is particularly important for applications that compress audio and
video data into MPEG frames for subsequent playback. To support these applications,
the device provides an audio master clock that is locked to the video pixel rate. This
master clock can be divided down to generate the serial audio word clocks, bit clocks,
and the OSR clocks. In the context of the video decoder, a “locked” audio clock
means that there is a constant ratio between the number of video pixel clocks and
audio sample clocks. This ratio is defined as any integer number of audio clocks to
another integer number of video clocks. The EN_AV_LOCK bit in the Audio Lock 1
(0x12B) register controls the video-audio locking. Setting this register to 1 enables
video-audio locking. When the locking is not enabled, the PLL values pass straight
through the filter.

The audio clock is loosely coupled through a locking loop. Thus, for any given set of
audio samples, there are not necessarily a fixed number of video samples. However,
over the long term, the ratio will be maintained. Thus the sample-rate ratio is def ined
by defining two numbers that must equal each other over the long term. The
AUD_COUNT bits (0x12C to 0x12E) contains a 24-bit integer value representing the
number of audio clocks, and the 24-bit VID_COUNT bits (0x128 to 0x12A)
represents the fractional number of video clocks that are expected in the time frame of
the audio register. The VID_COUNT register contains 21 integer bits and 3 fractional
bits. The locking loop will drive the audio PLL such that this ratio is maintained. Lock
is maintained as long as the accumulated difference between audio samples and video
pixels does not exceed one-half of a video field.

The locking algorithm counts a number of audio clocks from an audio clock
reference, equal to the number programmed into the AUD_COUNT register. The
reference for the audio clock is the AUX_PLL, which is always equal to 384 times the
audio sample rate.

A video count register accumulates the number of video pixel clocks during this
interval. The difference between the accumulated number of pixel clocks and the
expected value in VID_COUNT def ines the error term. The reference for the video
clock is a clock that is 8 times the pixel rate. Since jitter can exist due to clock domain
synchronization issues, and because the video pixel clock can be somewhat unstable
in order to lock to sources such as VCRs, the error term is heavily filtered (a low loop
gain) to maintain a clean audio clock.

The fractional portion of the VID_COUNT register provides a degree of flexibility in
the required parameter in the AUD_COUNT register, and thus how often the loop
updates. Without fractional capability, the value required in the AUD_COUNT
register might have to be so large that the loop is updated too infrequently.

Table 3 -2 8 contains examples of how these registers should be programmed for

common audio sample rates and video pixel rates. Notice that the fractions can be
exactly represented through binary numbers. These values demonstrate the minimum
requirements. The user may want to multiply both AUD_COUNT and VID_COUNT

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CX25840/1/2/3 Data Sheet Detailed Functional Description

numbers by a common integer such that all modes have similar loop update rates. The
video pixels and audio samples columns show the minimum ratio of whole pixel to
whole sample counts. However, because the actual clocks are multiples of the video
pixel and audio sample rates, and because the video count can be specified to 3-bit
fractional granularity, the logic does not have to wait for that long to measure the ideal
ratio. Table 3-28 shows the minimum values of AUD_COUNT and VID_COUNT that
will achieve the desired ratio. The VID_COUNT register value assumes an 8x pixel
clock and a 21-bit integer, 3-bit fractional number. The AUD_COUNT register value
assumes a 384 x sample rate clock.

Table 3-28. 43 Locking Register Values for Common Audio Sample Rate

Video Pixel

Rate

13.5 M 48 k 1,125 4 0x1193F8 0x05FFF

13.5 M 96 k 1,125 8 0x08CAF8 0x02FFF

13.5 M 32 k 2,250 8 0x0D2EF8 0x02FFF

13.5 M 44.1 k 4,500 147 0x057E38 0x01B8F

14.75 M 48 k 7,375 24 0x0733B8 0x023FF

14.75 M 96 k 7,375 48 0x0733B8 0x047FF

14.75 M 32 k 7,375 16 0x0733B8 0x017FF

14.75 M 44.1 k 147,500 441 0x0900A8 0x02957

12.27 M 48 k 818,181 3,200 0x0C7BFD 0x04AFF

12.27 M 96 k 818,181 6,400 0x0C7BFD 0x095FF

12.27 M 32 k 2,454,543 6,400 0x257407 0x095FF

12.27 M 44.1 k 272,727 980 0x04294F 0x016F7

Audio Sample

Rate

The table entries show the exact ratio, and the event that generates an error happens
faster than the field rate of 60 Hz. (NTSC square pixel with 32 kHz audio would have
a worst-case update rate of 40 Hz. However, because the AUD_COUNT integer is
divisible by eight, and there are still three bits of resolution in the VID_COUNT
register, both numbers could be divided by eight to reduce the update frequency to
320 Hz.)

Video Pixels Audio Samples

Recommended

VID_COUNT

Recommended

AUD_COUNT

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Detailed Functional Description CX25840/1/2/3 Data Sheet

3.10 Register Addressing

The user-programmable registers can be programmed through either a two-wire serial
interface or the VIP Host port. In either method, there is a portion of the cycle in
which a register subaddress is passed over the interface. The internal register space is
based on a 16-bit subaddressing scheme. (The address space is currently limited to 12
bits based on VIP Host port limitations.) Table 3-29 shows how the address space is
organized among the major submodules of the IC.

The first address space is used for the serial port mechanism, whether it is the two­wire interface or the VIP Host port. The mapping of these 256 bytes depends on
which of the two interfaces is active. This space is used to configure the operation of
the serial interface itself. It is also used for configuring power-down states. Since the
serial interfaces receive their own external clocks, these modules can be used to shut
down the other digital clocks.

See Section 5 for a full definition of the register address space.

Table 3-29. Register Subaddresses

Subaddress[11:8] Register File Size (bytes)

0000 Two-wire serial/VIP 256

0001 Chip Config 256

0010 IR Blaster 256

0011 RESERVED 256

0100 Video and VBI 1K

1xxx RESERVED 2K

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CX25840/1/2/3 Data Sheet Detailed Functional Description

3.11 Two-Wire Communications Port

The device communicates over a 400 kHz, two-wire serial interface or a 2-bit VIP
host interface. These two interfaces share pins and are mutually exclusive. The
VIP_ENABLE reset strap selects either the VIP Host or the serial slave
communication mode.

3.11.1 Serial Slave Interface

The registers can be accessed through a two-wire serial bus interface operating as a
slave device. The serial clock and data lines SER_CLK and SER_DATA transfer data
from the bus master. A CHIP_SEL/VIPCLK pin is available to configure the device
for one of two possible chip addresses. The device address byte can be either 0x88 or
0x8A for write cycles, or 0x89 or 0x8B for read cycles. (The ALTADDR_SEL reset
strap also enables a 0x8C/0x8D and 0x8E/0x8F option. See Section 3.16 for more
details.)

3.11.2 Starting and Stopping

The relationship between SER_CLK and SER_DATA is decoded to provide both a
start and stop condition on the bus. To initiate a transfer on the serial interface bus, the
master must transmit a start pulse to the slave device by taking the SER_DATA line
low while the SER_CLK line is held high. The master should only generate a start
pulse at the beginning of the cycle, or after the transfer of a data byte to or from the
slave. To terminate a transfer, the master must take the SER_DATA line high while the
SER_CLK line is held high. The master can issue a stop pulse at any time during a
cycle. Since the interface interprets any transition on the SER_DATA line during the
high phase of the SER_CLK line as a start or stop pulse, ensure that data is stable
during the high phase of the clock. Figure 3-24 provides a timing diagram for the
serial start and stop transaction.

Figure 3-24. Serial Start and Stop Transaction

SER_CLK

SER_DATA

StopStart

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Detailed Functional Description CX25840/1/2/3 Data Sheet

3.11.3 Chip Addressing

The device’s serial interface chip address consists of two parts: a 7-bit base address
and a single-bit R/W command. The R/W bit is appended to the base address to form
the transmitted address.

A6 A5 A4 A3 A2

Table 3-30. Chip Addressing

Serial Address

88 0 1 1000100 0 Write

8A 1 1 1000101 0 Write

8C 0 0 1000100 0 Write

8E 1 0 1000101 0 Write

CHIP_SEL/

VIPCLK Pin 17

A1 A0 R/W

Base Address R/W Bit

Table 3 -3 0 defines chip addressing.

IRQ_N/PRGM4

Pin 10

0 1 1000100 1 Read

1 1 1000101 1 Read

0 0 1000100 1 Read

1 0 1000101 1 Read

Base Address R/W Bit Action

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3.11.4 Reading and Writing

After transmitting a start pulse to initiate a cycle, the master must address the device.
To do this, the master must transmit one of the four valid chip addresses, with the
Most Significant Bit (MSB) transmitted first. After transmitting the address, the
master must release the SER_DATA line during the low phase of the SER_CLK and
wait for an acknowledge. If the transmitted address matches the selected chip address,
the device responds by driving the SER_DATA line low, generating an acknowledge to
the master. The master samples the SER_DATA line at the rising edge of the
SER_CLK line, and proceeds with the cycle. If no device responds, the master
transmits a stop pulse and ends the cycle.

If the slave address R/W bit is low, indicating a write, the master must transmit the
16-bit subaddress as two 8-bit bytes, MSB first. The device acknowledges the transfer
and loads data into its internal address register. The master then issues a stop
command, a start command, or transfers an 8-bit byte, MSB first, which is loaded into
the register specified by the internal address register. The device then acknowledges
the transfer and increments the address register in preparation for the next transfer. As
before, the master may issue a stop command, a start command, or transfer another 8
bits to be loaded into the next location.

If the slave address R/W bit is high, indicating a read, the device transfers the contents
of the register specified by its internal address register, MSB first. The master must
acknowledge receipt of the data and pull the SER_DATA line low. As with the write
cycle, the address register is auto incremented, in preparation for the next read. To
stop a read transfer, the host must not acknowledge the last read cycle. The device
then releases the data bus in preparation for a stop command. If an acknowledged
pulse is received, the chip proceeds to transfer the next register.

When the master generates a read from the device, it starts its transfer from whatever
location is currently loaded in the address register. Because the address register might
not contain the address of the desired register, the master executes a write cycle and
sets the address register to the desired location. After receiving an acknowledgment
for the transfer of data into the address register, the master initiates a read of the
device by starting a new serial interface cycle with an appropriate read address. The
device then transfers the contents of the desired register. Serial communications
protocol is illustrated in Figure 3-25.

Figure 3-25. Serial Communications Protocol

Data Write

SA A DATA A ADATASUB-ADDR MSBCHIP ADDR

0 x 88 or 0 x 8A

Data Write

SADATAADATAAADATA A NA PDATACHIP ADDR

0 x 89 or 0 x 8B

Write Followed by Read

SA ADATAAADATA A PNADATAASRSUB-ADDRCHIP ADDR CHIP ADDR

0 x 88 or 0 x 8A Repeated

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8 Bits 8 Bits+

16 Bits

Starts

SUB-ADDR LSB

. . .

by Subadress

A

Register

Pointed to

. . .

S = START

P

SR = REPEATED START
P = STOP
A = ACKNOWLEDGE
NA = NON ACKNOWLEDGE

From Master to
CX25840/1/2/3

From CX25840/1/2/3 to
Master

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Detailed Functional Description CX25840/1/2/3 Data Sheet

3.12 VIP 2 Host Interface

The VIP 2 Host Interface provides a faster alternative interface to the two-wire serial
communication interface. The VESA VIP 2 Host slave interface is a high-bandwidth,
minimal-pin-count interface for connecting multiple video components. Refer to the
Video Electronics Standards Association (VESA) Video Interface Port, version 2
specification for full implementation details. The VIP 2 Host slave interface enables
the chip to communicate with devices that are compliant with either the VIP 1.1 or 2
master specifications. The host interface provides read accesses to the FIFO and
Read/Write accesses to the register space.

The VIP Host Interface also supports the following:

 Burst reads of the registers with at most one wait phase per byte
 Power management configuration through writes into the command register
 Power reporting in the status registers

The VIP Host interface works on the VIPCLK pin, which doubles as CHIP_SEL/
VIPCLK in the two-wire serial mode. The VIP 2 Host interface block takes care of the
serialization of the data flow from the device to the a VIP Master (graphics chip) and
the serial to parallel conversion of the data flow from the VIP Master to the device.
The VIP Host interface block follows the VIP 2 specification, which stipulates that,
for reliable operation, all register accesses must be at most one wait phase per byte
and no wait phases for FIFO operations.

3.12.1 Address Space

The VIP Master can address 4096 locations. VIP address spaces are defined in

Table 3 -3 1.

Table 3-31. VIP Address Spaces

Address Space Block Select bit

000–00F

010–FFF

VIP configuration space

Local register space

3.12.2 VIP Power-Up Detection

On power-up, the VIP master asserts VRST. The device holds the HAD[0] line low
until VRST remains asserted. Once the VRST is deasserted, the host interface drives
the HAD[0] line to a three-state, indicating the signal’s presence on the VIP bus.

Vip_sel

Reg_sel

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3.12.3 VIP Power Modes

The VIP master can configure the device for different power modes. The device
supports all four modes, as described in the VIP 2 specification. The master must
write to bits [1:0] of the command register to configure the chip for these different
power modes.

 P0: The device is operating in the normal power consumption mode without any

part of the chip being put to sleep. This is the default mode.

 P1: In this mode, the digital part of the chip is shut down. It essentially turns off all

the clocks to the digital part of device. This mode has a turn-on latency of less than
10 ms. The VIP clock will be on, and the graphics chip can access the
configuration registers (000:00D addresses).

 P2: In this mode, the analog portions of the chip are shut down as well. The host

interface turns off the power to the digital part and the analog portions of the chip.
Turn-on latency is less than 1 second. The VIP master can turn off the VIPCLK in
this mode. However, if the clock is supplied, the master will be able to access the
configuration registers (000:00D address).

 P3: The device supports the P3 powered down mode where it consumes minimal

power. The VIP master stops the VIPCLK to the block in a power-down mode. In
this mode, the host interface will drive the VIP interface pins to a three-state. The
host interface asserts a sleep signal, and this turns of the power to digital and the
analog parts of the chip. This mode is the same as the power mode P2.

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3.13 Hardware Interrupt

The interrupt pin, IRQ_N/PRGM4 (VIRQ_N in VIP mode) signals interrupt
conditions that occur within the chip. An interrupt condition can be enabled through
the Interrupt Mask 1 and Interrupt Mask 2 (0x412 and 0x413) register. Setting the
appropriate video decoder or IR controller bits in the register masks the assertion of
the interrupt pin. The Interrupt Status 1 and Interrupt Status 2 (0x410 and 0x411)
registers allow the status of each of those interrupts to be checked separately. There is
also an option to invert the polarity of the pin.

3.14 I/O Pin Configuration

3.14.1 Output Pin Configuration

The digital I/O pin functionality is extremely flexible. The CX25840/1/2/3 provides
up to eleven programmable pins. These configurable GPIOs are shared with the
following pin/port groups so that the user can assign exactly which pins can be
dedicated to specific functions versus general purpose I/O functions.

 Video Timing Control (VRESET/HCTL/PRGM3 is unavailable when VIP Host

mode is selected)

 Interrupt pin
 Infrared Remote Transmit
 Infrared Remote Receive
 Auxiliary PLL Output Clock

Any of the programmable pins can be conf igured to provide alternate functions from
their default state. This allows customization of the output interface in order to fit a
wide variety of system requirements. Ta ble 3 -3 2 shows the default state of the
programmable pins after reset.

Table 3-32. Default PRGM[0:7] Pin Configuration

Pin Name

DVALID/PRGM0 DVALID Default function is a valid pixel data indicator. When asserted, indicates a valid pixel. Can be

FIELD/PRGM1 FIELD Default function is field indicator. Even/Odd Field indicator (0 = odd field, 1 = even field). Field

HRESET/PRGM2 HRESET Default function is horizontal reset indicator. Asserted at 0H sync point, held for 32 or 64 clocks.

VRESET/HCTL/
PRGM3

IRQ_N/PRGM4 IRQ_N Interrupt pin
IR_TX/PRGM6 IR_TX Infrared Remote Transmit
IR_RX/PRGM5 GPO[2] Infrared Remote Receive. This is by default an input, so the output select will be a don’t care

PLL_CLK/PRGM7 GPO[3] Auxiliary PLL output clock. This default mode is to select the PLL output from inside the analog

GPIO[0]/PRGM8 GPO[0] Configurable Multifunction Status/Control Pins
GPIO[1]/PRGM9 GPO[1] Configurable Multifunction Status/Control Pins

Default

Output Select

programmed for alternate functions in Ta ble 3 -3 3.

resets to 0, odd, and toggles every new_field. Can be programmed for alternate functions in

Tab le 3-3 3.

Width can be configured through HR32 bit in MISC_TIM_CTRL register in video decoder core.
Can be programmed for alternate functions in Ta bl e 3 -3 3.

VRESET Default function is vertical reset indicator. Asserted from vsync begin (start of serration pulses)

through end of equalization pulse period, nominally 5 or 6 lines depending on video standard.
Can be programmed for alternate functions in Table 3 -33 . In VIP mode this pin becomes the Host
Interface Reset Input and is not programmable.

unless put in output mode.

domain, so this output select will be a don’t care unless CLK_PAD_IN is selected from the digital
core.

Description

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Alternatively, the following functions in Ta bl e 3-33 are available by programming the
Pin Configuration registers (0x11C to 0x122). The XXX_OUT_SEL field select
which internal signal is output on the PRGMx pin. The default output 0 value is
determined by the specific output pin.

Table 3-33. Alternate PRGM[0:7] Pin Functions

0 = Pin Dependant

1 = ACTIVE (Composite active or horizontal active indicator. See ACTFMT bit of OUT_CTRL1
register in video decoder core.

)

2 = VACTIVE (Vertical active indicator. Asserted during all vertical active lines.)
3 = CBFLAG (Cr/Cb indicator (0 = Cr, 1 = Cb) Cbflag is reset to cb at the beginning of each

line and toggles every pixel clock period.

)

4 = VID_DATA_EXT[0] (Extended Video Data. Least significant bits of internal 10-bit video
bus. When enabled, 10-bit video is possible.

)

5 = VID_DATA_EXT[1] (Extended Video Data. Least significant bits of internal 10-bit video
bus. When enabled, 10-bit video is possible.

)

6 = GPO[0] (Data from internal GPIO flops.)
7 = GPO[1] (Data from internal GPIO flops.)
8 = GPO[2] (Data from internal GPIO flops.)
9 = GPO[3] (Data from internal GPIO flops.)
A = IRQ_N/PRGM4 (Interrupt output: default active low polarity)

B = AC_SYNC
C = AC_SDOUT
D = PLL_CLK
E = VRESET/HCTL/PRGM3 (vertical reset indicator)
F = RESERVED

Any signal shown in Figure 3-26 can be routed to any pin.

Figure 3-26. Output Signals Connection and Routing to Pins

Output Signals

Output Values

Bit Location

GP Flop

GPO0

GPO1

GPO2

GPO3

0

1

2

3

Register 126

Output Mux Value

Default unique to pin

ACTIVE

VACTIVE

CBFLAG

VID_DATA_EXT[0]

VID_DATA_EXT[1]

GPO[0]

GPO[1]

GPO[2]

GPO[3]

IRQ_N

AC_SYNC

AC_SDOUT

PLL_CLK

VRESET

RESERVED

Hex

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Pin #

17

23

22

21

18

10

8

9

7

4

46

Pins/Output Mux

Name (Default)

CHIP_SEL/VIPCLK (GPO[0])

DVALID/PRGM0 (DVALID)

FIELD/PRGM1 (FIELD)

HRESET/PRGM2 (HRESET)

VRESET/HCTL/PRGM3 (VRESET)

IRQ_N/PRGM4 (IRQ_IN)

IR_TX/PRGM6 (IR_TX)

IR_RX/PRGM5 (GPO[2])

GPIO[0]/PRGM8 (GPO[0])

GPIO[1]/PRGM9 (GPO[1])

PLL_CLK_PRGM7 (PLL_CLK)

Enable

Register Bit

114 2

114 6

114 7

115 0

115 1

114 3

114 5

114 4

114 0

114 1

116 2

Output Mux Location

Register Bit

11D

3:0

11F

3:0

11F

7:4

120

3:0

120

7:4

11D

7:4

11E

7:4

11D

3:0

11D

3:0

11D

7:4

122

7:4, 2:0

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Detailed Functional Description CX25840/1/2/3 Data Sheet

For example, if you want to read the signal VACTIVE on pin 23 (DVALID/PRGM0),
enable the signal by programming the output mux to a decimal 2 on register 0x11F,
bits 3:0. The signal VACTIVE can now be read on pin 23 (DVALID/PRGM0).
However, if you want to read any signal on pin 46 (PLL_CLK/PRGM7), set bit 2 of
register 0x115, then program the output mux to X11 (x = don’t care) on register
0x122, bits 2:0, and finally, register 0x122, bits 7:4. See Figure 3-27.

Figure 3-27. Reading the VACTIVE Signal on Pin 23 (DVALID/PRGM0)

Output Signal

VACTIVE DVALID/PRGM0 (DVALID)

Enable bit 6 of register 0x114.
Program bits 3:0 of register 0x11F to 0x02.

3.14.2 Input Pin Configuration

For general purpose inputs, there are four internal registers that can be programmed to
receive their state from the pins shown in Tab le 3-34. The input pin for each general
purpose input can be programmed through the GPIOx_IN_SEL bits in the Pin
Configuration 9 and 10 registers (0x124 and 0x125). Bits 0x0 of GPIO{3:0}_IN_SEL
select the pin input that is assigned to the internal GPIx input flip-flop.

Table 3-34. Alternate GPI0 Pin Functions

0 = DVALID/PRGM0
1 = FIELD/PRGM1
2 = HRESET/PRGM2
3 = VRESET/PRGM3
4 = IRQ_N/PRGM4
5 = IR_TX/PRGM6
6 = IR_RX/PRGM5
7 = RESERVED
8 = RESERVED
9 = RESERVED
0xA = RESERVED
0xB = PLL_CLK

Pin

102284_060

3-74 Conexant 102284B

Production Data Sheet

8/3/05