Datasheet CX11250, CX20437, CX20463 Datasheet (CONEX)

Page 1

SmartHSF





Mobile Modem

Host-Processed, V.90/K56flex CX11250 Host Side Device, CX20463 SmartDAA Optional CX20437 Voice Codec for PCI Bus/Mini PCIBased Mobile Applications

Data Sheet

Conexant Proprietary Information

Modem Device Set with



, and



Doc. No. 100553B July 28, 2000

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SmartHSF Mobile Modem Data Sheet

Revision History

Revision Date Comments

B 7/28/2000 Revision B release.

A 4/19/2000 Initial release.

Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Conexant’s Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever.

THESE MATERIALS ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. CONEXANT SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.

Conexant products are not intended for use in medical, lifesaving or life sustaining applications. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale.

The following are trademarks of Conexant Systems, Inc.: Conexant™, the Conexant C symbol, “What’s Next in Communications Technologies”™, K56flex™, SmartDAA™, and SmartHSF. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners.

For additional disclaimer information, please consult Conexant’s Legal Information posted at www.conexant.com, which is incorporated by reference.

Reader Response:

suggestions to tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications engineer.

Conexant Systems, Inc.

Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and

Conexant

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Contents

REVISION HISTORY .....................................................................................................................................................II

1. INTRODUCTION................................................................................................................................................. 1-1

1.1 OVERVIEW .............................................................................................................................................. 1-1

1.2 FEATURES .............................................................................................................................................. 1-4

1.2.1 General Modem Features .......................................................................................................... 1-4

1.2.2 PCI Bus Host Interface Features ............................................................................................... 1-5

1.2.3 SmartDAA Features ................................................................................................................... 1-5

1.2.4 Applications................................................................................................................................ 1-5

1.3 TECHNICAL OVERVIEW......................................................................................................................... 1-5

1.3.1 General Description ................................................................................................................... 1-5

1.3.2 Host Modem Software................................................................................................................ 1-5

1.3.3 Operating Modes........................................................................................................................ 1-6

Data/Fax Modes................................................................................................................ 1-6

Synchronous Access Mode - Video Conferencing............................................................ 1-6

TAM Mode......................................................................................................................... 1-6

Voice/Speakerphone Mode (S Models)............................................................................. 1-6

Personal Digital Cellular High Speed Mode (C Models).................................................... 1-6

PDC Packet Mode (C Models) .......................................................................................... 1-7

PHS Mode (C Models) ...................................................................................................... 1-7

cdmaOne Data Mode IS95A (C Models)........................................................................... 1-7

cdmaOne Data Packet Mode IS95B (C Models)............................................................... 1-7

GSM Mode (C Models)...................................................................................................... 1-7

1.3.4 Reference Design ...................................................................................................................... 1-7

1.4 HARDWARE DESCRIPTION ................................................................................................................... 1-7

1.4.1 CX11250 Host Side Device........................................................................................................ 1-7

1.4.2 Digital Isolation Barrier............................................................................................................... 1-8

1.4.3 CX20463 SmartDAA Line Side Device ...................................................................................... 1-8

1.4.4 CX20437 Voice Codec (S Models) ............................................................................................ 1-8

2. TECHNICAL SPECIFICATIONS......................................................................................................................... 2-1

2.1 ESTABLISHING DATA MODEM CONNECTIONS ................................................................................... 2-1

Dialing ............................................................................................................................... 2-1

Modem Handshaking Protocol.......................................................................................... 2-1

Call Progress Tone Detection ........................................................................................... 2-1

Answer Tone Detection..................................................................................................... 2-1

Ring Detection................................................................................................................... 2-1

Billing Protection ............................................................................................................... 2-1

Connection Speeds........................................................................................................... 2-1

Automode.......................................................................................................................... 2-1

2.2 DATA MODE ............................................................................................................................................ 2-1

Speed Buffering (Normal Mode) ....................................................................................... 2-1

DTE-to-Modem Flow Control............................................................................................. 2-1

Escape Sequence Detection............................................................................................. 2-1

GSTN Cleardown (V.90/K56flex, V.34, V.32 bis, V.32)..................................................... 2-2

Fall Forward/Fallback (V.90/K56flex, V.34/V.32 bis/V.32) ................................................ 2-2

Retrain............................................................................................................................... 2-2

2.3 ERROR CORRECTION AND DATA COMPRESSION............................................................................. 2-2

V.42 Error Correction ........................................................................................................ 2-2

MNP 2-4 Error Correction.................................................................................................. 2-2

V.42 bis Data Compression .............................................................................................. 2-2

MNP 5 Data Compression ................................................................................................ 2-2

2.4 FAX CLASS 1 OPERATION..................................................................................................................... 2-2

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2.5 VOICE/TAM MODE.................................................................................................................................. 2-2

2.5.1 Online Voice Command Mode ................................................................................................... 2-2

2.5.2 Voice Receive Mode .................................................................................................................. 2-3

2.5.3 Voice Transmit Mode ................................................................................................................. 2-3

2.5.4 Speakerphone Modes................................................................................................................ 2-3

2.6 FULL-DUPLEX SPEAKERPHONE (FDSP) MODE.................................................................................. 2-3

2.7 CALLER ID............................................................................................................................................... 2-3

2.8 MULTIPLE COUNTRY SUPPORT (W MODELS) .................................................................................... 2-3

2.8.1 OEM Programmable Parameters............................................................................................... 2-3

2.8.2 Blacklist Parameters .................................................................................................................. 2-4

2.9 DIAGNOSTICS......................................................................................................................................... 2-4

2.9.1 Commanded Tests..................................................................................................................... 2-4

2.10 LOW POWER SLEEP MODE .................................................................................................................. 2-4

3. HARDWARE INTERFACE.................................................................................................................................. 3-1

3.1 CX11250 HSD HARDWARE PINS AND SIGNALS.................................................................................. 3-1

3.1.1 HSD Signal Interfaces................................................................................................................ 3-1

PCI Bus/Mini PCI Host Interface ....................................................................................... 3-1

Power Detection and Switching ........................................................................................ 3-1

Serial EEPROM Interface.................................................................................................. 3-1

LSD Interface (Through DIB) ............................................................................................ 3-2

VC Interface (S Models).................................................................................................... 3-2

Telephone Handset Interface (S Models) ......................................................................... 3-2

Call Progress Speaker Interface ....................................................................................... 3-2

PDC/PDC packet Interface ............................................................................................... 3-2

PHS Interface.................................................................................................................... 3-2

CDMA Interface................................................................................................................. 3-3

GSM Interface...................................................................................................................3-3

3.1.2 HSD Interface Signals, Pin Assignments, and Signal Definitions .............................................. 3-3

MART

3.2 CX20463 S

3.2.1 LSD Signal Interfaces .............................................................................................................. 3-16

3.2.2 LSD Interface Signals, Pin Assignments, and Signal Definitions............................................. 3-16

3.3 CX20437 VC HARDWARE PINS AND SIGNALS (S MODELS) ............................................................ 3-21

3.3.1 VC Signal Interfaces ................................................................................................................ 3-21

3.3.2 VC Interface Signals, Pin Assignments, and Signal Definitions............................................... 3-21

3.4 ELECTRICAL ENVIRONMENTAL, AND TIMING SPECIFICATIONS .................................................... 3-27

3.4.1 Operating Conditions, Absolute Maximum Ratings, and Power Requirements ....................... 3-27

3.4.2 SERIAL EEPROM INTERFACE TIMING ................................................................................. 3-29

4. HOST SOFTWARE INTERFACE ....................................................................................................................... 4-1

4.1 PCI CONFIGURATION REGISTERS....................................................................................................... 4-1

4.1.1 0x00 - Vendor ID Field ............................................................................................................... 4-2

4.1.2 0x02 - Device ID Field................................................................................................................ 4-2

4.1.3 0x04 - Command Register ......................................................................................................... 4-2

4.1.4 0x06 - Status Register................................................................................................................ 4-3

4.1.5 0x08 - Revision ID Field............................................................................................................. 4-3

4.1.6 0x09 - Class Code Field............................................................................................................. 4-3

4.1.7 0x0D - Latency Timer Register .................................................................................................. 4-3

4.1.8 0x0E - Header Type Field .......................................................................................................... 4-3

4.1.9 0x28 - CIS Pointer Register ....................................................................................................... 4-3

4.1.10 0x2C - Subsystem Vendor ID Register ...................................................................................... 4-3

4.1.11 0x2E- Subsystem ID Register .................................................................................................... 4-4

4.1.12 0x34 - Cap Ptr ............................................................................................................................ 4-4

4.1.13 0x3C - Interrupt Line Register .................................................................................................... 4-4

DAA LSD HARDWARE PINS AND SIGNALS.............................................................. 3-16

HSD Interface (Through DIB).......................................................................................... 3-16

Telephone Line Interface ................................................................................................ 3-16

Speakerphone Interface.................................................................................................. 3-21

Telephone Handset/Headset Interface ........................................................................... 3-21

HSD Interface.................................................................................................................. 3-21

Caution: Handling CMOS Devices .................................................................................. 3-27

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4.1.14 0x3D - Interrupt Pin Register...................................................................................................... 4-4

4.1.15 0x3E - Min Grant Register.......................................................................................................... 4-4

4.1.16 0x3F - Max Latency Register ..................................................................................................... 4-4

4.1.17 0x40 - Capability Identifier.......................................................................................................... 4-4

4.1.18 0x41 - Next Item Pointer ............................................................................................................ 4-4

4.1.19 0x42 - PMC - Power Management Capabilities ......................................................................... 4-5

4.1.20 0x44 - PMCSR - Power Management Control/Status Register (Offset = 4)............................... 4-5

4.1.21 0x46 - PMCSR_BSE - PMCSR PCI to PCI Bridge Support Extensions..................................... 4-6

4.1.22 0x47 - Data................................................................................................................................. 4-6

4.2 BASE ADDRESS REGISTER .................................................................................................................. 4-6

4.3 SERIAL EEPROM INTERFACE............................................................................................................... 4-7

4.3.1 Supported EEPROM Sizes ........................................................................................................ 4-7

4.3.2 Definitions .................................................................................................................................. 4-8

Device ID Register ............................................................................................................ 4-8

Vendor ID Register............................................................................................................ 4-8

Subsystem Vendor ID and Subsystem Device Register ................................................... 4-8

Min_Gnt Register .............................................................................................................. 4-8

Max_Lat Register.............................................................................................................. 4-8

PMC [8:6] and PME DRV Type ......................................................................................... 4-9

Class Code Register (Class Code, Sub-class Code, Prog. I/F)........................................ 4-9

CardBus CIS Pointer (CardBus CIS pointer High, CardBus CIS pointer Low) (Not

Used)................................................................................................................................. 4-9

Data Scale PMCSR[14:13] (D0C, D1C, D2C, D3C, D0D, D1D, D2D, D3D) ..................... 4-9

Data Register (D3, D2, D1, D0 power consumed and D3, D2, D1, D0 power

dissipated)......................................................................................................................... 4-9

Load CISRAM Count (CIS _SIZE) (Not Used).................................................................. 4-9

5. PACKAGE DIMENSIONS................................................................................................................................... 5-1

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Figures

Figure 1-2. SmartHSF Modem Major Interfaces....................................................................................................................... 1-3

Figure 3-1. CX11250 HSD Hardware Interface Signals ........................................................................................................... 3-4

Figure 3-2. CX11250 HSD 100-Pin TQFP Pin Signals............................................................................................................. 3-5

Figure 3-3. CX20463 LSD Hardware Interface Signals.......................................................................................................... 3-17

Figure 3-4. CX20463 LSD 32-Pin TQFP Pin Signals ............................................................................................................. 3-17

Figure 3-5. CX20437 VC Hardware Interface Signals............................................................................................................ 3-22

Figure 3-6. CX20437 VC 32-Pin TQFP Pin Signals ............................................................................................................... 3-22

Figure 3-7. Waveforms - Serial EEPROM Interface ............................................................................................................... 3-29

Figure 5-1. Package Dimensions - 100-Pin TQFP ................................................................................................................... 5-1

Figure 5-2. Package Dimensions - 32-pin TQFP...................................................................................................................... 5-2

Tables

Table 1-1. SmartHSF Modem Models and Functions............................................................................................................... 1-2

Table 3-1. CX11250 HSD 100-Pin TQFP Pin Signals.............................................................................................................. 3-6

Table 3-2. CX11250 HSD Pin Signal Definitions...................................................................................................................... 3-9

Table 3-3. Cell Phone/Telephone Line Interface Signals ....................................................................................................... 3-15

Table 3-4. CX20463 LSD 32-Pin TQFP Pin Signals............................................................................................................... 3-18

Table 3-5. CX20463 LSD Pin Signal Definitions .................................................................................................................... 3-19

Table 3-6. CX20463 LSD DC Electrical Characteristics......................................................................................................... 3-20

Table 3-7. CX20437 VC 32-Pin TQFP Pin Signals................................................................................................................. 3-23

Table 3-8. CX20437 VC Pin Signal Definitions ...................................................................................................................... 3-24

Table 3-9. CX20437 VC Digital Electrical Characteristics...................................................................................................... 3-26

Table 3-10. CX20437 VC Analog Electrical Characteristics................................................................................................... 3-26

Table 3-11. Operating Conditions........................................................................................................................................... 3-27

Table 3-12. Absolute Maximum Ratings................................................................................................................................. 3-27

Table 3-13. Current and Power Requirements....................................................................................................................... 3-28

Table 3-14. Timing - Serial EEPROM Interface...................................................................................................................... 3-29

Table 4-1. PCI Configuration Registers.................................................................................................................................... 4-1

Table 4-2. Command Register ................................................................................................................................................. 4-2

Table 4-3. Status Register........................................................................................................................................................ 4-3

Table 4-4. Power Management Capabilities (PMC) Register ................................................................................................... 4-5

Table 4-5. Power Management Control/Status Register (PMCSR).......................................................................................... 4-5

Table 4-6. HSD Address Map................................................................................................................................................... 4-6

Table 4-7. EEPROM Content for 256 Words by 16 Bits per Word ........................................................................................... 4-7

Table 4-8. EEPROM Content for 128 Words by 16 Bits per Word ........................................................................................... 4-7

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1. INTRODUCTION

1.1 OVERVIEW

The Conexant SmartHSF Host-Processed (SoftK56) V.90/K56flex Modem Device Family with SmartDAA technology supports analog data up to 56 kbps, analog fax to 14.4 kbps, telephone answering machine (TAM), and PCI Bus/Mini PCI host interface operation. In addition, the device set optionally supports cellular phone interface (PDC high speed/PDC packet data, PHS data, CDMA/CDMA Packet data, GSM data) or voice/speakerphone. These modem devices meet the size and power requirements of the mobile environment. Table 1-1 lists the available models.

The modem operates with PSTN telephone lines in the U.S./Japan/Canada and, optionally, worldwide. Optional cellular interface supports Japanese PDC (Personal Digital Cellular) and PHS (Personal Handyphone System) phones, GSM (Global System for Mobile Communications) phones, and cdmaOne (IS-95A/IS-95B) phones. Modem and cellular data protocol software is provided.

Conexant's SmartDAA technology (patent pending) eliminates the need for a costly line transformer, relays, and optoisolators typically used in discrete DAA (Data Access Arrangement) implementations. The SmartDAA architecture also simplifies product implementation by eliminating the need for country-specific board configurations enabling worldwide homologation of a single modem board design.

The SmartDAA system-powered DAA operates reliably without drawing power from the line, unlike line-powered DAAs which operate poorly when line current is insufficient due to long lines or poor line conditions. Enhanced features, such as monitoring of local extension status without going off-hook, are also supported.

Incorporating Conexant’s proprietary Digital Isolation Barrier (DIB) design (patent pending) and other innovative DAA features, such as Digital PBX line protection and reporting, the SmartDAA architecture simplifies application design, minimizes layout area, and reduces component cost.

For over a decade, Conexant has assisted customers with DAA technology and homologation. This expertise and system level approach has been leveraged in this product.

The SmartHSF device set, consisting of a CX11250 Host Side Device (HSD) in a 100-pin TQFP and a CX20463 SmartDAA Line Side Device (LSD) in a 32-pin TQFP, supports data/fax/TAM operation with host software-based digital signal processing and cell phone/DAA/telephone line interface functions.

The optional CX20437 Voice Codec (VC), in a 32-pin TQFP, supports voice/full-duplex speakerphone (FDSP) operation with interfaces to a microphone, speaker, and telephone handset/headset. Because some cellular interface signals and CX20437 VC interface signals share the same CX11250 HSD pins, speakerphone configuration does not support the cellular interface.

The major hardware signal interfaces are identified in Figure 1-1.

In V.90/K56flex data mode, the modem can receive data at speeds up to 56 kbps from a digitally connected V.90 or K56flexcompatible central site modem. In this mode, the modem can transmit data at speeds up to V.34 rates.

In V.34 data mode, the modem operates at line speeds up to 33.6 kbps. When applicable, error correction (V.42/MNP 2-4) and data compression (V.42 bis/MNP 5) maximize data transfer integrity and boost average data throughput. Non-errorcorrecting mode is also supported.

Fax Group 3 send and receive rates are supported up to 14.4 kbps with T.30 protocol.

V.80 synchronous access mode supports host-controlled communication protocols, e. g., H.324 video conferencing.

Audio recording and playback over the telephone line interface using A-Law, µ-Law, or linear coding at 8 kHz sample rate supports applications such as remote digital telephone answering machine (TAM).

This designer's guide describes the modem hardware capabilities and identifies the supporting commands. Commands and parameters are defined in the Commands Reference Manual (Doc. No. 100498, formerly identified as Doc. No. 1118).

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SmartHSF Mobile Modem Data Sheet

Table 1-1. SmartHSF Modem Models and Functions

Model/Order/Part Numbers Supported Hardware Functions (See Note 3)

Marketing Name Device Set

Order No.

SmartHSF/MC-PCI DS56-L155-111 11250-11 20463-12 — PCI US/J/C Y Y — —

SmartHSF/MS-PCI DS56-L155-121 11250-11 20463-12 20437-11 PCI US/J/C N Y — Y

SmartHSF/MWC-PCI DS56-L155-131 11250-11 20463-11 — PCI WW Y Y Y —

SmartHSF/MWS-PCI DS56-L155-141 11250-11 20463-11 20437-11 PCI WW N Y Y Y

NOTES:

1. Model options: C Cellular M Mobile S Voice/full-duplex speakerphone (FDSP) W Worldwide support including U.S./Japan/Canada

-PCI PCI Bus/Mini PCI interface

2. Supported functions (Y = Supported; – = Not supported): TAM Telephone answering machine (Voice playback and record through telephone line) FDSP Full-duplex speakerphone and voice playback and record through telephone line, handset, and mic/speaker PDC HS Personal Digital Cellular High Speed data PDC Packet Personal Digital Cellular Packet data PHS Personal Handyphone System CDMA Code Division Multiple Access GSM Global System for Mobile Communications data

3. Software configuration/functions determined by Device ID programmed into EEPROM (see Section 4.3).

4. For ordering purposes, the CX prefix may not be included in the part number for some devices. Also, the CX prefix may not appear in the part number as branded on

some devices.

Host Side

Device (HSD)

[100-Pin TQFP]

Part No.

Line Side

Device (LSD)

[32-Pin TQFP]

Part No.

Voice Codec

(VC)

[32-Pin TQFP]

Part No.

Host

Bus

DAA Type

PDC HS/

PDC Packet,

PHS,

CDMA, GSM

V.90/K56flex

Data,

V.17 Fax,

TAM

World-

wide

Voice/

FDSP

1-2

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OEM/Customer

Supplied Software

Conexant

Modem

Software

SmartHSF Mobile Modem Data Sheet

Conexant Modem Product

Conexant Modem Hardware Devices

OEM

Supplied

Hardware

Host Computer

Operating

System Software

and

Modem

Communication

Application

Software

Modem

Software

Drivers

PCI Bus/

MiniPCI

CX11250

Host Side Device (HSD)

100-Pin TQFP

SmartDAA

PCI Bus Interface

Interface

Figure 1-1. SmartHSF Modem Major Interfaces

Interface

Voice Codec

Interface

Cell

Phone

DAA Hardware

CX20463 SmartDAA

Line Side Device (LSD)

32-Pin TQFP

Digital

Isolation Barrier (DIB) Components

Rectifier

and Filter

Components

Line Side DIB

Interface

(LSDI)

Codec

Telephone

Line

Interface

CX20437

Voice Codec (VC)

32-Pin TQFP

(Optional)

Call Progress

Note: Speakerphone configuration does not support the cellular interface.

Telephone

Line Interface

Discrete

Components

Voice Relay,

HS Pickup

Detector

(Optional)

HS Hybrid

Components

(Optional)

(Mic/Speaker)

SPEAKER

Interface

(Optional)

Digital

Speaker

Circuit

(Optional)

PDC/ PDC Packet/ PHS/CDMA/

CDMA Packet/ GSM Interface

(Optional)

TELEPHONE

LINE

TIP RING

TELEPHONE

HANDSET

TIP RING

MIC SPEAKER

SOUNDUCER

PDC/PHS/ CDMA/ GSM PHONE

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1.2 FEATURES

1.2.1 General Modem Features

V.90 data modem with receive rates up to 56k bps and send rates up to V.34 rates

•

ITU-T V.90, K56flex, V.34 (33.6 kbps), V.32 bis, V.32, V.22 bis, V.22, V.23, and V.21; Bell 212A and 103

−

V.42 LAPM and MNP 2-4 error correction

−

V.42 bis and MNP 5 data compression

−

V.250 and V.251 commands

−

V.17 fax modem with send and receive rates up to 14.4 kbps

•

V.17, V.29, V.27 ter, and V.21 channel 2

−

EIA/TIA 578 Class 1 and T.31 Class 1.0 commands

−

Telephony/TAM

•

V.253 commands

−

8-bit µ-Law/A-Law coding (G.711)

−

8-bit/16-bit linear coding

−

8 kHz sample rate

−

Concurrent DTMF, ring, and Caller ID detection

−

V.80 synchronous access mode supports host-controlled communication protocols with H.324 interface support

•

V.8/V.8bis and V.251 commands

•

Cellular data hardware interface and software support (C models)

•

Protocol stacks for PDC high speed data, PDC packet data, PHS data, CDMA IS-95A/IS-95B data, and GSM data

−

API for customer-provided cellular data protocol stack

−

Full-duplex Speakerphone (FDSP) Mode (S models)

•

Microphone and speaker interface

−

Telephone handset/headset interface

−

Data/Fax/Voice call discrimination

•

Host software/MMX-based digital signal processing

•

Single configuration profile stored in host

•

Operates in U.S./Japan/Canada

•

Worldwide operation including U.S./Japan/Canada (W models)

•

Complies to TBR21 and other country requirements

−

Caller ID detection

−

System compatibility

•

Windows 95/98, Windows NT 4.0, Windows 2000, and Windows Millennium (Windows Me) operating systems

−

Microsoft'/Intel PC 99 Windows Hardware Designer’s Guide-compliant

−

Advanced Configuration and Power Interface (ACPI)

−

Unimodem/V compliant

−

Pentium 166 MHz MMX-compatible PC or greater

−

16 Mbyte RAM or more

−

Thin packages support low profile designs

•

CX11250 HSD: 100-pin TQFP (1.2 mm max. height)

−

CX20463 LSD: 32-pin TQFP (1.6 mm max. height)

−

CX20437 VC: 32-pin TQFP (1.6 mm max. height)

−

+3.3V operation with +5V tolerant digital inputs

•

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1.2.2 PCI Bus Host Interface Features

32-bit PCI Bus host interface

•

Meets PCI Local Bus Specification Rev. 2.2

−

PCI Bus Mastering interface

−

33 MHz PCI clock support

−

Supports Power Management

•

Meets PCI Bus Power Management Spec. Rev. 1.1

−

ACPI Power Management Registers

−

APM support

−

PME# support

−

Vaux/Vpci power switching support (-PCI model option)

−

VauxDET support

−

1.2.3 SmartDAA Features

Digital PBX line protection

•

System side powered DAA operates under poor line current supply conditions

•

Wake-on-ring

•

Ring detection

•

Line polarity reversal detection

•

Line current loss detection

•

Caller ID (CID) detect

•

Pulse dialing

•

Line-in-use detection – detects even while on-hook

•

Remote hang-up detect – for efficient call termination

•

Extension pickup detect

•

Call waiting detection

•

Meets worldwide DC VI Masks requirements (W models)

•

1.2.4 Applications

Laptop, notebook, and handheld computers

•

PCI Bus/Mini PCI embedded system boards

•

PCI Bus/Mini PCI plug-in cards

•

1.3 TECHNICAL OVERVIEW

1.3.1 General Description

Modem operation, including dialing, call progress, telephone line interface, telephone handset interface, PDC High Speed/GSM interface, voice/speakerphone interface, and host interface functions are supported and controlled through the V.250, V.251, and V.253-compatible command set.

The modem hardware connects to the host processor via a PCI/Mini PCI bus interface. The OEM adds a crystal circuit, EEPROM, DIB and LSD power rectifier and filter components, telephone line interface, optional telephone handset interface, optional PDC high speed/GSM interface, optional voice/speakerphone interface, and other supporting discrete components as required by the modem model and the application to complete the system.

1.3.2 Host Modem Software

The host modem software performs the following tasks:

1. General modem control, which includes command sets, fax Class 1, TAM, voice/speakerphone, error correction, data compression, GSM protocol stacks, PDC high speed data protocol stacks and phone drivers, and operating system interface functions.

2. Modem data pump signal processing, which includes data and facsimile modulation and demodulation, as well as voice sample formatting, is performed by the host processor using Conexant SoftK56 technology.

3. SmartDAA control, which includes HSD SmartDAA Interface control, LSD configuration and control, telephone line interface parameter control, and telephone line impedance control.

Configurations of the modem software are provided to support modem models listed in Table 1-1.

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1.3.3 Operating Modes

Data/Fax Modes

In V.90/K56flex data modem mode, the modem can receive data from a digital source using a V.90- or K56flex-compatible central site modem at line speeds up to 56 kbps. Asymmetrical data transmission supports sending data at line speeds up to V.34 rates. This mode can fallback to full-duplex V.34 mode, and to lower rates, as dictated by line conditions.

In V.34 data modem mode, the modem can operate in 2-wire, full-duplex, asynchronous modes at line rates up to 33.6 kbps. Data modem modes perform complete handshake and data rate negotiations. Using V.34 modulation to optimize modem configuration for line conditions, the modem can connect at the highest data rate that the channel can support from 33600 bps down to 2400 bps with automatic fallback. Automode operation in V.34 is provided in accordance with PN3320 and in V.32 bis in accordance with PN2330. All tone and pattern detection functions required by the applicable ITU or Bell standard are supported.

In V.32 bis data modem mode, the modem can operate at line speeds up to 14.4 kbps.

In fax modem mode, the modem can operate in 2-wire, half-duplex, synchronous modes and can support Group 3 facsimile send and receive speeds of 14400, 12000, 9600, 7200, 4800, and 2400 bps. Fax data transmission and reception performed by the modem are controlled and monitored through the EIA/TIA-578 Class 1 or T.31 Class 1.0 command interface. Full HDLC formatting, zero insertion/deletion, and CRC generation/checking are provided.

Synchronous Access Mode - Video Conferencing

V.80 Synchronous Access Mode (SAM) between the modem and the host/DTE is provided for host-controlled communication protocols, e.g., H.324 video conferencing applications.

Voice-call-first (VCF) before switching to a videophone call is also supported.

TAM Mode

TAM Mode features include 8-bit µ-Law, A-Law, and linear coding at 8 kHz sample rate. Full-duplex voice supports concurrent voice receive and transmit. Tone detection/generation, call discrimination, and concurrent DTMF detection are also supported. This mode supports applications such as digital TAM, voice annotation, and recording from and playback to the telephone line. ADPCM (4-bit IMA) coding is also supported to meet Microsoft WHQL logo requirements.

TAM Mode is supported by three submodes:

1. Online Voice Command Mode supports connection to the telephone line or, for S models, a microphone/speaker/handset/headset.

2. Voice Receive Mode supports recording voice or audio data input from the telephone line or, for S models, a microphone/handset/headset.

3. Voice Transmit Mode supports playback of voice or audio data to the telephone line or, for S models, a speaker/handset/headset.

Voice/Speakerphone Mode (S Models)

The S models include additional telephone handset, external microphone, and external speaker interfaces which support voice and full-duplex speakerphone (FDSP) operation.

Hands-free full-duplex telephone operation is supported in Speakerphone Mode under host control. Speakerphone Mode features an advanced proprietary speakerphone algorithm which supports full-duplex voice conversation with acoustic, line, and handset echo cancellation. Parameters are constantly adjusted to maintain stability with automatic fallback from fullduplex to pseudo-duplex operation. The speakerphone algorithm allows position independent placement of microphone and speaker. The host can separately control volume, muting, and AGC in microphone and speaker channels.

NOTE: Because some cellular interface signals and CX20437 VC interface signals share the same CX11250 HSD pins,

speakerphone configuration does not support the cellular interface.

Personal Digital Cellular High Speed Mode (C Models)

Personal Digital Cellular (PDC) High Speed Mode, implemented in host software, includes V.42 bis data compression and ARQ framing. A pass-through mode is also available to allow phone book data to be transferred to and from the PC at speeds up to 9600 bps (e.g., for editing on the PC). PDC High Speed Mode is enabled by the +WS46=20 and +CPDCM=2 AT commands and disabled by the +WS46=1 AT command.

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PDC Packet Mode (C Models)

PDC Packet Mode, implemented in host software as an optional mode of PDC, enables packet-based data communications at 28.8 kbps. PDC Packet Data Mode is enabled by the +WS46=20 and +CPDCM=3 AT commands and disabled by the +WS46=1 AT command.

PHS Mode (C Models)

PHS Data Mode is implemented in host software and supports a data rate of 32 kbps. PHS uses the PIAFS protocol stack. PHS Data Mode is enabled by the +WS46=26 AT command and disabled by the +WS46=1 AT command.

cdmaOne Data Mode IS95A (C Models)

cdmaOne Data Mode is implemented in host software and supports data rates of 9.6 kbps and 14.4 kbps. cdmaOne Data Mode is enabled by the +WS46=13 AT command and disabled by the +WS46=1 AT command.

cdmaOne Data Packet Mode IS95B (C Models)

cdmaOne Data Packet Mode is implemented in host software and supports a data rate of 64 kbps. cdmaOne Data Packet Mode is enabled by the +WS46=13 AT command and disabled by the +WS46=1 AT command.

GSM Mode (C Models)

GSM Mode, implemented in host software, supports data and fax transfer. The supported features include:

Data modem

•

V.21, V.23, V.22, V.22 bis, V.32

−

ISDN interoperability: 300 bps to 9600 bps

−

Transparent asynchronous mode up to 9600 bps

•

Non-transparent mode (RLP) up to 9600 bps

•

Fax modem send and receive rate up to 9600 bps

•

AT GSM commands (ETSI 07.07)

•

GSM direct connect

•

Driver interface for OEM-provided phone driver

•

Built-in parallel host (16550A UART) interface

•

GSM mode is enabled by the +WS46=12 AT command and disabled by the +WS46=1 AT command.

1.3.4 Reference Design

A Mini PCI Type IIIB data/fax/TAM reference design board is available to minimize application design time and costs.

The board is pretested to pass FCC Part 15, Part 68, and CTR 21 for immediate manufacturing.

A design package for the board is available in electronic form. The design package includes schematics, bill of materials (BOM), vendor parts list (VPL), board layout files in Gerber format, and complete documentation.

The design can also be used for the basis of a custom design by the OEM to accelerate design completion for rapid market entry.

1.4 HARDWARE DESCRIPTION

SmartDAA technology (patent pending) eliminates the need for a costly analog transformer, relays, and opto-isolators that are typically used in discrete DAA implementations. The programmable SmartDAA architecture simplifies product implementation in worldwide markets by eliminating the need for country-specific components.

1.4.1 CX11250 Host Side Device

The CX11250 Host Side Device (HSD), packaged in a 100-pin TQFP, includes a PCI/Mini PCI Interface and a SmartDAA Interface.

The PCI/Mini PCI interface connects directly to an embedded or external PCI/Mini PCI interface eliminating the need for additional external logic components.

The SmartDAA Interface communicates with, and supplies power and clock to, the LSD through the DIB.

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1.4.2 Digital Isolation Barrier

The OEM-supplied Digital Isolation Barrier (DIB) electrically DC isolates the HSD from the LSD and telephone line. The HSD is connected to a fixed digital ground and operates with standard CMOS logic levels. The LSD is connected to a floating ground and can tolerate high voltage input (compatible with telephone line and typical surge requirements).

The DIB transformer couples power and clock from the HSD to the LSD. (See Mobile Product Updates for qualified transformers.)

The DIB data channel supports bidirectional half-duplex serial transfer of data, control, and status information between the HSD and the LSD.

1.4.3 CX20463 SmartDAA Line Side Device

The CX20463 SmartDAA Line Side Device (LSD) includes a Line Side DIB Interface (LSDI), a coder/decoder (codec), and a Telephone Line Interface (TLI).

The LSDI communicates with, and receives power and clock from, the SmartDAA interface in the HSD through the DIB.

LSD power is received from the HSD PWRCLKP and PWRCLKN pins via the DIB through a half-wave rectifying diode and capacitive power filter circuit connected to the DIB transformer secondary winding. The CLK input is also coupled from the transformer secondary winding through a capacitor and a resistor in series.

Information is transferred between the LSD and the HSD through the DIB_P and DIB_N pins. These pins connect to the HSD DIB_DATAP and DIB_DATAN pins, respectively, through the DIB.

The TLI integrates DAA and direct telephone line interface functions and connects directly to the line TIP and RING pins, as well as to external line protection components.

Direct LSD connection to TIP and RING allows real-time measurement of telephone line parameters, such as the telephone central office (CO) battery voltage, individual telephone line (copper wire) resistance, and allows dynamic regulation of the offhook TIP and RING voltage and total current drawn from the central office (CO). This allows the modem to maintain compliance with U.S. and worldwide regulations and to actively control the DAA power dissipation.

1.4.4 CX20437 Voice Codec (S Models)

The optional CX20437 Voice Codec (VC), packaged in a 32-pin TQFP, supports voice/full-duplex speakerphone (FDSP) operation with interfaces to a microphone and speaker and to a telephone handset/headset.

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2. TECHNICAL SPECIFICATIONS

2.1 ESTABLISHING DATA MODEM CONNECTIONS

Dialing

DTMF Dialing.

complies with Bell Publication 47001.

Pulse Dialing.

Blind Dialing.

Modem Handshaking Protocol

If a tone is not detected within the time specified in the S7 register after the last digit is dialed, the modem aborts the call attempt.

Call Progress Tone Detection

Ringback, equipment busy, and progress tones can be detected in accordance with the applicable standard represented by the country profile currently in affect.

Answer Tone Detection

Answer tone can be detected over the frequency range of 2100 ± 40 Hz in ITU-T modes and 2225 ± 40 Hz in Bell modes.

DTMF dialing using DTMF tone pairs is supported in accordance with ITU-T Q.23. The transmit tone level

Pulse dialing is supported in accordance with EIA/TIA-496-A.

The modem can blind dial in the absence of a dial tone if enabled by the X0, X1, or X3 command.

Ring Detection

A ring signal can be detected from a TTL-compatible square wave input (frequency is country-dependent).

Billing Protection

When the modem goes off-hook to answer an incoming call, both transmission and reception of data are prevented for a period of time determined by country requirement to allow transmission of the billing signal.

Connection Speeds

Data modem line speed can be selected using the +MS command in accordance with V.25 ter. The +MS command selects modulation, enables/disables automode, and selects transmit and receive minimum and maximum line speeds.

Automode

Automode detection can be enabled by the +MS command to allow the modem to connect to a remote modem in accordance with V.25 ter.

2.2 DATA MODE

Data mode exists when a telephone line connection has been established between modems and all handshaking has been completed.

Speed Buffering (Normal Mode)

Speed buffering allows a DTE to send data to, and receive data from, a modem at a speed different than the line speed. The modem supports speed buffering at all line speeds.

DTE-to-Modem Flow Control

If the modem-to-line speed is less than the DTE-to-modem speed, the modem supports XOFF/XON or RTS/CTS flow control with the DTE to ensure data integrity.

Escape Sequence Detection

The “+++” escape sequence can be used to return control to the command mode from the data mode. Escape sequence detection is disabled by an S2 Register value greater than 127.

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GSTN Cleardown (V.90/K56flex, V.34, V.32 bis, V.32)

Upon receiving GSTN Cleardown from the remote modem in a non-error correcting mode, the modem cleanly terminates the call.

Fall Forward/Fallback (V.90/K56flex, V.34/V.32 bis/V.32)

During initial handshake, the modem will fallback to the optimal line connection within K56flex/V.34/V.32 bis/V.32 mode depending upon signal quality if automode is enabled by the +MS command.

When connected in V.90/K56flex/V.34/V.32 bis/V.32 mode, the modem will fall forward or fallback to the optimal line speed within the current modulation depending upon signal quality if fall forward/fallback is enabled by the %E1 command.

Retrain

The modem may lose synchronization with the received line signal under poor line conditions. If this occurs, retraining may be initiated to attempt recovery depending on the type of connection.

The modem initiates a retrain if line quality becomes unacceptable if enabled by the %E command. The modem continues to retrain until an acceptable connection is achieved, or until 30 seconds elapse resulting in line disconnect.

2.3 ERROR CORRECTION AND DATA COMPRESSION

V.42 Error Correction

V.42 supports two methods of error correction: LAPM and, as a fallback, MNP 4. The modem provides a detection and negotiation technique for determining and establishing the best method of error correction between two modems.

MNP 2-4 Error Correction

MNP 2-4 is a data link protocol that uses error correction algorithms to ensure data integrity. Supporting stream mode, the modem sends data frames in varying lengths depending on the amount of time between characters coming from the DTE.

V.42 bis Data Compression

V.42 bis data compression mode operates when a LAPM or MNP connection is established.

The V.42 bis data compression employs a “string learning” algorithm in which a string of characters from the DTE is encoded as a fixed length codeword. Two dictionaries, dynamically updated during normal operation, are used to store the strings.

MNP 5 Data Compression

MNP 5 data compression mode operates during an MNP connection.

In MNP 5, the modem increases its throughput by compressing data into tokens before transmitting it to the remote modem, and by decompressing encoded received data before sending it to the DTE.

2.4 FAX CLASS 1 OPERATION

Facsimile functions operate in response to Fax Class 1 commands when +FCLASS=1 or +FCLASS=1.0.

In the fax mode, the on-line behavior of the modem is different from the data (non-fax) mode. After dialing, modem operation is controlled by fax commands. Some AT commands are still valid but may operate differently than in data modem mode.

Calling tone is generated in accordance with T.30.

2.5 VOICE/TAM MODE

Voice and audio functions are supported by the Voice Mode. Voice Mode includes three submodes: Online Voice Command Mode, Voice Receive Mode, and Voice Transmit Mode.

2.5.1 Online Voice Command Mode

This mode results from the connection to the telephone line or a voice/audio I/O device (e.g., microphone or speaker) through the use of the +FCLASS=8 and +VLS commands. After mode entry, AT commands can be entered without aborting the connection.

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2.5.2 Voice Receive Mode

This mode is entered when the +VRX command is active in order to record voice or audio data input, typically from a microphone or the telephone line.

Received analog voice samples are converted to digital form and compressed for reading by the host. AT commands control the codec sample rate.

Received analog mono audio samples are converted to digital form and formatted into 8-bit µ-Law, A Law, linear, or 4-bit IMA ADPCM format for reading by the host. AT commands control the bit length and sampling rate. Concurrent DTMF/tone detection is available.

2.5.3 Voice Transmit Mode

This mode is entered when the +VTX command is active in order to playback voice or audio data, typically to a speaker or to the telephone line. Concurrent DTMF/tone detection is available. Digitized audio data is converted to analog form.

2.5.4 Speakerphone Modes

Speakerphone modes are selected in voice mode with the following commands:

Speakerphone ON/OFF (+VSP).

Microphone Gain (+VGM=<gain>).

Speaker Gain (+VGS=<gain>).

This command turns the Speakerphone function ON (+VSP = 1) or OFF (+VSP = 0).

This command sets the microphone gain of the Speakerphone function.

This command sets the speaker gain of the Speakerphone function.

2.6 FULL-DUPLEX SPEAKERPHONE (FDSP) MODE

The modem operates in FDSP mode when +FCLASS=8 and +VSP=1 (see 2.5.4).

In FDSP Mode, speech from a microphone or handset is converted to digital form, shaped, and output to the telephone line through the line interface circuit. Speech received from the telephone line is shaped, converted to analog form, and output to the speaker or handset. Shaping includes both acoustic and line echo cancellation.

2.7 CALLER ID

Caller ID can be enabled/disabled using the +VCID command. When enabled, caller ID information (date, time, caller code, and name) can be passed to the DTE in formatted or unformatted form. Inquiry support allows the current caller ID mode and mode capabilities of the modem to be retrieved from the modem. The retrieval of the Caller ID via an explicit AT query at a later time is essential for implementing a compliant “Instantly available PC” concept.

2.8 MULTIPLE COUNTRY SUPPORT (W MODELS)

W models support modem operation in various countries. The country choice is made via the AT+GCI command or country select applet from within those installed in Windows registry. The following capabilities are provided in addition to the data modem functions previously described. Country dependent parameters are included in the .INF file for customization by the OEM Programmable Parameters

2.8.1 OEM Programmable Parameters

The following parameters are programmable:

Dial tone detection levels and frequency ranges

•

DTMF dialing transmit output level, DTMF signal duration, and DTMF interdigit interval parameters

•

Pulse dialing parameters such as make/break times, set/clear times, and dial codes

•

Ring detection frequency range

•

Blind dialing disable/enable

•

The maximum, minimum, and default carrier transmit level values

•

Calling tone, generated in accordance with V.25, may also be disabled

•

Call progress frequency and tone cadence for busy, ringback, congested, dial tone 1, and dial tone 2

•

Answer tone detection period

•

On-hook/off-hook, make/break, and set/clear relay control parameters

•

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2.8.2 Blacklist Parameters

The modem can operate in accordance with requirements of individual countries to prevent misuse of the network by limiting repeated calls to the same number when previous call attempts have failed. Call failure can be detected for reasons such as no dial tone, number busy, no answer, no ringback detected, voice (rather than modem) detected, and key abort (dial attempt aborted by user). Actions resulting from such failures can include specification of minimum inter-call delay, extended delay between calls, and maximum numbers of retries before the number is permanently forbidden ("blacklisted"). Up to 20 such numbers may be tabulated. The blacklist parameters are programmable. The current blacklisted and delayed numbers can be queried via AT*B and AT*D commands, respectively.

2.9 DIAGNOSTICS

2.9.1 Commanded Tests

Diagnostics are performed in response to the &T1 command per V.54.

Analog Loopback (&T1 Command).

DTE.

Last Call Status Report (#UD).

Data from the local DTE is sent to the modem, which loops the data back to the local

This command reports the status of the last call.

2.10 LOW POWER SLEEP MODE

When not connected in data, fax, or speakerphone mode, the HSD is placed in a low power state, i.e., Idle Mode.

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3. HARDWARE INTERFACE

3.1 CX11250 HSD HARDWARE PINS AND SIGNALS

3.1.1 HSD Signal Interfaces

PCI Bus/Mini PCI Host Interface

The Host Side Device conforms to the PCI Local Bus Specification Version 2.2 and Mini PCI Specification Draft 1.0. It is a memory slave and a bus master for PC host memory accesses (burst transactions). Configuration is by PCI configuration protocol.

The PCI Bus/Mini PCI interface signals are:

Address and data

•

32 bidirectional Address/Data (AD[31-0]); bidirectional

−

4 Bus Command and Byte Enable (CBE [3:0]); bidirectional

−

Bidirectional Parity (PAR); bidirectional

−

Interface control

•

Cycle Frame (FRAME#); bidirectional

−

Initiator Ready (IRDY#); bidirectional

−

Target Ready (TRDY#); bidirectional

−

Stop (STOP#); bidirectional

−

Initialization Device Select (IDSEL); input

−

Device Select (DEVSEL#); bidirectional

−

Arbitration

•

Request (REQ#); output

−

Grant (GRANT#); input

−

Error reporting

•

Parity Error (PERR#); bidirectional

−

System Error (SERR#); bidirectional

−

Interrupt

•

Interrupt A (INTA#); output

−

System

•

Clock (PCICLK); input

−

Reset (PCIRST#); input

−

Clock Running (CLKRUN#); input

−

Power Management Event (PME#), output

−

Power Detection and Switching

Vaux Enable (VauxEN#); output

•

Vpci Enable (VpciEN#); output

•

Vpci Detect (VpciDET); input

•

Vaux Detect (VauxDET); input

•

Serial EEPROM Interface

A serial EEPROM is required to store the Device ID, Vendor ID, Subsystem ID, Subsystem Vendor ID, and Power Management parameters for the PCI Configuration Space Header.

The EEPROM must be 2048 (128 x 16) bits or larger and be rated at 1MHz (SROMCLK is 537.6 kHz). For example, the following EEPROMs or equivalent may be used: Microchip 93LC66B (256 x 16), 93LC56B (128 x 16), Atmel AT93C66 (256 x

16), AT93C56 (128 x 16). The EEPROM is programmable by the PC via the modem.

The EEPROM interface signals are:

Serial Data Input (SROMIN); input

•

Serial Data Output (SROMOUT); output

•

Clock (SROMCLK); output

•

Chip Select (SROMCS); output

•

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LSD Interface (Through DIB)

The DIB interface signals are:

Clock and Power Positive (PWRCLKP); output

•

Clock and Power Negative (PWRCLKN); output

•

Data Positive (DIB_DATAP); input/output

•

Data Negative (DIB_DATAN); input/output

•

VC Interface (S Models)

The VC interface signals are:

Modem Sleep (IASLEEP); output

•

Master Clock (M_CLK); output

•

Voice Serial Clock (V_SCLK); input

•

Voice Serial Control (V_CTRL); output

•

Voice Serial Frame Sync (V_STROBE); input

•

Voice Serial Transmit Data (V_TXSIN); output

•

Voice Serial Receive Data (V_RXOUT); input

•

Telephone Handset Interface (S Models)

The telephone handset interface signals are:

Voice Relay Control (VOICE#); output

•

Handset Pickup Detect (H_PICKUP); input

•

Call Progress Speaker Interface

The call progress speaker interface signal is:

Digital speaker output (DSPKOUT); output

•

DSPKOUT is a square wave output in Data/Fax mode used for call progress or carrier monitoring. This output can be optionally connected to a low-cost on-board speaker, e.g., a sounducer, or to an analog speaker circuit.

PDC/PDC packet Interface

Nine lines, defined by the installed cell phone driver software, are available to support the PDC/PDC packet cellular phone interface:

Panel 1

•

Panel 2

•

ADP

•

CELL_RXD

•

CELL_TXD

•

TCH_CLK

•

TCH_TX

•

TCH_RX

•

TCH_FRAME

•

PHS Interface

Eleven lines, defined by the installed cell phone driver software, are available to support the PHS cellular phone interface.

ASLP

•

PSLP

•

DFCK

•

Ready

•

DSDT

•

USDT

•

BITC

•

UDT

•

DDT

•

UFCK

•

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CDMA Interface

Twelve lines, defined by the installed cell phone driver software, are available to support the CDMA cellular phone interface:

Panel 1

•

Panel 2

•

Control RXD

•

Control TXD

•

BB (USART IN)

•

BA (USART OUT)

•

GSM Interface

Five lines, defined by the installed cell phone driver software, are available to support the GSM phone interface:

DA(IN)

•

RX-A

•

TX-A

•

TX-A

•

RX2-B USART

•

TX2-B USART

•

3.1.2 HSD Interface Signals, Pin Assignments, and Signal Definitions

The CX11250 HSD 100-pin TQFP hardware interface signals are shown by major interface in Figure 3-1, are shown by pin number in Figure 3-2, and are listed by pin number in Table 3-1.

The CX11250 HSD hardware interface signals are defined in Table 3-2.

Cell phone/telephone line interface signal assignments are listed in Table 3-3.

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PCI BUS/

MINI PCI

EEPROM

POWER DETECTION AND

SWITCHING CIRCUIT

+3.3V

27pF

28.224 MHz

27pF

CLKRUN#

C/BE0# C/BE1# C/BE2# C/BE3#

PCICLK

FRAME#

IDSEL

DEVSEL#

IRDY#

TRDY#

REQ#

INTA# STOP# PERR# SERR#

PCIRST#

VIO/+3.3V

SROMCS

SROMCLK

SROMIN

SROMOUT

VpciDET

VauxDET

VpciEN#

VauxEN#

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8

AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

PAR

GNT#

PME#

0.1uF

240K

SmartHSF Mobile Modem Data Sheet

SDXTAL1

SDXTAL2

CX11250

HOST SIDE DEVICE

(HSD)

100-PIN TQFP

CLKRUN#

AD0

AD1

65 64 62 61 60 59 56 55 54 53 52 51 50 49 37 35 34 33 32 30 29 28 24 23 21 20 19 17 16 15 57 48 38 25 10 39 27 42 40 41 46 13 12

8 43 44 45 14

9 22 26

76 79 78 77

71 80 69 79

7 18 31 47 58 68 94

11 36 63 89

72 73

AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0# CBE1# CBE2# CBE3# PCICLK FRAME# IDSEL DEVSEL# IRDY# TRDY# PAR REQ# GNT# INTA# STOP# PERR# SERR# PME# PCIRST# VIO VIO

SROMCS SROMCLK SROMIN SROMOUT

VpciDET VauxDET VpciEN# VauxEN#

PLLVDD

PLLVSS

LP_CLK

VDD VDD VDD VDD VDD VDD VDD

GND GND GND GND

SCANEN SCANMODE

V_CTRL/PANEL2 (GPIO13)

V_RXOUT/ASLP/CF (GPIO1)

V_TXSIN/PSLP/CJ (GPIO9)

V_STROBE/CC/DA(IN) (GPIO0)

VOICE#/ADP/RDY/CD(GPIO2)

SPKMUTE/CRXD/DSDT (GPIO8)

DSPKOUT/CTXD/USDT//TXA (GPIO11)

TCH_TX/UDT/TXA (GPIO5)

TCH_RX/DDT/ BB/RX2B (GPIO4)

TCH_FRAME/UFCK/BA/TX2B (GPIO3)

V_CTRL/PANEL2 (GPIO13)

V_RXOUT/ASLP/CF (GPIO1)

V_TXSIN/PSLP/CJ (GPIO9)

V_STROBE/CC/DA(IN) (GPIO0)

VOICE#/ADP/RDY/CD(GPIO2)

SPKMUTE/CRXD/DSDT (GPIO8)

DSPKOUT/CTXD/USDT//TXA (GPIO11)

TCH_TX/UDT/TXA (GPIO5)

TTCH_RX/DDT/ BB/RX2B (GPIO4)

TCH_FRAME/UFCK/BA/TX2B (GPIO3)

V_CTRL/PANEL2 (GPIO13)

V_RXOUT/ASLP/CF (GPIO1)

V_TXSIN/PSLP/CJ (GPIO9)

V_STROBE/CC/DA(IN) (GPIO0)

VOICE#/ADP/RDY/CD(GPIO2)

SPKMUTE/CRXD/DSDT (GPIO8)

DSPKOUT/CTXD/USDT//TXA (GPIO11)

TCH_TX/UDT/TXA (GPIO5)

TCH_RX/DDT/ BB/RX2B (GPIO4)

TCH_FRAME/UFCK/BA/TX2B (GPIO3)

V_CTRL/PANEL2 (GPIO13)

V_RXOUT/ASLP/CF (GPIO1)

V_TXSIN/PSLP/CJ (GPIO9)

V_STROBE/CC/DA(IN) (GPIO0)

VOICE#/ADP/RDY/CD(GPIO2)

SPKMUTE/CRXD/DSDT (GPIO8)

DSPKOUT/CTXD/USDT//TXA (GPIO11)

TCH_TX/UDT/TXA (GPIO5)

TCH_RX/DDT/ BB/RX2B (GPIO4)

TCH_FRAME/UFCK/BA/TX2B (GPIO3)

V_CTRL/PANEL2 (GPIO13)

V_RXOUT/ASLP/CF (GPIO1)

V_TXSIN/PSLP/CJ (GPIO9)

V_STROBE/CC/DA(IN) (GPIO0)

VOICE#/ADP/RDY/CD(GPIO2)

SPKMUTE/CRXD/DSDT (GPIO8)

DSPKOUT/CTXD/USDT//TXA (GPIO11)

TCH_TX/UDT/TXA (GPIO5)

TCH_RX/DDT/ BB/RX2B (GPIO4)

TCH_FRAME/UFCK/BA/TX2B (GPIO3)

PWRCLKP

PWRCLKN

DIB_DATAP

DIB_DATAN

DRESET# (GPOL0)

M_CLK/PANEL1 (GPIO12)

V_SCLK/CB (GPIO7)

IASLEEP/DFCK/CE/RXA Binary Audio In (GPIO10)

TCH_CLK/BITC (GPIO6)

DRESET# (GPOL0)

M_CLK/PANEL1 (GPIO12)

V_SCLK/CB (GPIO7)

IASLEEP/DFCK/CE/RXA Binary Audio In (GPIO10)

TCH_CLK/BITC (GPIO6)

DRESET# (GPOL0)

M_CLK/PANEL1 (GPIO12)

V_SCLK/CB (GPIO7)

IASLEEP/DFCK/CE/RXA Binary Audio In (GPIO10)

TCH_CLK/BITC (GPIO6)

DRESET# (GPOL0)

M_CLK/PANEL1 (GPIO12)

V_SCLK/CB (GPIO7)

IASLEEP/DFCK/CE/RXA Binary Audio In (GPIO10)

TCH_CLK/BITC (GPIO6)

DRESET# (GPOL0)

M_CLK/PANEL1 (GPIO12)

V_SCLK/CB (GPIO7)

IASLEEP/DFCK/CE/RXA Binary Audio In (GPIO10)

TCH_CLK/BITC (GPIO6)

95 5 6 3 2 4 1 96 88 100 99 87 81 82 83 85

PWRCLKP

PWRCLKN

DIB_DATAP

DIB_DATAN

POR M_CLKIN M_CNTRLSIN M_SCK M_RXOUT M_TXSIN M_STROBE SLEEP Binary Audio Source VOICE RELAY MUTE SPEAKER

CALL PROG DIGITAL AUDIO NC NC NC NC

Panel 1

Panel 2

NC NC NC NC NC NC

ADP

CELL_RXD

CELL_TXD

TCH_CLK

TCH_TX

TCH_RX

TCH_FRAME

NC NC NC NC

ASLP

PSLP

DFCK

RDY

DSDT

USDT

BITC

UDT

DDT

UFCK

Panel 1

Panel 2

Control RXD

Control TXD

NC NC

BB (USART IN)

BA (USART OUT)

NC NC NC NC NC NC

DA(IN)

RX-A

NC NC NC

TX-A

RX2-B USART

TX2-B USART

DIGITAL ISOLATION BARRIER (DIB)

TELEPHONE LINE

INTERFACE

CONFIGURATION

VOICE CODEC (VC) 20437 32-PIN TQFP

SPEAKER CIRCUIT

PDC/PDC PACKET

INTERFACE

CONFIGURATION

PDC PHONE

PHS

INTERFACE

CONFIGURATION

PHS PHONE

CDMA/CDMA PACKET

INTERFACE

CONFIGURATION

CDMA PHONE

GSM

INTERFACE

CONFIGURATION

GSM PHONE

100553_F3-1_ HIS 11250 100T

3-4

Figure 3-1. CX11250 HSD Hardware Interface Signals

Conexant

100553B

Page 23

SmartHSF Mobile Modem Data Sheet

SPKMUTE/CRXD/DSDT (GPIO8)

DRESET# (GPOL0)

PLLVSS

VOICE#/ADP/RDY/CD (GPIO2)

VDD

PLLVDD

IASLEEP/DFCK/CE/RXA

PWRCLKN

PWRCLKP

DIB_DATAN

GND

DIB_DATAP

TCH_FRAME/UFCK/BA/TX2B (GPIO3)

Bin Audio In (GPIO10)

DSPKOUT/CTXD/USDT (GPIO11)

CLKRUN#

LP_CLK

TCH_RX/DDT/BB/RX2B (GPIO4)

TCH_TX/UDT/TXA(GPIO5)

TCH_CLK/BITC (GPIO6)

VauxDET

SROMCLK

SROMIN

SROMOUT

SROMCS

V_STROBE/CC/DA(IN) (GPIO0)

V_RXOUT/ASLP/CF (GPIO1)

V_SCLK/CB (GPIO2)

V_TXSIN/PSLP/CJ (GPIO9)

M_CLK/PANEL1 (GPIO12)

V_CTRL/PANEL2 (GPIO13)

VDD

INTA#

PCIRST#

PCICLK

GND

GNT#

REQ#

PME#

AD31

AD30

AD29

VDD

AD28

AD27

AD26

VIO

AD25

AD24

CBE3#

100

VIO

IDSEL

AD23

AD22

AD21

VDD

AD20

AD19

CX11250

GND

AD16

AD18

AD17

CBE2#

IRDY#

FRAME#

TRDY#

DEVSEL#

STOP#

PERR#

SERR#

PAR

VDD

AD15

CBE1#

AD14

SDXTAL2

SDXTAL1

SCANMODE

SCANEN

VPCIDET

VauxEN#

VpciEN#

VDD

AD0

AD1

AD2

AD3

GND

AD4

AD5

AD6

AD7

VDD

CBE0#

AD8

AD9

AD10

AD11

AD12

AD13

100553B

Figure 3-2. CX11250 HSD 100-Pin TQFP Pin Signals

Conexant

100553_F3-2_ PO-11250-100TQFP

3-5

Page 24

SmartHSF Mobile Modem Data Sheet

Table 3-1. CX11250 HSD 100-Pin TQFP Pin Signals

Pin Signal Label I/O Type Interface Pin Signal Label I/O Type Interface

1 V_STROBE/

CC/ DA(IN) (GPIO0)

2V_RXOUT/

ASLP/ CF (GPIO1)

3V_SCLK/

CB (GPIO2)

4V_TXSIN/

PSLP/ CJ (GPIO9)

5 M_CLK/

PANEL1 (GPIO12)

6 V_CTRL/

PANEL2

(GPIO13) 7 VDD PWR +3.3V 57 CBE0# I/Opts PCI Bus: CBE0# 8 INTA# Opod PCI Bus: INTA# 58 VDD PWR +3.3V 9 PCIRST# Ip PCI Bus: PCIRST# 59 AD7 I/Opts PCI Bus: AD7 10 PCICLK Ip PCI Bus: PCICLK 60 AD6 I/Opts PCI Bus: AD6 11 GND GND GND 61 AD5 I/Opts PCI Bus: AD5 12 GNT# Ipts PCI Bus: GNT# 62 AD4 I/Opts PCI Bus: AD4 13 REQ# Opts PCI Bus: REQ# 63 GND GND GND 14 PME# Opod PCI Bus: PME# 64 AD3 I/Opts PCI Bus: AD3 15 AD31 I/Opts PCI Bus: AD31 65 AD2 I/Opts PCI Bus: AD2 16 AD30 I/Opts PCI Bus: AD30 66 AD1 I/Opts PCI Bus: AD1 17 AD29 I/Opts PCI Bus: AD29 67 AD0 I/Opts PCI Bus: AD0 18 VDD PWR +3.3V 68 VDD PWR +3.3V 19 AD28 I/Opts PCI Bus: AD28 69 VpciEN# Ot2 Pwr Detection/Switching Ckt

Itpd Telephone Line: VC M_STROBE

CDMA Phone: CC GSM Phone: DA(IN)

Itk Telephone Line: VC M_RXOUT

PHS Phone: ASLP CDMA Phone: CF

Itpd Telephone Line: VC M_SCK

CDMA Phone: CB

Ot2 Telephone Line: VC M_TXSIN

PHS Phone: PSLP CDMA Phone: CJ

Ot2 VC Telephone Line: VC M_CLKIN

PDC Phone: Panel 1 CDMA Phone: Panel 1

Ot2 Telephone Line: VC M_CNTRLSIN

PDC Phone: Panel 2 CDMA Phone: Panel 2

51 AD13 I/Opts PCI Bus: AD13

52 AD12 I/Opts PCI Bus: AD12

53 AD11 I/Opts PCI Bus: AD11

54 AD10 I/Opts PCI Bus: AD10

55 AD9 I/Opts PCI Bus: AD9

56 AD8 I/Opts PCI Bus: AD8

20 AD27 I/Opts PCI Bus: AD27 70 VauxEN# Ot2 Pwr Detection/Switching Ckt 21 AD26 I/Opts PCI Bus: AD26 71 VpciDET Itpd Pwr Detection/Switching Ckt 22 VIO PWR PCI Bus: VI/O or +3.3V 72 SCANEN Itpd GND 23 AD25 I/Opts PCI Bus: AD25 73 SCANMODE Itpd GND 24 AD24 I/Opts PCI Bus: AD24 74 SDXTAL1 Ix Crystal or Clock Circuit 25 CBE3# I/Opts PCI Bus: CBE3# 75 SDXTAL2 Ox Crystal or NC (if SDXTAL1 connected

26 VIO PWR PCI Bus: VI/O or +3.3V 76 SROMCS Ot2 SROM: Chip Select (CS) 27 IDSEL Ip PCI Bus: IDSEL 77 SROMOUT Ot2 SROM: Data In (DI) 28 AD23 I/Opts PCI Bus: AD23 78 SROMIN Itpu SROM: Data Out (DO) 29 AD22 I/Opts PCI Bus: AD22 79 SROMCLK Ot2 SROM: Clock (SK) 30 AD21 I/Opts PCI Bus: AD21 80 VauxDET Itpd Pwr Detection/Switching Ckt 31 VDD PWR +3.3V 81 TCH_CLK/

BITC (GPIO6)

32 AD20 I/Opts PCI Bus: AD20 82 TCH_TX/

UDT/ TXA (GPIO5)

33 AD19 I/Opts PCI Bus: AD19 83 TCH_RX/

DDT/ BB/ RX2B (GPIO4)

34 AD18 I/Opts PCI Bus: AD18 84 LP_CLK RC

Itpu/Ot12 PDC Phone: TCH_CLK

Itpu/Ot12 PDC Phone: TCH_TX K

Itpu/Ot12 PDC Phone: TCH_RX

to Clock Circuit)

PHS Phone: BITC

PHS Phone: UDT GSM Phone: TXA

PHS Phone: DDT CDMA Phone: BB_RXD GSM Phone: RX2-B

+3.3V through 240 K

Ω

3-6

Conexant

100553B

Page 25

SmartHSF Mobile Modem Data Sheet

Table 3-1. CX11250 HSD 100-Pin TQFP Pin Signals (Continued)

Pin Signal Label I/O Type Interface Pin Signal Label I/O Type Interface

35 AD17 I/Opts PCI Bus: AD17 85 TCH_FRAME/

UFCK/ BA/ TX2B

(GPIO3) 36 GND GND GND 86 CLKRUN# I/Opod PCI Bus: CLKRUN# 37 AD16 I/Opts PCI Bus: AD16 87 DSPKOUT/

CTXD/

USDT/

TXA

(GPIO11) 38 CBE2# I/Opts PCI Bus: CBE2# 88 Bin Audio In

(GPIO10) 39 FRAME# I/Opsts PCI Bus: FRAME# 89 GND GND GND 40 IRDY# I/Opsts PCI Bus: IRDY# 90 DIB_DATAN Idd/Odd DIB: Data Negative Channel 41 TRDY# I/Opsts PCI Bus: TRDY# 91 DIB_DATAP Idd/Odd DIB: Data Positive Channel 42 DEVSEL# I/Opsts PCI Bus: DEVSEL# 92 PW RCLKP Odpc DIB: Transformer primary winding

43 STOP# I/Opsts PCI Bus: STOP# 93 PWRCLKN Odpc DIB: Transformer primary winding

44 PERR# I/Opsts PCI Bus: PERR# 94 VDD PWR +3.3V 45 SERR# I/Opod PCI Bus: SERR# 95 DRESET#

(GPOL0) 46 PAR I/Opts PCI Bus: PAR 96 IASLEEP/

DFCK/

CE/

RXA 47 VDD PWR +3.3V 97 PLLVDD PWR 48 CBE1# I/Opts PCI Bus: CBE1# 98 PLLVSS GND GND 49 AD15 I/Opts PCI Bus: AD15 99 SPKMUTE/

CRXD/

DSDT (GPIO8)

50 AD14 I/Opts PCI Bus: AD14 100 VOICE#/ADP/

RDY/CD (GPIO2)

Itpu/Ot12 PDC Phone: TCH_FRAME

PHS Phone: UFCK CDMA Phone: BA_TXD GSM Phone: TX2-B

Ot12 Telephone Line: Spkr circuit

PDC Phone: CELL_TXD PHS Phone: USDT CDMA Phone: Control TXD GSM: TX-A

Itpu Line Interface: Binary Audio Source

non-dotted terminal

dotted terminal

Ot2 VC: POR

Ot2 Telephone Line: VC SLEEP

PHS Phone: DFCK CDMA Phone: CE GSM Phone: RX-A

+3.3V and to GND through 0.1 µF

It/Ot12 Telephone Line: Spkr Circuit (Out);

Vaux Mode Power Select (In) PDC Phone: CELL_RXD PHS Phone: DSDT CDMA Phone: Control RXD

Ot12 Telephone Line: Voice Relay Control

PDC Phone: ADP PHS Phone: RDY CDMA Phone: CD

100553B

Conexant

3-7

Page 26

SmartHSF Mobile Modem Data Sheet

NOTES:

1. I/O Types

I/Opod Digital input/output, PCI, open drain (PCI type = o/d)

I/Opsts Digital input/output, PCI, sustained three-state (PCI type = s/t/s)

I/Opts Digital input/output, PCI, three-state (PCI type = t/s)

Idd input, DIB, data channel

Ip Digital input, PCI, totem pole (PCI type = in)

Ipts Digital input, PCI, (PCI type = t/s)

It Digital input, TTL-compatible

Itk Digital input, TTL-compatible, internal keeper

Itpd Digital input, TTL-compatible, internal 75k ± 25k Ω pull-down

Itpu Digital input, TTL-compatible, internal 75k ± 25k Ω pull-up It/Ot2 Digital input, TTL-compatible/digital output, TTL-compatible, 2 mA, Z

It/Ot12 Digital input, TTL-compatible/digital output, TTL-compatible, 12 mA, Z

Ix Crystal/clock input

Odpc Output, DIB power and clock channel

Odd Output, DIB data channel

Ood Digital output, open drain

Opod Digital output, PCI, open drain (PCI type =o/d)

Opts Digital output, PCI, three-state (PCI type = t/s) Ot2 Digital output, TTL-compatible, 2 mA, Z

Ot12 Digital output, TTL-compatible, 12 mA, Z

Ox Crystal output

2. Interface Legend:

NC No internal pin connection DIB Digital Isolation Barrier VC Voice Codec

3. All references to PCI Bus also apply to Mini PCI unless otherwise specified.

INTERNAL

= 120

= 32

= 120

INTERNAL

Ω

= 32

Ω

3-8

Conexant

100553B

Page 27

SmartHSF Mobile Modem Data Sheet

Table 3-2. CX11250 HSD Pin Signal Definitions

Label Pin I/O I/O Type Signal Name/Description

SYSTEM

SDXTAL1 SDXTAL2

VDD 7, 18, 31, 47,

GND 11, 36, 63, 89 G GND

VIO 22, 26 P PWR

LP_CLK 84 RC

PLLVDD 97 P PWR

PLLGND 98 G GND

SCANEN 72 I Itpd

SCANMODE 73 I Itpd

CLKRUN# 86 I I/Opod,

VpciDET 71 I Itpd

VauxDET 80 I Itpd

VpciEN# 69 O Ot2

VauxEN# 70 O Ot2

SROMCLK 79 O Ot2

SROMCS 76 O Ot2

SROMIN 78 I Itpu

SROMOUT 77 O Ot2

74 75

58, 68, 94

I O

PPWR

Ix Ox

(o/d)

Crystal/Clock In and Crystal Out.

crystal or clock circuit. Connect SDXTAL2 to the 28.224000 MHz crystal circuit or leave open if SDXTAL1 is connected to a clock circuit.

Digital Supply Voltage.

Digital Ground.

I/O Signaling Voltage Reference.

internally for PCI clamping.

Low Power Clock RC Circuit.

Digital Supply Voltage.

Digital Ground.

Scan Enable.

Scan Mode

Clock Running.

and an open drain output used to request starting or speeding up CLK. Connect to GND for PCI Bus designs. Connect to CLKRUN# pin for Mini PCI designs.

POWER DETECTION

Vpci Detect.

to be ignored. Connect this pin to the PCI Bus +5V pins for PCI Bus designs or to PCI 3.3V for Mini PCI designs. VpciDET is deasserted when the PCI Bus enters the B3 state.

This pin may alternatively be directly driven in embedded designs by using a logical signal, either +5V or +3.3V level, to indicate when the PCI Bus is in a B3 state. Driving this pin low synchronously to the PCI clock or when the PCI clock is stopped also allows the HSD to be put into a very low power mode. Using this method, if modem operation is not required, modem power consumption can be reduced even while the PCI Bus is in power state B0.

Vaux Detect.

to PCI Bus: Vaux. At device power on (POR), if D3_Cold bit in the EEPROM is a 1, PMC[15] is set to a 1 if VauxDET is high or PMC[15] is cleared to a 0 if VauxDET is low.

Vpci Enable.

that switch between Vaux and Vpci for different power states and for retail designs where the target PC may or may not support Vaux.

Vaux Enable.

that switch between Vaux and Vpci for different power states and for retail designs where the target PC may or may not support Vaux.

SERIAL EEPROM INTERFACE

Serial ROM Shift Clock.

Serial ROM Chip Select.

Serial ROM Device Status and Data Out.

through 1 kΩ if using a +5V EEPROM.

Serial ROM Instruction, Address, and Data In.

Connect to GND.

. Connect to GND.

The VpciDET input indicates when PCI cycles and PCIRST# are

Active high input used to detect the presence of Vaux. Connect

Active low output used to enable Vpci FET. For use in designs

Active low output used to enable Vaux FET. For use in designs

Connect to +3.3V.

Connect to digital ground.

Connect to +3.3V and to GND through 0.1 µF.

Connect to digital ground.

CLKRUN# is an input used to determine the status of CLK

Connect to SROM SK input (frequency: 537.6 kHz).

Connect to SROM CS input.

Connect SDXTAL1 to a 28.224000 MHz

Connect to PCI Bus VI/O or +3.3V. Used

Connect to +3.3V through 240 KΩ.

Connect to SROM DO output,

Connect to SROM DI input.

100553B

Conexant

3-9

Page 28

SmartHSF Mobile Modem Data Sheet

Table 3-2. CX11250 HSD Pin Signal Definitions (Continued)

Label Pin I/O I/O Type Signal Name/Description

PCI BUS INTERFACE

PCICLK 10 I Ip

PCIRST# 9 I Ip

AD[31:0] 15-17, 19-21,

CBE0# CBE1# CBE2# CBE3#

PAR 46 I/O I/Opts

FRAME# 39 I/O I/Opsts

IRDY# 40 I/O I/Opsts

TRDY# 41 I/O I/Opsts

STOP# 43 I/O I/Opsts

IDSEL 27 I Ip

DEVSEL# 42 I/O I/Opsts

REQ# 13 O Opts

GNT# 12 I Ipts

PERR# 44 I/O I/Opsts

SERR# 45 O Opod

INTA# 8 O Opod

PME# 14 O Opod

STSCHG# 14 O Opod

23-24, 28-30, 32-35, 37, 4956, 59-62, 6467

57 48 38 25

I/O I/Opts

(in)

(t/s)

(s/t/s)

(in)

(s/t/s)

(t/s)

(s/t/s)

(o/d)

PCI Bus Clock.

transactions on PCI. Connect to PCI Bus: CLK.

PCI Bus Reset.

sequencers, and signals to a consistent reset state. Connect to PCI Bus: RST#.

Multiplexed Address and Data.

same PCI pins. Connect to PCI Bus: AD[31-0].

Bus Command and Bus Enable.

multiplexed on the same PCI pins. During the address phase of a transaction, CBE[3:0]# define the bus command. During the data phase, CBE[3:0]# are used as Byte Enables. Connect to PCI Bus: CBE[3:0]#.

Parity is even parity across AD[31:00] and CBE[3:0]#. The master

Parity.

drives PAR for address and write data phases; the Bus Interface drives PAR for read data phases. Connect to PCI Bus: PAR.

Cycle Frame.

beginning and duration of an access. Connect to PCI Bus: FRAME#.

Initiator Ready.

ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. Connect to PCI Bus: IRDY#.

Target Ready.

complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. Connect to PCI Bus: TRDY#.

STOP# is asserted to indicate the Bus Interface is requesting the master

Stop.

to stop the current transaction. Connect to PCI Bus: STOP#.

Initialization Device.

read and write transactions. Connect to PCI Bus: IDSEL.

Device Select.

has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. Connect to PCI Bus: DEVSEL#.

t. REQ# is used to indicate to the arbiter that this agent desires use of

Reques

the bus. Connect to PCI Bus: REQ#.

GNT# is used to indicate to the agent that access to the bus has been

Grant.

granted. Connect to PCI Bus: GNT#.

Parity Error.

PCI Bus: PERR#.

System Error.

parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Connect to PCI Bus: SERR#.

Interrupt A.

Connect to PCI Bus: INTA#.

Power Management Event.

(selected by the PME DRV bit in the EEPROM) asserted when a valid ring signal is detected and the PME_En bit of the PMCSR is a 1. This signal should be used only if the target PCI Bus supports power management wake-up event. Connect to the PCI Bus: PME#.

Status Changed.

RRdy/-Bsy bit (PRR1) in the Pin Replacement Register (PRR) and to the setting of the ReqAttn bit (ESR4) in the Extended Status Register (ESR).

The PCICLK (PCI Bus CLK signal) input provides timing for all

Active low input asserted to initialize PCI-specific registers,

Address and Data are multiplexed on the

Bus Command and Byte Enables are

FRAME# is driven by the current master to indicate the

IRDY# is used to indicate the initiating agent’s (bus master’s)

TRDY# is used to indicate s the Bus Interface’s ability to

IDSEL input is used as a chip select during configuration

When actively driven, DEVSEL# indicates the driving device

PERR# is used for the reporting of data parity errors. Connect to

SERR# is an open drain output asserted to report address

INTA# is an open drain output asserted to request an interrupt.

Active low open drain or active high TTL output

Active low output asserted to alert the host to changes in the

3-10

Conexant

100553B

Page 29

SmartHSF Mobile Modem Data Sheet

Table 3-2. CX11250 HSD Pin Signal Definitions (Continued)

Label Pin I/O I/O Type Signal Name/Description

DIB INTERFACE

PWRCLKP 92 O Odpc

PWRCLKN 93 O Odpc

DIB_DATAP 91 I/O Idd/Odd

DIB_DATAN 90 I/O Idd/Odd

TELEPHONE LINE (DAA)/AUDIO INTERFACE

DRESET# (GPOL0)

M_CLK/PANEL1 (GPIO12)

V_CTRL/PANEL 2 (GPIO13)

V_SCLK/CB (GPIO2)

V_RXOUT/ASLP/ CF (GPIO1)

V_TXSIN/PSLP/ CJ (GPIO9)

V_STROBE/CC/ DA(IN) (GPIO0)

IASLEEP/ DFCK/CE/RXA

VOICE#/ADP/ RDY/CD (GPIO2)

SPKMUTE/ CRXD/DSDT/ (GPIO8)

DSPKOUT/ CTXD/ USDT/CNTL_TX D (GPIO11)

Bin Audio In (GPIO10)

95 O Ot2

5OOt2

6OOt2

3 I Itpd

2IIt

4OOt2

1 I Itpd

96 O Ot2

100 O Ot12

99 I/O It/Ot12

87 O Ot12

88 I Itpu

Clock and Power Positive.

DIB transformer primary winding non-dotted terminal.

Clock and Power Negative.

DIB transformer primary winding dotted terminal.

Data Positive.

and LSD. Connect to LSD through DIB data positive channel components.

Data Negative.

and LSD. Connect to LSD through DIB data negative channel components.

Modem Reset.

Master Clock Output

Voice Control Output.

Voice Serial Clock input.

Voice Serial Receive Data Input.

Voice Serial Transmit Data Output.

Voice Serial Frame Sync Input.

Modem Sleep.

Voice Relay Control.

open voice relay. The polarity of this output is configurable.

Speaker Mute/Vaux Mode Power Select.

turn off (mute) the speaker during normal operation. Applicable to S models only.

Upon device reset, this pin is temporarily an input and is sampled. If sampled high and VauxDET is high, VpciEN# will be asserted when the device is in D0. If sampled low (e.g., SPKMUTE signal is pulled down to GND through 10k Ω) and VauxDET is high, VauxEN# will be asserted when the device is in D0. VauxEN# is always asserted when VauxDET is high in D3 with PME enabled. Either VauxEN# or VpciEN#, but not both, can be asserted at the same time.

Call Progress (Digital Speaker) Output.

the received analog input signal digitized to TTL high or low level by an internal comparator. This signal is used for call progress or carrier monitoring. This output can be optionally connected to a low-cost on-board speaker, e.g., a sounducer, or to an analog speaker circuit.

Binary Audio Input.

Transfers data, control, and status information between HSD

Connect to VC POR pin.

Connect to VC SLEEP pin.

Provides clock and power to the LSD. Connect to

. Connect to VC M_CLKIN pin.

Connect to VC M_CNTRLSIN pin.

Connect to VC M_SCK pin.

Connect to VC M_RXOUT pin.

Connect to VC M_TXSIN pin.

Connect to VC M_STROBE pin.

Output (typically active low) used to control the normally

Binary audio source.

Output (typically active low) used to

The DSPKOUT digital output reflects

100553B

Conexant

3-11

Page 30

SmartHSF Mobile Modem Data Sheet

Table 3-2. CX11250 HSD Pin Signal Definitions (Continued)

Label Pin I/O I/O Type Signal Name/Description

PDC/PDC PACKET PHONE INTERFACE

M_CLK/PANEL1 (GPIO12)

V_CTRL/PANEL 2 (GPIO13)

VOICE#/ADP/ RDY/CD (GPIO2)

SPKMUTE/ CRXD/ DSDT/ (GPIO8)

DSPKOUT/ CTXD/USDT/ (GPIO11)

TCH_CLK/BITC (GPIO6)

TCH_TX/UDT/ TXA(GPIO5)

TCH_RX/DDT/ BB_RXD/RX2B (GPIO4)

TCH_FRAME/ UFCK/BA_TXD/ TX2B (GPIO3)

V_RXOUT/ASLP/ CF (GPIO1)

V_TXSIN/PSLP/ CJ (GPIO9)

IASLEEP/DFCK/ CE/RXA

VOICE#/ADP/ RDY/CD(GPIO2)

SPKMUTE/ CRXD/DSDT (GPIO8)

DSPKOUT/ CTXD/USDT (GPIO11)

TCH_CLK/ BITC (GPIO6)

TCH_TX/UDT/ TXA (GPIO5)

TCH_RX/DDT/ BB_RXD/RX2B (GPIO4)

TCH_FRAME/ UFCK/BA_TXD/ TX2B (GPIO3)

5 O Itpu/Ot12

6 O Itpu/Ot12

100 O Ot12

99 I It/Ot12

87 O Ot12

81 I Itpu/Ot12

82 O Itpu/Ot12

83 I Itpu/Ot12

85 I Itpu/Ot12

2IIt

4 O It/Ot2

96 I It/Ot2

100 O Ot12

99 I It/Ot12

87 O Ot12

81 I Itpu/Ot12

82 O Itpu/Ot12

83 I Itpu/Ot12

85 I Itpu/Ot12

Panel 1.

Panel 2.

ADP.

CELL_RXD.

CELL_TXD.

TCH_CLK.

TCH_TX.

TCH_RX.

TCH_FRAME.

PHS PHONE INTERFACE

ASLP.

PSLP.

DFCK.

Ready.

DSDT.

USDT.

BITC.

UDT.

DDT.

UFCK.

Defined by the PDC firmware driver.

Defined by the PHS firmware driver.

3-12

Conexant

100553B

Page 31

SmartHSF Mobile Modem Data Sheet

Table 3-2. CX11250 HSD Pin Signal Definitions (Continued)

Label Pin I/O I/O Type Signal Name/Description

CDMA PHONE INTERFACE

M_CLK/PANEL1 (GPIO12)

V_CTRL/PANEL 2 (GPIO13)

V_SCLK/CB (GPIO2)

V_RXOUT/ASLP/ CF (GPIO1)

V_TXSIN/PSLP/ CJ (GPIO9)

V_STROBE/CC/ DA(IN) (GPIO0)

IASLEEP/DFCK/ CE/RXA

VOICE#/ADP/ RDY/CD(GPIO2)

SPKMUTE/ CRXD/DSDT/ (GPIO8)

DSPKOUT/ CTXD/USDT/ (GPIO11)

TCH_RX/DDT/ BB/RX2B (GPIO4)

TCH_FRAME/ UFCK/BA/TX2B (GPIO3)

V_STROBE/CC/ DA(IN) (GPIO0)

IASLEEP/DFCK/ CE/RXA

DSPKOUT/ CTXD/USDT/ TXA(GPIO11)

TCH_TX/UDT/ TXA(GPIO5)

TCH_RX/DDT/ BB/RX2B (GPIO4)

TCH_FRAME/ UFCK/BA/ TX2B (GPIO3)

5 O Itpu/Ot12

6 O Itpu/Ot12

3 I Itpd

2IIt

4OOt2

1 I Itpd

96 I Ot2

100 O Ot12

99 I It/Ot12

87 O Ot12

83 I Itpu/Ot12

85 O Itpu/Ot12

1 I Itpd

96 I It/Ot2

87 O Ot12

82 O Itpu/Ot12

83 I Itpu/Ot12

85 O Itpu/Ot12

Panel 1.

Panel 2.

CB.

CF.

CJ.

CC.

CE.

CD.

Control RXD.

Control TXD.

BB (USART IN).

BA (USART OUT).

GSM PHONE INTERFACE

DA(IN).

RX-A.

TX-A.

RX2-B USART.

TX2-B USART.

Defined by the CDMA firmware driver.

Defined by the GSM firmware driver.

100553B

Conexant

3-13

Page 32

SmartHSF Mobile Modem Data Sheet

Table 3-2. CX11250 HSD Pin Signal Definitions (Continued)

NOTES:

1. I/O Types

I/Opod Digital input/output, PCI, open drain (PCI type = o/d)

I/Opsts Digital input/output, PCI, sustained three-state (PCI type = s/t/s)

I/Opts Digital input/output, PCI, three-state (PCI type = t/s)

Idd input, DIB, data channel

Ip Digital input, PCI, totem pole (PCI type = in)

Ipts Digital input, PCI, (PCI type = t/s)

It Digital input, TTL-compatible

Itpd Digital input, TTL-compatible, internal 75k ± 25k Ω pull-down

Itpu Digital input, TTL-compatible, internal 75k ± 25k Ω pull-up It/Ot2 Digital input, TTL-compatible/digital output, TTL-compatible, 2 mA, Z

It/Ot12 Digital input, TTL-compatible/digital output, TTL-compatible, 12 mA, Z

Ix Crystal/clock input

Odpc Output, DIB power and clock channel

Odd Output, DIB data channel

Ood Digital output, open drain

Opod Digital output, PCI, open drain (PCI type =o/d)

Opts Digital output, PCI, three-state (PCI type = t/s) Ot2 Digital output, TTL-compatible, 2 mA, Z

Ot12 Digital output, TTL-compatible, 12 mA, Z

Ox Crystal output

2. Interface Legend: NC = No internal pin connection RESERVED = No external connection allowed (may have internal connection).

3. All references to PCI Bus also apply to Mini PCI unless otherwise specified.

INTERNAL

= 120

= 32

= 120

INTERNAL

Ω

= 32

Ω

3-14

Conexant

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Page 33

SmartHSF Mobile Modem Data Sheet

Table 3-3. Cell Phone/Telephone Line Interface Signals

Application Signal and I/O Direction

PSTN Selected PDC/PDC Packet

Pin Pin Name PSTN

95 DRESET# (GPOL0) DRESET# O - - - - - - - -

5 M_CLK/PANEL1

(GPIO12)

6 V_CTRL/PANEL2

(GPIO13) 3 V_SCLK/CB (GPIO7) V_SCLK I - - - - CB I - 2 V_RXOUT/ASLP/CF

(GPIO1) 4 V_TXSIN/PSLP/CJ

(GPIO9) 1V_STROBE/CC/

DA(IN) (GPIO0)

96 IASLEEP/DFCK/CE/RXA IASLEEP O - - DFCK I CE I RX-A I

100 VOICE#/ADP/RDY/CD

(GPIO2)

99 SPKMUTE/CRXD/

DSDT (GPIO8)

87 DSPKOUT/CTXD/

USDT/TXA (GPIO11)

81 TCH_CLK/BITC (GPIO6) - - TCH_CLK I BITC I - 82 TCH_TX/UDT/TXA

(GPIO5)

83 TCH_RX/DDT/BB/RX2B

(GPIO4)

85 TCH_FRAME/UFCK/

BA/TX2B (GPIO3)

Signal

M_CLK O Panel 1 O - - Panel 1 O - -

V_CTRL O Panel 2 O - - Panel 2 O - -

V_RXOUT I - - ASLP I CF I - -

V_TXSIN O - - PSLP O CJ O - -

V_STROBE I - - - - CC I DA(IN) I

VOICE# O ADP O RDY O CD O - -

SPKMUTE O CELL_RXD I DSDT I Control RXD I - -

DSPKOUT O CELL_TXD O USDT O Control TXD O TX-A O

PSTN

I/O

- - TCH_TX O UDT O - TX-A O

- - TCH_RX I DDT I BB

- - TCH_FRAME I UFCK I BA

Selected

PDC/

PDC packet

Signal

PHS Selected CDMA Selected GSM Selected

PDC

I/O

PHS

Signal

PHS

I/O

CDMA Signal

(USART IN)

(USART OUT)

CDM

I/O

IRX2-B USART I

OTX2-B USART O

GSM

Signal

GSM

I/O

100553B

Conexant

3-15

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SmartHSF Mobile Modem Data Sheet

3.2 CX20463 SmartDAA LSD HARDWARE PINS AND SIGNALS

3.2.1 LSD Signal Interfaces

HSD Interface (Through DIB)

The DIB interface signals are:

Clock (CLK); input

•

Digital Power (PWR+); input power

•

Digital Ground (DGND); digital ground

•

Data Positive (DIB_P); input

•

Data Negative (DIB_N); input

•

Telephone Line Interface

The telephone line interface signals are:

RING AC Coupled (RAC1); input

•

TIP AC Coupled (TAC1); input

•

Electronic Inductor Resistor (EIR); output

•

TIP and RING DC Measurement (TRDC); input

•

DAC Output Voltage (DAC); output

•

Electronic Inductor Capacitor (EIC)

•

Electronic Inductor Output (EIO)

•

Electronic Inductor Feedback (EIF)

•

Resistive Divider Midpoint (DCF)

•

Transmit Analog Output (TXA); output

•

Receive Analog Input (RXI); input

•

Receiver Gain (RXG); output

•

MOV Enable (MOVEN); output

•

Worldwide Impedance 0 (ZW0); input

•

US Impedance 0 (ZUS0); input

•

Transmit Feedback (TXF); input

•

Transmit Output (TXO); output

•

3.2.2 LSD Interface Signals, Pin Assignments, and Signal Definitions

LSD 32-pin TQFP hardware interface signals are shown by major interface in Figure 3-3, are shown by pin number in Figure 3-4, and are listed by pin number in Table 3-4.

LSD hardware interface signals are defined in Table 3-5.

LSD pin signal digital electrical characteristics are defined in Table 3-6.

3-16

Conexant

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Page 35

PWRCLKN

PWRCLKP

DIB_DATAP

DIB_DATAN

DIGITAL

ISOLATION

BARRIER

C110

R112

C112

(DIB)

POWER AND

CLOCK

CHANNEL

DATA

CHANNEL

C22

C24

R120

NOTES:

1. Consult applicable reference design for exact

component placement and values.

2. R125 is usually installed.

3. R124 is usually removed.

SmartHSF Mobile Modem Data Sheet

RAC2 TAC2

RAC1 TAC1

CX20463

SMARTDAA

LINE SIDE

DAC

TRDC

DEVICE

(LSD)

25 23

32-PIN TQFP

CLK

PWR+

AVDD

DVDD

DGND AGND

DIB_P

DIB_N

POR

R32

C70

C26

R125

DVDD

R124R110

C30 C28

C72C62

GND_LSD

R34

R36

AGND_LSD

DVDD

RXG

TXA

MOVEN (GPIO1)

ZW0

ZUS0

TXO TXF

DCF

VREF

RBIAS

GPIO2

Ring

Filter

15 2 6 5 21 22

3 4 18

14 17 20 19

AGND_LSD

C42

C44

Electronic

Inductor,

Off-Hook,

Pulse Dial,

and TIP and

RING VI

Control

Echo

Cancellation

and

Receiver

Pulse Dial

Voltage

Protection

(Country Specific)

Impedance

Matching

and

Transmitter

C74

AGND_LSD

R54

AGND_LSD

Safety

and EMI

Protection

AGND_LSD

C45

C76

AGND_LSD

Telephone

Line

Connector

TIP RING

EIR EIC

EIO

EIF

RXI

Figure 3-3. CX20463 LSD Hardware Interface Signals

DGND

DVDD

CLK

DIB_P

DIB_N

POR

PWR+

MOVEN (GPIO1)

GPIO2

EIC

RXI

RXG

TRDC

DAC

VREF

CX20463

RAC1

RAC2

TAC1

TAC2

ZW0

RBIAS

EIR

DCF

AVDD

AGND

EIF

EIO

TXO

TXF

TXA

ZUS0

100491F3-7 PO-20463-32T

Figure 3-4. CX20463 LSD 32-Pin TQFP Pin Signals

100491_F3-09_HI CX20463

100553B

Conexant

3-17

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SmartHSF Mobile Modem Data Sheet

Table 3-4. CX20463 LSD 32-Pin TQFP Pin Signals

Pin Signal Label I/O Type Interface

1 GPIO2 It/Ot12 NC 2 EIC Oa Telephone Line Interface Components 3 RXI Ia Telephone Line Interface Components 4 RXG Oa Telephone Line Interface Components 5 TRDC Oa Telephone Line Interface Components 6 DAC Oa Telephone Line Interface Components 7 VC REF VREF through C42 and to AGND_LSD through C44 and C74 8 VREF REF VC through C42 and to AGND_LSD through C45 and C76 9 RAC1 Ia Diode bridge top AC connection (RING) through R2 and C2 10 RAC2 Ia NC 11 TAC1 Ia Diode bridge bottom AC connection (TIP) through R4 and C4 12 TAC2 Ia NC 13 RBIAS Ia AGND_LSD through R54 14 ZW0 Ia Telephone Line Interface Components 15 EIR Ot12 Telephone Line Interface Components 16 DCF Ia AGND_LSD 17 ZUS0 Ia Telephone Line Interface Components 18 TXA Oa Telephone Line Interface Components 19 TXF Ia Telephone Line Interface Components 20 TXO Oa Telephone Line Interface Components 21 EIO Oa Telephone Line Interface Components 22 EIF Ia Telephone Line Interface Components 23 AGND AGND_LSD AGND_LSD 24 AVDD PWR LSD DVDD pin 25 DGND GND_LSD DIB transformer secondary winding undotted terminal through diode D2 and R120 in series

26 DVDD PWR LSD AVDD pin, to GND_LSD through C28, C30, and C72 in parallel, and to DIB

27 CLK I DIB transformer secondary winding undotted terminal through C26 and R32 in series, and

28 DIB_P I/O DIB C22 through R34 29 DIB_N I/O DIB C24 through R36 30 POR It LSD DVDD pin 31 PWR+ PW R DIB transformer secondary winding dotted terminal through R125 and to GND_LSD

32 MOVEN (GPIO1) Ot12 Telephone Line Interface Components

NOTES:

1. I/O types*: Ia Analog input It Digital input, TTL-compatible (See Table 3-6) Oa Analog output

Ot12 Digital output, TTL-compatible, 12 mA, Z

AGND_LSD Isolated LSD Analog Ground GND_LSD Isolated LSD Digital Ground

2. Refer to applicable reference design for exact component placement and values.

and to GND_LSD

transformer secondary winding dotted terminal through R124.

through R120 shared with LSD DGND pin through diode D2

through zener diode D4 and C70 in parallel

INTERNAL

= 32 Ω (See Table 3-6)

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Page 37

SmartHSF Mobile Modem Data Sheet

Table 3-5. CX20463 LSD Pin Signal Definitions

Label Pin I/O Type Signal Name/Description

SYSTEM SIGNALS

AVDD 24 PWR

AGND 23 AGND_LSD

POR 30 It

VREF 8 REF

VC 7 REF

CLK 27 I

PWR+ 31 PWR

DVDD 26 PWR

DGND 25 GND_LSD

DIB_P 28 I/O

DIB_N 29 I/O

RAC1, TAC1

RAC2 TAC2

EIR 15 Oa

EIC 2 Oa

DAC 6 Oa

TRDC 5 Ia

EIO 21 Oa

EIF 22 Ia

RXG 4 Oa

RXI 3 Ia

TXA 18 Oa

MOVEN (GPIO1) 32 Ot12

RBIAS 13 Ia

DCF 16 Ia

9, 11

10, 12

Ia, Ia

Analog Power Supply.

LSD Analog Ground. LSD Analog Ground.

GND_LSD/AGND_LSD tie point and to the analog ground plane.

Power-On Reset.

Output Reference Voltage.

C45 and C76. Ensure a very close proximity between C42 and C45 and the VREF pin.

Output Middle Reference Voltage.

through C44 and C74. Ensure a very close proximity between C44 and the VC pin. Use a short path and a wide trace to AGND_LSD pin.

DIB INTERFACE SIGNALS

Provides input clock, AC-coupled, to the LSD. Connect to DIB transformer

Clock.

secondary winding undotted terminal through R32 and C26 in series, and through R120 shared with LSD DGND pin through diode D2.

Digital Power Input

DIB transformer secondary winding dotted terminal through R125, and to GND_LSD though zener diode D4 and C70 in parallel.

Digital Power

terminal through R124, and to GND_LSD through C28, C30, and C72 in parallel.

LSD Digital Ground.

through diode D2 in series with R120, and to GND_LSD at the GND_LSD/AGND_LSD tie point.

Data and Control Positive.

R34 on the LSD side. DIB_P and DIB_N signals are differential, and ping-pong between DIB and HSD (half duplex).

Data and Control Negative.

R36 on LSD side. DIB_P and DIB_N signals are differential, and ping-pong between DIB and HSD (half duplex).

TIP AND RING INTERFACE

RING1 AC Coupled and TIP1 AC Coupled.

used to detect ring. Connect RAC1 to the diode bridge AC top connection (RING) through R2 and C2.

Connect TAC1 to the diode bridge AC bottom connection (TIP) through R4 and C4.

RING2 AC Coupled and TIP2 AC Coupled.

Electronic Inductor Resistor.

Electronic Inductor Capacitor Switch.

dialing and to ground all other times. This is needed to eliminate pulse dial interference from the electronic inductor AC filter capacitor.

DAC Output Voltage.

TIP and RING DC Measurement.

internally to extract TIP and RING DC voltage and Line Polarity Reversal (LPR) information.

Electronic Inductor Output.

offhook, pulse dial, and DC IV mask operation.

Electronic Inductor Feedback.

Receiver Gain.

Receive Analog Input.

Transmit Analog Output.

MOV Enable

use. Leave open if the product is not intended for Australia, Poland, or Italy.

Receiver Bias.

Resistive Divider Midpoint.

. Connect to pin 24 (AVDD), to DIB transformer secondary winding dotted

. Connect to pulse dial voltage protection circuit for Australia/Poland/Italy

Connect to the LSD DVDD pin.

Connect to LSD DVDD pin.

Connect to VC through C42 and to AGND_LSD through

Connect to VREF through V42 and to AGND_LSD

. Provides unregulated input digital power to the LSD. Connect to

Connect to DIB transformer secondary winding undotted terminal

Connect to HSD DIB_DATAP through C22 in the DIB and

Connect to HSD DIB_DATAN through C24 in the DIB and

Electronic inductor resistor switch.

Internally switched to no connect when pulse

Output voltage of the reference DAC.

Input on-hook voltage (from a resistive divider). Used

Calculated voltage is applied to this output to control

Electronic inductor feedback.

Receiver operational amplifier output.

Receiver operational amplifier inverting input.

Transmit signal used for canceling echo in the receive path.

Connect to GND through R54.

Connect to LSD analog ground.

Connect to AGND_LSD at the

AC-coupled voltage from telephone line

Not used. Leave open.

100553B

Conexant

3-19

Page 38

SmartHSF Mobile Modem Data Sheet

Table 3-5. CX20463 LSD Pin Signal Definitions (Continued)

Label Pin I/O Type Signal Name/Description

TELEPHONE LINE INTERFACE (CONTINUED)

ZW0 14 Ia

ZUS0 17 Ia

TXO 20 Oa

TXF 19 Ia

GPIO2 1 It/Ot12

NOTES:

1. I/O types*: Ia Analog input It Digital input, TTL-compatible (see Table 3-6) Oa Analog output

Ot12 Digital output, TTL-compatible, 12 mA, Z

AGND_LSD Isolated LSD Analog Ground GND_LSD Isolated LSD Digital Ground

2. Refer to applicable reference design for exact component placement and values.

Worldwide Impedance 0.

matching for worldwide countries.

US Impedance 0.

Transmit Output.

transmitter transistor (Q6).

Transmit Feedback.

General Purpose I/O 2

INTERNAL

Outputs transmit signal and impedance matching signal; connect to

NOT USED

Table 3-6. CX20463 LSD DC Electrical Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions

Input Voltage Low V

Input Voltage High V

Output Voltage Low V

Output Voltage High V

Input Leakage Current – -10 – 10 µA

Output Leakage Current (High Impedance) – -10 – 10 µA

GPIO Output Sink Current at 0.4 V maximum – 2.4 – - mA

GPIO Output Source Current at 2.97 V minimum – 2.4 – - mA

GPIO Rise Time/Fall Time 20 100 ns

Test conditions unless otherwise noted:

1. Test Conditions unless otherwise stated: VDD = +3.3 ± 0.3 VDC; TA = 0°C to 70°C; external load = 50 pF

Input signal used to provide line complex impedance

Input signal used to provide line impedance matching for U.S.

Connect to emitter of transmitter transistor (Q6).

. Leave open if not used.

= 32 Ω (see Table 3-6)

-0.30 – 3.60 V VDD = +3.6V

––1.0V

1.6 – – V

0 – 0.33 V

2.97 – – V

3-20

Conexant

100553B

Page 39

SmartHSF Mobile Modem Data Sheet

3.3 CX20437 VC HARDWARE PINS AND SIGNALS (S MODELS)

Microphone and analog speaker interface signals, as well as telephone handset/headset interface signals are provided to support functions such as speakerphone mode, telephone emulation, microphone voice record, speaker voice playback, and call progress monitor.

3.3.1 VC Signal Interfaces

Speakerphone Interface

The following signals are supported:

Speaker Out (M_SPKR_OUT); analog output - Should be used in speakerphone designs where sound quality is important

•

Microphone (M_MIC_IN); analog input

•

Telephone Handset/Headset Interface

The following interface signals are supported:

Telephone Input (M_LINE_IN), input (TELIN) –Optional connection to a telephone handset interface circuit

•

Telephone output (M_LINE_OUTP); output (TELOUT) - Optional connection to a telephone handset interface circuit

•

Center Voltage (VC); output reference voltage

•

HSD Interface

The following interface signals are supported:

Reset (POR); input

•

Sleep (SLEEP); input

•

Master Clock (M_CLKIN); input

•

Serial Clock (M_SCK); output

•

Control (M_CNTRLSIN); input

•

Serial Frame Sync (M_STROBE); output

•

Serial Transmit Data (M_TXSIN); input

•

Serial Receive Data (M_RXOUT); output

•

3.3.2 VC Interface Signals, Pin Assignments, and Signal Definitions

VC 32-pin TQFP hardware interface signals are shown by major interface in Figure 3-5, are shown by pin number in Figure 3-6, and are listed by pin number in Table 3-7.

VC hardware interface signals are defined in Table 3-8.

VC pin signal DC electrical characteristics are defined in Table 3-9.

VC pin signal analog electrical characteristics are defined in Table 3-10.

100553B

Conexant

3-21

Page 40

SmartHSF Mobile Modem Data Sheet

CX11250

HSD

IASLEEP

DRESET#

M_CLK

V_SCLK

V_STROBE

V_TXSIN

V_RXOUT

V_CTRL

+3.3V

VAA (+3.3V)

GND

AGND

4 19 21 23 20 22 18

17 25

28 26

6 27

SLEEP POR M_CLKIN M_SCK M_STROBE M_TXSIN M_RXOUT M_CNTRLSIN

VDD VDD

MAVDD

VSS SET3V_BAR2

MAVSS VSUB

M_DIG_SPEAKER

CX20437

VOICE CODEC

(VC)

32-PIN TQFP

M_MIC_IN

M_SPKR_OUT

M_LINE_IN

M_LINE_OUTP

M_LINE_OUTM

VREF

M_MIC_BIAS

M_RELAYA M_RELAYB

M_ACT90

M_1BIT_OUT

D_LPBK_BAR

NC NC NC

13 3

14 9

MIC SPKOUT

TELIN

TELOUT

FERRITE

AUDIO CIRCUIT

HANDSET INTERFACE

VC_HAND

0.1

FERRITE

0.1 10

15 24 16 29 30 31

AGND

7 8 32

100533_F3-5_HI_20437 32T

Figure 3-5. CX20437 VC Hardware Interface Signals

VSUB

VSS

M_ACT90

M_1BIT_OUT

VREF

M_MIC_IN

M_LINE_IN

SET3V_BAR2

M_MIC_BIAS

M_DIG_SPEAKER

SLEEP

M_SPKR_OUT

POR

MAVDD

MAVSS

M_LINE_OUTP

D_LPBK_BAR

CX20437

M_LINE_OUTM

Figure 3-6. CX20437 VC 32-Pin TQFP Pin Signals

VDD

M_RELAYB

100491 F3-8 PO-CX20437

M_RELAYA

M_STROBE

M_RXOUT

M_SCK

M_TXSIN

M_CLKIN

M_CNTRLSIN

VDD

3-22

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100553B

Page 41

SmartHSF Mobile Modem Data Sheet

Table 3-7. CX20437 VC 32-Pin TQFP Pin Signals

Pin Signal Label I/O I/O Type Interface

1 SLEEP I Itpd HSD: IASLEEP 2 M_DIG_SPEAKER O Ot2 NC 3 M_SPKR_OUT O Oa Speaker interface circuit 4 POR I Itpu HSD: DRESET# 5 MAVDD PWR VAA (+3.3V) 6 MAVSS AGND AGND 7NC NC 8NC NC 9 M_LINE_OUTP (TELOUT) O Oa Handset interface circuit 10 M_LINE_OUTM O Oa NC 11 VREF REF VC through capacitors

12 VC REF AGND through ferrite bead and capacitors and to and to handset interface

13 M_MIC_IN I Ia Microphone interface circuit 14 M_LINE_IN (TELIN) I Ia Handset interface circuit 15 M_MIC_BIAS NC 16 M_RELAYB NC 17 VDD PWR +3.3V 18 M_CNTRLSIN I Itpd HSD: V_CTRL 19 M_CLKIN I Itpd HSD: M_CLK 20 M_TXSIN I Itpd HSD: V_TXSIN 21 M_SCK O Ot2 HSD: V_SCLK 22 M_RXOUT O Ot2 HSD: V_RXOUT 23 M_STROBE O Ot2 HSD: V_STROBE 24 M_RELAYA O Ot2od NC 25 VDD PWR +3.3V 26 M_SET3V_BAR2 I Itpu GND 27 VSUB AGND AGND 28 VSS GND GND 29 M_ACT90 I Itpu NC 30 M_1BIT_OUT O Ot2 NC 31 D_LPBK_BAR I Itpu NC 32 NC NC

NOTES:

1. I/O types: Ia Analog input It Digital input, TTL-compatible Itpd Digital input, TTL-compatible, internal 75k ± 25k Ω pull-down Itpu Digital input, TTL-compatible, internal 75k ± 25k Ω pull-up

It/Ot2 Digital input, TTL-compatible/digital output, TTL-compatible, 2 mA, Z

It/Ot12 Digital input, TTL-compatible/digital output, TTL-compatible, 12 mA, Z

Oa Analog output Ot2 Digital output, TTL-compatible, 2 mA, Z

Ot12 Digital output, TTL-compatible, 12 mA, Z

AGND Analog Ground GND Digital Ground See CX20437 VC Digital Electrical Characteristics (Table 3-9) and CX20437 VC Analog Electrical Characteristics (Table 3-10).

2. Interface Legend: HSD Host Side Device

circuit (VC_HAND) through ferrite bead

INTERNAL

= 120

INTERNAL

= 32

Ω

= 120

= 32

Ω

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Conexant

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SmartHSF Mobile Modem Data Sheet

Table 3-8. CX20437 VC Pin Signal Definitions

Label Pin I/O Type Signal Name/Description

SYSTEM SIGNALS

VDD 17, 25 PWR

MAVDD 5 PWR

VSS 28 GND

MAVSS 6 AGND

VSUB 27 GND

POR 4 Itpu

SET3V_BAR2 26 Itpu

SLEEP 1 Itpd

M_CLKIN 19 Itpd

M_SCK 21 Ot2

M_CNTRL_SIN 18 Itpd

M_STROBE 23 Ot2

M_TXSIN 20 Itpd

M_RXOUT 22 Ot2

TELEPHONE LINE (DAA)/AUDIO INTERFACE AND REFERENCE VOLTAGE

M_LINE_OUTP 9 O(DF)

M_LINE_IN 14 I(DA)

M_MIC_IN 13 I(DA)

M_SPKR_OUT 3 O(DF)

VREF 11 REF

VC 12 REF

Digital Power Supply.

Analog Power Supply.

Digital Ground.

Analog Ground.

Power-On Reset.

Set +3.3V Analog Reference.

HSD INTERCONNECT

IA Sleep.

Master Clock Input

Serial Clock Output.

Control Input.

Serial Frame Sync.

Serial Transmit Data.

Serial Receive Data.

Telephone Handset Out (TELOUT).

handset circuit. The output can drive a 300 Ω load.

Telephone Handset Out (TELIN).

handset circuit.

Microphone Input.

Modem Speaker Analog Output.

analog input signal. The M_SPKR_OUT on/off and three levels of attenuation are controlled by bits in DSP RAM. When the speaker is turned off, the M_SPKR_OUT output is clamped to the voltage at the VC pin. The M_SPKR_OUT output can drive an impedance as low as 300 ohms. In a typical application, the M_SPKR_OUT output is an input to an external LM386 audio power amplifier.

High Voltage Reference.

Ensure a very close proximity between these capacitors and VREF pin.

Low Voltage Reference.

parallel combination of 10 µF and 0.1 µF (ceramic). Ensure a very close proximity between these capacitors and VC pin. Use a short path and a wide trace to AGND pin. Also connect to handset interface circuit (VC_HAND) through a ferrite bead.

Active high sleep input. Connect to HSD IASLEEP pin.

Connect to +3.3V and digital circuits power supply filter.

Connect to +3.3V and analog circuits power supply filter.

Connect to GND.

Connect to AGND.

Active low reset input. Connect to Host RESET#.

Connect to GND.

. Connect to HSD M_CLK pin.

Connect to HSD V_SCLK pin.

Connect to HSD V_CTRL pin.

Connect to HSD V_STROBE pin.

Connect to HSD V_TXSIN pin.

Connect to HSD V_RXOUT pin.

Single-ended analog data output to the telephone

Single-ended analog data input from the telephone

Single-ended from the microphone circuit.

The M_SPKR_OUT analog output reflects the received

Connect to VC through 10 µF and 0.1 µF (ceramic) in parallel.

Connect to analog ground through ferrite bead in series with a

3-24

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Table 3-8. CX20437 VC Pin Signal Definitions (Continued)

Label Pin I/O Type Signal Name/Description

NOT USED

M_DIG_SPEAKER 2 Ot2

M_LINE_OUTM 10 Oa

M_RELAYA 24 Ot

M_RELAYB 16 Ot

M_MIC_BIAS 15 Oa

M_ACT90 29 Itpu

M_1BIT_OUT 30 Ot2

D_LPBK_BAR 31 It

NC 7, 8, 32 NC

NOTES:

It/Ot2 Digital input, TTL-compatible/digital output, TTL-compatible, 2 mA, Z

It/Ot12 Digital input, TTL-compatible/digital output, TTL-compatible, 12 mA, Z

Oa Analog output Ot2 Digital output, TTL-compatible, 2 mA, Z

Ot12 Digital output, TTL-compatible, 12 mA, Z

AGND Analog Ground GND Digital Ground See CX20437 VC Digital Electrical Characteristics (Table 3-9) and CX20437 VC Analog Electrical Characteristics (Table 3-10).

2. Interface Legend: HSD Host Side Device

Not Used.

Internal No Connect.

Leave open.

INTERNAL

= 120

= 32

= 120

INTERNAL

Ω

= 32

Ω

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Table 3-9. CX20437 VC Digital Electrical Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions

Input Voltage Low V

Input Voltage High V

Output Voltage Low V

Output Voltage High V

Input Leakage Current – -10 – 10 µA

Output Leakage Current (High Impedance) – -10 – 10 µA

Test conditions unless otherwise noted:

1. Test Conditions unless otherwise stated: VDD = +3.3 ± 0.3 VDC; TA = 0°C to 70°C; external load = 50 pF

Table 3-10. CX20437 VC Analog Electrical Characteristics

Signal Name Type Characteristic Value

M_LINE_IN (TELIN), I (DA) Input Impedance

M_MIC_IN AC Input Voltage Range 1.1 VP-P

Reference Voltage +1.35 VDC

M_LINE_OUTP (TELOUT) O (DD) Minimum Load

Maximum Capacitive Load 0 µF Output Impedance

AC Output Voltage Range

Reference Voltage +1.35 VDC DC Offset Voltage ± 200 mV

M_SPKR_OUT O (DF) Minimum Load

Maximum Capacitive Load 0.01 µF Output Impedance

AC Output Voltage Range 1.4 VP-P Reference Voltage +1.35 VDC DC Offset Voltage ± 20 mV

Test conditions unless otherwise noted:

1. Test Conditions unless otherwise stated: VDD = +3.3 ± 0.3 VDC; MAVDD = +3.3 ± 0.3 VDC, TA = 0°C to 70°C

-0.30 – VDD+0.3 V

0.4*VDD – – V

0–0.4V

0.8*VDD – VDD V

> 70K

Ω

300

Ω

1.4 VP-P (with reference to ground and a 600 Ω load)

300

Ω

Parameter Min Typ Max Units

DAC to Line Driver output (600Ω load, 3dB in SCF and CTF) SNR/SDR at:

4Vp-p differential 2Vp-p differential

-10dBm differential

DAC to Speaker Driver output (150Ω load, 3dB in SCF and CTF, -6dB in speaker driver) SNR/SDR at:

2Vp-p 1Vp-p

-10dBm

Line Input to ADC (6dB in AAF) SNR/SDR at –10 dBm 80/95 dB Input Leakage Current (analog inputs) -10 10

Output Leakage Current (analog outputs) -10 10

3-26

Conexant

88/85 82/95

72/100

88/75 82/80 72/83

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3.4 ELECTRICAL ENVIRONMENTAL, AND TIMING SPECIFICATIONS

1.1.1 Operating Conditions, Absolute Maximum Ratings, and Power Requirements

The operating conditions are specified in Table 3-11.

The absolute maximum ratings are listed in Table 3-12.

The current and power requirements are listed in Table 3-13.

Table 3-11. Operating Conditions

Parameter Symbol Limits Units

Supply Voltage V

Operating Temperature Range T

Table 3-12. Absolute Maximum Ratings

Parameter Symbol Limits Units

Supply Voltage V

Input Voltage V

Storage Temperature Range T

Analog Inputs V

Voltage Applied to Outputs in High Impedance (Off) State V

DC Input Clamp Current I

DC Output Clamp Current I

Static Discharge Voltage (25°C) V

Latch-up Current (25°C) I

* VIO = +3.3V ± 0.3V or +5V ± 5%.

TRIG

STG

ESD

+3.0 to +3.6 VDC

0 to +70 °C

-0.5 to +4.0 VDC

-0.5 to (VIO +0.5)* VDC

-55 to +125 °C

-0.3 to (MAVDD + 0.5) VDC

-0.5 to (VIO +0.5)* VDC

±20 mA

±2500 VDC

±400 mA

Caution: Handling CMOS Devices

These devices contain circuitry to protect the inputs against damage due to high static voltages. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltage.

An unterminated input can acquire unpredictable voltages through coupling with stray capacitance and internal cross talk. Both power dissipation and device noise immunity degrades. Therefore, all inputs should be connected to an appropriate supply voltage.

Input signals should never exceed the voltage range from 0.5V or more negative than GND to 0.5V or more positive than VDD. This prevents forward biasing the input protection diodes and possibly entering a latch up mode due to high current transients.

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Table 3-13. Current and Power Requirements

Conditions Current Power

CX11250 HSD + CX20463 LSD

Device State (Dx)

and Bus State (Bx)

D0, B0 On Running Yes 38.4 42.2 127 152

D0, B0 On Running No 10.4 11.4 34.3 41.0

D3, B0 On Running No 8.3 9.2 27.4 33.1

D3, B1 On Running No 8.3 9.2 27.4 33.1

D3, B2, B3 (D3hot) On Stopped No 8.3 9.2 27.4 33.1

D3, B3 (D3cold) Off Stopped No 2.4 2.7 7.9 9.7

NOTES:

Operating voltage: VDD = +3.3V ± 0.3V. Test conditions: VDD = +3.3 VDC for typical values; VDD = +3.6 VDC for maximum values. Definitions:

PCI Bus Power On: PCI Bus +5V and +3.3V on (modem normally powered by +3.3V from PCI Bus +3.3V

Mini PCI Bus Power On: PCI Bus +3.3V on (modem normally powered by +3.3V from PCI Bus +3.3V; PCIRST# not asserted.

PCI Clock (PCICLK) Running: PCI Bus signal PCICLK running (PCI Bus and Mini PCI Bus only).

Line connection: Yes: Off-hook, IA powered.

Device States: D3: Low power state. Suspend state can change the system power state; the resulting power state depends

Device and Bus States: D0, B0: Any PCI transaction, PCICLK running, VCC present.

Refer to the PCI Bus Power Management Interface Specification for additional information.

PCI Bus

Power

or regulated down from PCI Bus +5V); PCIRST# not asserted. Off: PCI Bus +5V and +3.3V off (modem normally powered by +3.3V from Vaux or Vpci); PCIRST# asserted.

Off: PCI Bus +3.3V off (modem normally powered by +3.3V from Vaux or Vpci); PCIRST# asserted.

Stopped: PCI Bus signal PCICLK stopped (off) (PCI Bus and Mini PCI Bus only).

No: On-hook, IA powered down.

on the system architecture (OS, BIOS, hardware) and system configuration (i.e., other PCI installed cards). D0: Full power state.

D3, B1: No PCI Bus transactions, PCICLK running, VCC present. D3, B2, B3: No PCI transactions, PCICLK stopped, VCC may be present. D3, B3: No PCI transactions, PCICLK stopped, no VCC.

PCI Clock

(PCICLK)

Line

Connection

Typical

Current (mA)

Maximum

Current (mA)

Typical

Power (mW)

Maximum

3-28

Conexant

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3.4.2 SERIAL EEPROM INTERFACE TIMING

The serial EEPROM interface timing is listed in Table 3-14 and is shown in Figure 3-7.

Table 3-14. Timing - Serial EEPROM Interface

Symbol Parameter Min Typ. Max Units Test Condition

CSS

CSH

DIS

DIH

PD0

PD1

SKH

SKL

– Endurance –

NOTES:

1. Minimum times for HSD outputs when PCI clock = 33 MHz (times increase with decreasing PCI clock frequency).

2. No requirement.

3. Timing controlled by software for programming of EEPROM. No requirement for EEPROM read into HSD.

Chip select setup 200 (Note 1) – – ns

Chip select hold 500 (Note 1) – – ns

Data input setup 200 (Note 1) – – ns

Data input hold 1600 – – ns

Data input delay 50 – – ns

Data input disable time – – Note 2 ns

Status valid – – Note 3 ns

Clock high 900 (Note 1) – – ns

Clock low 900 (Note 1) – – ns

6–Cycles

SROMCS (CS)

SROMCLK (SK)

SROMOUT (DI)

SROMIN (DO) (READ)

SROMIN (DO) (PROGRAM)

CSS

DIS

PD0

SKH

DIH

SKL

Figure 3-7. Waveforms - Serial EEPROM Interface

PD1

CSH

1219F3-7 WF-EEPROM

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SmartHSF Mobile Modem Data Sheet

4. HOST SOFTWARE INTERFACE

4.1 PCI CONFIGURATION REGISTERS

The PCI Configuration registers are located in the HSD. Table 4-1 identifies the configuration register contents that are supported in the HSD:

Table 4-1. PCI Configuration Registers

Bit

Offset

(Hex)

00 Device ID Vendor ID

04 Status (see Table 4-2) Command (see Table 4-3)

08 Class Code Revision ID

0C Not Implemented Header Type Latency Timer Not Implemented

10 Base Address 0 - Memory (HSD)

14 Base Address 1 – I/O (Dummy)

18 Unused Base Address Register

1C Unused Base Address Register

20 Unused Base Address Register

24 Unused Base Address Register

28 CIS Pointer (Not used)

2C Subsystem ID Subsystem Vendor ID

30 Not Implemented

34 Reserved Cap Ptr

38 Reserved

3C Max Latency Min Grant Interrupt Pin Interrupt Line

40 Power Management Capabilities (PMC)

44 Data PMCSR_BSE = 0

31:24 23:16 15:8 7:0

Next Item Ptr = 0 Capability ID =01h

(see Table 4-4)

Bridge Support

Extensions

Power Management

Control/Status Register (PMCSR)

(see Table 4-5)

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4.1.1 0x00 - Vendor ID Field

This 16-bit read-only field identifying the device manufacturer is loaded from the serial EEPROM after reset events. The value is 14F1 for Conexant.

4.1.2 0x02 - Device ID Field

This 16-bit read-only field identifying the particular device is loaded from the serial EEPROM after reset events. The default Device ID if serial EEPROM is not loaded is 0x1085.

4.1.3 0x04 - Command Register

Command Register

15 – 10 9 8 7 6 5 4 3 2 1 0

Reserved r/w r/w 0 r/w 0 0 0 r/w R/w r/w

r/w indicates the bit is read or write.

The Command Register bits are described in Table 4-2.

Table 4-2. Command Register

Bit Description

0 Controls a device’s response to I/O Space accesses. A value of 0 disables the device response. A value

of 1 allows the device to respond to I/O Space accesses. The bit state is 0 after PCIRST# is deasserted.

1 Controls a device’s response to Memory Space accesses. A value of 0 disables the device response. A

value of 1 allows the device to respond to Memory Space accesses. The bit state is 0 after PCIRST# is deasserted.

2 Controls a device’s ability to act as a master on the PCI Bus. A value of 0 disables the device from

generating PCI accesses. A value of 1 allows the device to behave as a bus master. The bit state is 0 after PCIRST# is deasserted.

5-3 Not Implemented.

6 This bit controls the device’s response to parity errors. When the bit is set, the device must take its

normal action when a parity error is detected. When the bit is 0, the device must ignore any parity errors that it detects and continue normal operation. The bit state is 0 after PCIRST# is deasserted.

7 This bit is used to control whether or not a device does address/data stepping. This bit is read only from

the PCI interface. It is loaded from the serial EEROM after PCIRST# is deasserted.

8 This bit is an enable bit for the SERR# driver. A value of 0 disables the SERR# driver. A value of 1

enables the SERR# driver. The bit state is 0 after PCIRST# is deasserted.

9 This bit controls whether or not a master can do fast back-to-back transactions to different devices. A

value of 1 means the master is allowed to generate fast back-to-back transactions to different agents as described in Section 3.4.2 of the PCI 2.1 specification. A value of 0 means fast back-to-back transactions are only allowed to the same agent. The bit state is 0 after PCIRST# is deasserted.

15-10 Reserved

4-2

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4.1.4 0x06 - Status Register

Status Register Bits

15 14 13 12 11 10 – 9 8 7 6 5 4 3 - 0

r/c r/c r/c r/c r/c 01 r/c 0 0 0 1 0000

r/c indicates the bit is readable and clearable (by writing a ‘1’ to corresponding bit position)

The Status Register bits are described in Table 4-3.

Status register bits may be cleared by writing a ‘1’ in the bit position corresponding to the bit position to be cleared. It is not possible to set a status register bit by writing from the PCI Bus. Writing a ‘0’ has no effect in any bit position.

Table 4-3. Status Register

Bit Description

3-0 Reserved

4 Extended capabilities = 1.

7-5 Not Implemented.

8 This bit is only implemented by bus masters. It is set when three conditions are met: 1) the bus agent

asserted PERR# itself or observed PERR# asserted; 2) the agent setting the bit acted as the bus master for the operation in which the error occurred; and 3) the Parity Error Response bit (Command Register) is set.

10-9 These bits encode the timing of DEVSEL#. 01 is supported corresponding to medium speed.

11 Signaled Target Abort. Not implemented.

12 Received Target Abort. This bit must be set by a master device whenever its transaction is terminated with

Target-Abort.

13 Received Master Abort. This bit must be set by a master device whenever its transaction (except for

Special Cycle) is terminated with Master-Abort.

14 Signaled System Error. This bit must be set whenever the device asserts SERR#.

15 Detected Parity Error. This bit must be set by the device whenever it detects a parity error, even if parity

error handling is disabled (as controlled by bit 6 in the Command register).

4.1.5 0x08 - Revision ID Field

This 8-bit read-only field identifying the device revision number is hardcoded in the device.

4.1.6 0x09 - Class Code Field

This 24-bit field, contains three 8-bit sub-fields. The upper byte is a base class code: 07 indicates a communications controller. The middle byte is a sub-class code: 80 indicates “other” type of device. The lower byte is 00 which indicates no register level programming defined. The value of the entire Class Code field is 0x078000.

4.1.7 0x0D - Latency Timer Register

The Latency Timer register specifies, in units of PCI Bus clocks, the value of the Latency Timer for this PCI Bus master. This register has 5 read/write bits (MSBs) plus 3 bits of hardwired zero (LSBs). The Latency Timer Register is loaded into the PCI Latency counter each time FRAME# is asserted to determine how long the master is allowed to retain control of the PCI Bus. This register is loaded by system software. The default value for Latency Timer is 00.

4.1.8 0x0E - Header Type Field

Hardwired to 00.

4.1.9 0x28 - CIS Pointer Register

This register points to the CIS memory located in the HSD’s memory space.

4.1.10 0x2C - Subsystem Vendor ID Register

Subsystem Vendor ID register is supported. Loaded from the serial EEPROM after PCIRST# is deasserted.

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4.1.11 0x2E- Subsystem ID Register

Subsystem ID register is supported. Loaded from the serial EEPROM after PCIRST# is deasserted.

4.1.12 0x34 - Cap Ptr

Capabilities Pointer (CAP_PTR) at offset 0x34 containing hardcoded value 0x40.

4.1.13 0x3C - Interrupt Line Register

The Interrupt Line register is a read/write 8-bit register. POST software will write the value of this register as it initializes and configures the system. The value in this register indicates which of the system interrupt controllers the device’s interrupt pin is connected to.

4.1.14 0x3D - Interrupt Pin Register

The Interrupt Pin register tells which interrupt pin the device uses. The value of this register is 0x01, indicating that INTA# will be used.

4.1.15 0x3E - Min Grant Register

The Min Grant register is used to specify the devices desired settings for Latency Timer values. The value specifies a period of time in units of 0.25 microsecond. Min Grant is used for specifying the desired burst period assuming a 33 MHz clock. This register is loaded from the serial EEPROM after PCIRST# is deasserted.

4.1.16 0x3F - Max Latency Register

The Max Latency register is used to specify the devices desired settings for Latency Timer values. The value specifies a period of time in units of 0.25 microsecond. Min Latency specifies how often the device needs to gain access to the PCI Bus. This register is loaded from the serial EEPROM after PCIRST# is deasserted.

4.1.17 0x40 - Capability Identifier

The Capability Identifier is set to 01h to indicate that the data structure currently being pointed to is the PCI Power Management data structure.

4.1.18 0x41 - Next Item Pointer

The Next Item Pointer register describes the location of the next item in the function’s capability list. The value given is an offset into the function’s PCI Configuration Space. The value of 00h indicates there are no additional items in the capabilities list.

4-4

Conexant

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4.1.19 0x42 - PMC - Power Management Capabilities

The HSD contains power management as described in the PCI Power Management Specification, Revision 1.0 Draft, dated Mar 18, 1997.

The HSD Configuration registers include the following Power Management features:

Status register bit 4 set to 1 to indicate support for New Capabilities

•

Capabilities Pointer (CAP_PTR) at offset 0x34 containing hardcoded value 0x40

•

Power Management Register block at offset 0x40 and 0x44 (see Table 4-1)

•

The Power Management Capabilities register is a 16-bit read-only register which provides information on the capabilities of the function related to power management (Table 4-4).

Table 4-4. Power Management Capabilities (PMC) Register

Bit R/W Description

2:0 R

4 R Reserved (= 0).

5 R DSI (Device Specific Initialization). Loaded from serial EEPROM.

8:6 R Aux. Current. Loaded from serial EEPROM.

9 R D1_Support. When set to a 1, the HSD device supports D1 power state (loaded from serial EEPROM).

10 R D2_ Support. When set to a 1, the HSD device supports D2 power state (loaded from serial EEPROM).

15:11 R

Version. 010b indicates compliance with Revision 1.0 of the

Specification.

PME Clock. Hard coded to 0 to indicate that the PCI clock is

These 5 bits indicate which power states allow assertion of PME (loaded from serial EEPROM). A value of

0 for any bit indicates that the function cannot assert the PME# signal while in that power state.

Bit 11: 1 = PME# can be asserted from D0

Bit 12: 1 = PME# can be asserted from D1

Bit 13: 1 = PME# can be asserted from D2

Bit 14: 1 = PME# can be asserted from D3hot

Bit 15: 1 = PME# can be asserted from D3cold.

PCI Power Management Interface

required for PME generation.

not

4.1.20 0x44 - PMCSR - Power Management Control/Status Register (Offset = 4)

This 16-bit register is used to manage the PCI function’s power management state as well as to enable/monitor power management events (Table 4-5).

Table 4-5. Power Management Control/Status Register (PMCSR)

Bit R/W Description

1:0 R/W Power State.

00 = D0

01 = D1

10 = D2

11 = D3. 7:2 R Reserved (= 000000b).

8 R/W PME_En. A 1 enables PME assertion.

12:9 R/W Data_Select. Selects Data and Data Scale fields.

14:13 R Data Scale. Associated with Data field. Loaded from serial EEPROM.

15:11 R/C PME_Status. This bit is sticky when PME assertion from D3_cold is supported.

PME_Status = 1 indicates PME asserted by the HSD device. Writing 1 clears PME_Status. Writing 0 has no effect.

R: Bit(s) is (are) read only. R/W: Bit(s) is (are) readable and writeable. R/C: Bit(s) is (are) readable, and clearable by writing 1 (bit may not be set by writing).

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4.1.21 0x46 - PMCSR_BSE - PMCSR PCI to PCI Bridge Support Extensions

PMCSR_BSE is cleared to 0 to indicate that bus power/clock control policies have been disabled.

4.1.22 0x47 - Data

This register is used to report the state dependent data requested by the Data_Select field. The value of this register is scaled by the value reported by the Data_Scale field.

4.2 BASE ADDRESS REGISTER

HSD provides a single Base Address Register. The Base Address Register is a 32-bit register that is used to access the HSD register set. Bits 3:0 are hard-wired to 0 to indicate memory space. Bits 15-4 will be hard-wired to 0. The remaining bits (31 -

16) will be read/write. This specifies that this device requires a 64k byte address space. After reset, the Base Address Register contains 0x00000000.

The 64k byte address space used by the HSD is divided into 4k-byte regions. Each 4k-byte region is used as Table 4-6.

Table 4-6. HSD Address Map

Address

[15:12]

0x0 0x0-0xfff BASIC2 Registers Buffers, control, and status registers

0x1 0x0-0xfff CIS Memory Data loaded from Serial EEPROM for Card Bus applications

0x2 0x0-0xfff DSP Scratch Pad Access to DSP scratch pad registers

0x3 0x0-0xfff Reserved

0x4 0x0-0xfff Reserved

0x5-0xF 0x0-0xfff Reserved.

Address

[11:0]

Region Name Description

4-6

Conexant

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4.3 SERIAL EEPROM INTERFACE

The PCI Configuration Space Header and Power Management registers customizable fields are loaded from EEPROM during Power On Reset and during D3 to D0 power transition soft reset. If the EEPROM is missing, default hard-coded values are used. This section describes how the EEPROM content maps into the registers. The PCI Configuration Space Header and Power Management information is used by the PC BIOS/Windows OS to find the driver for this board and also to find out the extent PCI Power Management is typically supported on the modem board.

Obtain the appropriate EEPROM.TXT file (unique to each software configuration) from the local Conexant sales office.

4.3.1 Supported EEPROM Sizes

Two EEPROM sizes are supported: 256 by 16 bit (e.g., 93LC66B) as shown in Table 4-7 and 128 by 16 bit (e.g., 93LC56B) as shown in Table 4-8. The difference is the 256-word version supports modem default country selection from the EEPROM whereas the 128-word version does not.

The EEPROM text file used by the DOS4GW B2EPROM program utility lists the EEPROM content 8 bits per line in hexadecimal format. The least significant 8 bits are listed first followed by the most significant 8 bits of the 16-bit word.

Table 4-7. EEPROM Content for 256 Words by 16 Bits per Word

Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00 Device ID 01 Vendor ID 02 Subsystem Device ID 03 Subsystem Vendor ID 04 Max_Lat Min_Gnt 05 Don’t Care PMC

06 Sub-Class Code Prog. I/F 07 CardBus CIS Pointer High (Not used, don’t care) 08 CardBus CIS Pointer Low (Not used, don’t care) 09 D0C D1C D2C D3C D0D D1D D2D D3D 0A D3 power consumed D2 power consumed 0B D1 power consumed D0 power consumed 0C D3 power dissipated D2 power dissipated 0D D1 power dissipated D0 power dissipated 0E D3_

0F-FE Don’t Care Don’t Care

FF Don’t Care Don’t Care

Cold

D3_

Hot

D2 D1 D0 D2_

bit 8

PMC

bit 7

State

PMC

bit 6

D1_

State

PME DRV

DSI Load CISRAM Count

Class Code

Table 4-8. EEPROM Content for 128 Words by 16 Bits per Word

Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00 Device ID 01 Vendor ID 02 Subsystem Device ID 03 Subsystem Vendor ID 04 Max_Lat Min_Gnt 05 Don’t Care PMC

0F-7F Don’t Care Don’t Care

Cold

D3_

Hot

D2 D1 D0 D2_

100553B

bit 8

PMC

bit 7

State

Conexant

PMC

bit 6

D1_

State

PME DRV

DSI Load CISRAM Count (Not Used, don’t care)

Class Code

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SmartHSF Mobile Modem Data Sheet

4.3.2 Definitions

Device ID Register

This mandatory 16-bit register identifies the type of device and is assigned by Conexant. Valid values are:

Modem-Interface Modem Part Number Device ID Comments

U.S./Japan/Canada Only

SmartHSF/MC-PCI CX11250-11 + 20463-12 2493 Data/Fax SmartHSF/MC-PCI CX11250-11 + 20463-12 2494 Data/Fax/Remote TAM SmartHSF/MC-PCI CX11250-11 + 20463-12 2193 Data/Fax/Cellular SmartHSF/MC-PCI CX11250-11 + 20463-12 2194 Data/Fax/Remote TAM/Cellular SmartHSF/MS-PCI CX11250-11 + 20463-12 + 20437-11 2495 Data/Fax/Voice/Speakerphone SmartHSF/MS-PCI CX11250-11 + 20463-12 + 20437-11 2496 Full-Featured minus Handset

Worldwide including U.S./Japan/Canada

SmartHSF/MWC-PCI CX11250-11 + 20463-11 24A3 Data/Fax SmartHSF/MWC-PCI CX11250-11 + 20463-11 24A4 Data/Fax/Remote TAM SmartHSF/MWC-PCI CX11250-11 + 20463-11 21A3 Data/Fax/Cellular SmartHSF/MWC-PCI CX11250-11 + 20463-11 21A4 Data/Fax/Remote TAM/Cellular SmartHSF/MWS-PCI CX11250-11 + 20463-11 + 20437-11 24A5 Data/Fax/Voice/Speakerphone SmartHSF/MWS-PCI CX11250-11 + 20463-11 + 20437-11 24A6 Full-Featured minus Handset

The CX prefix may not be included in the part number for some devices. Also, the CX prefix may not appear in the part number as

NOTE:

branded on some devices.

Vendor ID Register

This mandatory 16-bit register identifies the manufacturer of the device. The value in this read-only register is assigned by a central authority (i.e., the PCI SIG) that controls the issuance of the numbers. The value is 14F1 for Conexant.

Subsystem Vendor ID and Subsystem Device Register

The subsystem vendor ID is obtained from the SIG, while the vendor supplies its own subsystem device ID. These values are supplied by OEM. Until these values are assigned, Conexant uses default values for Subsystem Vendor ID and Subsystem Device ID which are the same as Vendor ID and Device ID, respectively.

A PCI functional device may be contained on a card or be embedded within a subsystem. Two cards or subsystems that use the same PCI functional device core logic would have the same vendor and device IDs. These two optional registers are used to uniquely identify the add-in card or subsystem that the functional device resides within. Software can then distinguish the difference between cards or subsystems manufactured by different vendors but with the same PCI functional device on the card or subsystem. A value of zero in these registers indicates that there isn’t a subsystem vendor and subsystem ID associated with the device.

Min_Gnt Register

This register is assigned by Conexant. The value is 00.

This register is optional for a bus master and not applicable to non-master devices. This register indicates how long the master would like to retain PCI Bus ownership whenever it initiates a transaction. The value hardwired into this register indicates how long a burst period the device needs (in increments of 250 ns). A value of zero indicates the device has no stringent requirements in this area. This information is useful in programming the algorithm to be used in the PCI Bus arbiter (if it is programmable).

Max_Lat Register

This register is assigned by Conexant. The value is 00.

This register is optional for a bus master and not applicable to non-master devices. The specification states that this read-only register specifies “how often” the device needs access to the PCI Bus (in increments of 250 ns). A value of zero indicates the device has no stringent requirements for the data. This register could be used to determine the priority-level the bus arbiter assigns to the master.

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SmartHSF Mobile Modem Data Sheet

PMC [8:6] and PME DRV Type

These fields are assigned by Conexant.

PMC [8:6]:

been implemented by this function then 1) reads of this field must return a value of “000b” 2) Data Register takes precedence over this field for 3.3Vaux current requirements. If PME# generation from D3cold is not supported by the function (PMC(15)=0), then this field must return a value of “000b” when read. The value is 000b.

PME DRV Type:

is 1.

Class Code Register (Class Code, Sub-class Code, Prog. I/F)

This register is always mandatory and is assigned by Conexant. The value is 07 for Class Code, 80 for Sub-class code, and 00 for Prog. I/F.

This register is a 24-bit read-only register divided into three sub-registers: base class, sub-class, and Prog. I/F (programming interface). The register identifies the basic function of the device via the base class (i.e. for modems: Simple Communications Controller), a more specific device sub-class (i.e. for modems: Other Communications Device), and in some cases a registerspecific programming interface (not used for modems).

CardBus CIS Pointer (CardBus CIS pointer High, CardBus CIS pointer Low) (Not Used)

This read-only register is not used.

Data Scale PMCSR[14:13] (D0C, D1C, D2C, D3C, D0D, D1D, D2D, D3D)

This value is supplied by the OEM since Conexant implements the Data Register. Until these values are assigned, Conexant uses a default value 0000.

This field is required for any function that implements the Data Register. The data scale is a 2- bit read-only field which indicates the scaling factor to be used when interpreting the value of the Data Register. The value and meaning of this field will vary depending on which data value has been selected by the Data_Select field (PMCSR[12:09]). There are 4 data scales to select 1) 0 = unknown 2) 1 = 0.1x, 3) 2 = 0.01x, 4) 3 = 0.001x where x is defined by the Data Select Field.

This 3- bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. If the Data Register has

This bit sets the driving capability of the PME pin (0 = active high TTL, 1 = active low Open Drain). The value

Data Register (D3, D2, D1, D0 power consumed and D3, D2, D1, D0 power dissipated)

This value is supplied by the OEM since Conexant implements the Data Register. Until these values are assigned, Conexant uses a default value of 0000000000000000.

The Data Register is an optional, 8-bit read-only register that provides a mechanism for the function to report state dependent operating data such as power consumed or heat dissipation. Typically the data returned through the Data register is a static copy (look up table, for example) of the function’s worst case “DC characteristics” data sheet. This data, when made available to system software could then be used to intelligently make decisions about power budgeting, cooling requirements, etc. The data returned by the data register is selected by the Data Select field (PMCSR[12:09]).

Load CISRAM Count (CIS _SIZE) (Not Used)

This register is not used.

PMC[15:9, 5] (D3_Cold, D3_Hot, D2, D1, D0, D2_Support, D1_Support, DSI)

PMC[15:11]: PME_Support (D3_Cold, D3_Hot, D2, D1, D0)-

may assert PME#. A value of 0b for any bit indicates that the function is not capable of asserting the PME# signal while in that power state. D2 and D1 must be 0 since the modem does not support these states. The rest of the values are supplied by the OEM and the values depend upon the systems in which the modem will be installed. Conexant uses a default value of 49. This is for a system which does not support D3cold but supports D3hot.

When D3_Cold is a 1, PMC[15] is set to a 1 if VauxDET is high at device power on reset (POR) or is reset to a 0 if VauxDET is low at POR. When D3_Cold is a 0, PMC[15] is always 0, regardless of the VauxDET level.

PMC[10] (D2_Support):

not support this state and therefore this field must be 0.

PMC[9] (D1_Support):

support this state and therefore this field must be 0.

If this bit is a 1 then function supports the D2 Power Management State. Currently the modems do

If this bit is a 1 then function supports the D1 Power Management State. Currently the modems do not

This 5-bit field indicates the power states in which the function

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SmartHSF Mobile Modem Data Sheet

DSI:

The Device Specific Initialization bit indicates whether special initialization of this function is required (beyond the

standard PCI configuration header) before the generic class device driver is able to use it. This bit should always be set to “1”.

NOTE:

For more information, refer to PCI Bus Power Management Interface Specification.

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5. PACKAGE DIMENSIONS

The 100-pin TQFP package dimensions are shown in Figure 5-1.

The 32-pin TQFP package dimensions are shown in Figure 5-2.

16.00 ± 0.15

14.00 ± 0.05

12.00 REF

PIN 1

REF

0.50 REF

1.00 ± .05

0.10 ± .05

COPLANARITY = 0.08 MAX.

0.500 BSC

13.87 ± 0.05

14.00 ± 0.05

DETAIL A

0.22 ± 0.05

+0.15, -0.10

1.00 REF

0.60

12.00 REF

0.14 ± .03

16.00 ± 0.15

14.00 ± 0.05

DETAIL A

13.87 ± 0.05

Ref. 100-PIN TQFP (GP00-D530)

14.00 ± 0.05

PD-TQFP-100-D530 (032699)

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Figure 5-1. Package Dimensions - 100-Pin TQFP

Conexant

5-1

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SmartHSF Mobile Modem Data Sheet

D1 D2

PIN 1 REF

DETAIL A

Millimeters

Min.

1.6 MAX

0.05

1.4 REF

8.75

7.0 REF

5.6 REF

0.5

1.0 REF

0.80 BSC

0.30

0.13

0.10 MAX

Max.

0.15

9.25

0.75

0.40

0.19

Dim.

A1 A2 D D1 D2 L L1 e b c Coplanarity

Ref: 32-PIN TQFP (GP00-D262)

* Metric values (millimeters) should be used for PCB layout. English values (inches) are converted from metric values and may include round-off errors.

Inches*

Min.

0.0630 MAX

0.0020

0.0059

0.0551 REF

0.3445

0.3642

0.2756 REF

0.2205 REF

0.0197

0.0295

0.0394 REF

0.0315 BSC

0.0118

0.0157

0.0051

0.0075

0.004 MAX

Max.

DETAIL A

PD-TQFP-32 (040395)

Figure 5-2. Package Dimensions - 32-pin TQFP

5-2

Conexant

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NOTES

Page 62

0.0

Sales

Offi

ces

Further Information

literature@conexant.com (800) 854-8099 (North America) (949) 483-6996 (International) Printed in USA

WorldHeadquarters

Conexant Systems, Inc. 4311 Jamboree Road Newport Beach, CA 92660-3007 Phone: (949) 483-4600 Fax 1: (949) 483-4078 Fax 2: (949) 483-4391

Americas U.S. North west/

Pacific Northwest – Santa Clara

Phone: (408) 249-9696 Fax: (408) 249-7113

U.S. Southwest – Los Angeles

Phone: (805) 376-0559 Fax: (805) 376-8180

U.S. Southwest – Orange County

Phone: (949) 483-9119 Fax: (949) 483-9090

U.S. Southwest – San Diego

Phone: (858) 713-3374 Fax: (858) 713-4001

U.S. North Central – Illinois

Phone: (630) 773-3454 Fax: (630) 773-3907

U.S. South Central – Texas

Phone: (972) 733-0723 Fax: (972) 407-0639

U.S. Northeast– Massachusetts

Phone: (978) 367-3200 Fax: (978) 256-6868

U.S. Southeast – North Carolina

Phone: (919) 858-9110 Fax: (919) 858-8669

U.S. Southeast – Florida/

South America Phone: (727) 799-8406 Fax: (727) 799-8306

U.S.Mid-Atlantic– Pennsylvania

Phone: (215) 244-6784 Fax: (215) 244-9292

Canada – Ontario

Phone: (613) 271-2358 Fax: (613) 271-2359

Europe Europe Central – Germany

Phone: +49 89 829-1320 Fax: +49 89 834-2734

Europe North – England

Phone: +44 1344 486444 Fax: +44 1344 486555

Europe – Israel/Greece

Phone: +972 9 9524000 Fax: +972 9 9573732

Europe South – France

Phone: +33 1 41 44 36 51 Fax: +33141443690

Europe Mediterranean – Italy

Phone: +39 02 93179911 Fax: +39 02 93179913

Europe – Sweden

Phone: +46 (0) 8 5091 4319 Fax: +46 (0) 8 590 041 10

Europe – Finland

Phone: +358 (0) 9 85 666 435 Fax: +358 (0) 9 85 666 220

Asia – Pacific Taiwan

Phone: (886-2) 2-720-0282 Fax: (886-2) 2-757-6760

Australia

Phone: (61-2) 9869 4088 Fax: (61-2) 9869 4077

China–Central

Phone: 86-21-6361-2515 Fax: 86-21-6361-2516

China–South

Phone: (852) 2 827-0181 Fax: (852) 2 827-6488

China – South (Satellite)

Phone: (86) 755-5182495

China–North

Phone: (86-10) 8529-9777 Fax: (86-10) 8529-9778

India

Phone: (91-11) 692-4789 Fax: (91-11) 692-4712

Korea

Phone: (82-2) 565-2880 Fax: (82-2) 565-1440

Korea (Satellite)

Phone: (82-53) 745-2880 Fax: (82-53) 745-1440

Singapore

Phone: (65) 737 7355 Fax: (65) 737 9077

Japan

Phone: (81-3) 5371 1520 Fax: (81-3) 5371 1501

www.conexant.com

Datasheet CX11250, CX20437, CX20463 Datasheet (CONEX)

Specifications and Main Features

Frequently Asked Questions

User Manual