Page 1
December 1995
CGS701AV
Commercial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701ATV
Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
General Description
CGS701A is an off the shelf clock driver specifically designed for today’s high speed designs. It provides low skew
outputs which are produced at different frequencies from
three fixed input references. The XTALIN input pin is designed to be driven from a 25 MHz–40 MHz crystal oscillator.
The PLL, using a charge pump and an internal loop filter,
multiplies this input frequency to create a maximum output
frequency of four times the input.
The device includes a TRI-STATE
the outputs. This feature allows for low frequency functional
testing and debugging.
Also included, is an EXTSEL pin to allow testing the chip via
an external source. The EXTSEL pin, once set to high, causes the External-ClockÐMUX to change its input from the
output of the VCO and Counter to the external clock signal
provided via SKWTST input pin. (continued)
control pin to disable
É
Features
Y
Guaranteed:
400 ps pin-to-pin skew (t
outputs.
Y
PentiumÉand PowerPCTMcompatible
Y
g
300 ps propagation delay
Y
Output buffer of eight drivers for large fanout
Y
25 MHz–160 MHz output frequency range
Y
Outputs operating at 4X, 2X, 1X of the reference frequency for multifrequency bus applications
Y
Selectable output frequency
Y
Internal loop filter to reduce noise and jitter
Y
Separate analog and digital VCCand ground pins
Y
Low frequency test mode by disabling the PLL
Y
Implemented on National’s Core CMOS process
Y
Symmetric output current drive:a30/b30 mA IOL/I
Y
Industrial temperature ofb40§Ctoa85§C
Y
28-pin PLCC for optimum skew performance
Y
Guaranteed 2k volts ESD protection
OSHL
and t
OSLH
)on1X
OH
CGS701AV Commercial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701ATV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
Connection Diagram
Pin Description
PLCC Package
Pin Assignment for PLCC
TL/F/11920– 1
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
É
PentiumÉis a registered trademark of Intel Corporation.
TM
PowerPC
is a trademark of International Business Machines Corporation.
C
1996 National Semiconductor Corporation RRD-B30M106/Printed in U. S. A.
TL/F/11920
Pin Name Description
1V
2 FBK IN Feedback Input Pin
3 CLK4 4X Clock Output
4V
5 XTALIN Crystal Oscillator Input
6 GND Digital Ground
7 FBK OUT Feedback Output Pin
8V
9 CLK1Ðl 1X Clock Output
10 GND Digital Ground
11 CLK1Ð2 1X Clock Output
12 TRI-STATE Output TRI-STATE Control
13 SKWTST Skew Testing Pin
14 CLK1Ð3 1X Clock Output
15 GND Digital Ground
16 CLK1Ð4 1X Clock Output
17 V
18 SKWSEL Skew Test Selector Pin
19 GNDA Analog Ground
20 V
21 EXTSEL External Clock MUX Selector
22 GND Digital Ground
23 CLK1Ð5 1X Clock Output
24 V
25 CLK1Ð0 1X Clock Output
26 CLK1SEL CLK1 Multiplier Selector
27 GND Digital Ground
28 CLK2 2X Clock Output
CC
CC
CC
CC
CCA
CC
Digital V
CC
Digital V
CC
Digital V
CC
Digital V
CC
Analog V
CC
Digital V
CC
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CGS701A
General Description
CLK1SEL pin changes the output frequency of the
CLK1Ð0 thru CLK1Ð5 outputs. During normal operation,
when CLK1SEL pin is high, these outputs are at the same
frequency as the input crystal oscillator, while CLK2 and
CLK4 outputs are at twice and four times the input frequency respectively.
Once CLK1SEL pin is set to a low logic level, the CLK1
outputs will be at twice the input frequency, the same as the
CLK2 output, with CLK4 output still being at four times the
input frequency.
(Continued)
Block Diagram
In addition, another pin is added for increasing the test capability. SKWSEL pin allows testing of the counter’s output
and skew of the output drivers by bypassing the VCO. In this
test mode CLK4 frequency is the same as SKWTST input
frequency, while CLK2 is 1/2 and CLK1 frequencies are 1/4
respectively (refer to the Truth Table). In addition CLK1SEL
functionality is also true under this test condition.
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TL/F/11920– 2
Page 3
Truth Table
CLK1 EXT EXT SKW SKW
SEL SEL CLK SEL TST
*H L X L X H 4xfin 2xfin fin
*L L X L X H 4xfin 2xfin 2xfin
XHÉXX H ÉÉ É
HLXHÉ H 1xftst (/2 x f tst (/4 x f tst
LLXHÉ H 1xftst (/2 x f tst (/2 x f tst
XXXXX L Z Z Z
*Steady state phase, frequency lock
Typical Application
CGS701A
Input Output
TRI-STATE CLK4 CLK2 CLK1
TL/F/11920– 3
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Page 4
CGS701A
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
DC Input Voltage Diode Current (IIK)
eb
V
0.5V
e
V
V
CC
DC Input Voltage (VI)
DC Output Diode Current (IO)
eb
V
0.5V
e
V
V
CC
DC Output Voltage (VO)
DC Output Source
or Sink Current (I
DC VCCor Ground Current
per Output Pin (I
Storage Temperature (T
Junction Temperature 150§C
Power Dissipation
(Static and Dynamic) (Note B) 1400 mW
Note A: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at
these limits. The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The
Recommended Operating Conditions will define the conditions for actual device operation.
Note B: Power dissipation is calculated using 49
MHz with CLK4 at 132 MHz and CLK2 and CLK1 being at 66 MHz. In addition, the ambient temperature is assumed 70
)
CC
a
0.5V
a
0.5V
)
O
or I
GND
STG
)
)
CC
(Note A)
Recommended Operating
Conditions
Supply Voltage (VCC) 4.5V to 5.5V
b
0.5V toa7.0V
b
20 mA
a
b
0.5V to V
b
0.5V to V
b
65§Ctoa150§C
C/W as the thermal coefficient for the PCC package at 225 LFM airflow. The input frequency is assumed at 33
§
CC
CC
a
b
a
a
g
g
20 mA
0.5V
20 mA
20 mA
0.5V
60 mA
60 mA
Input Voltage (VI) 0VtoV
Output Voltage (VO) 0VtoV
Input Frequency 25 MHz–40 MHz
Operating Temperature (TA) SKWTST 0§Ctoa70§C
External Clock Frequency (Pin) 1 MHz – 10 MHz
XTALIN Duty Cycle Range 25/75 (75/25)%
Input Rise and Fall Times (0.8V to 2.0V)
XTALIN (Pin 5) 5 ns max
All Other Inputs 10 ns max
Typical i
JA
LFM
054
C/W
§
225 45
500 38
900 34
C.
§
CC
CC
DC Electrical Characteristics
Over recommended operating free air temperature range. All typical values are measured at V
e
4.5V–5.5V
V
CC
e
T
Symbol Parameter
V
IH
V
IL
V
OH
V
OL
I
OHD
I
OLD
I
IN
I
OZL/H
C
IN
I
CC
I
CCT
Minimum Input High Level
Voltage
Maximum Input Low Level
Voltage
Minimum Output High Level V
Voltage
Maximum Output Low Level 0.1
Voltage
High Level Output Current
Low Level Output Current 50 110 170 mA V
Leakage Current
Output Leakage Current
Input Capacitance 10.0 pF
Quiescent digitalaanalog
Current (No Load)
ICCper TTL Input 2.5 V
Min Typ Max
2.0 V
b
CC
b
V
CC
b
50
b
50 50 mAV
0§Cto70§C
0.8 V
0.1
0.6 I
0.6 I
b
110
b
170 mA V
3.0 5.0
CC
e
5V, T
e
25§C.
A
Units Conditions
eb
I
V
I
V
V
OUT
OH
OUT
OL
OH
OL
IN
IN
e
50 mA
eb
30 mA
e
50 mA
30 mA
e
V
CC
e
1.0V
e
0.4V or 4.6V
e
VCC, GND
b
mA
e
b
V
CC
2.1, GND
IN
1.0V
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CGS701A
AC Electrical Characteristics
Over recommended operating free air temperature range. All typical values are measured at V
e
V
4.5V–5.5V
CC
e
F
25 to 40 MHz
IN
e
T
Symbol Parameter
t
rise
Output Rise CLK4 0.8V to 2.6V (Note 1, 7)
CLK2 1.0V to V
CLK1 1.0V to V
b
1.0V 2.0 ns
CC
b
1.0V
CC
All 0.8V to 2.0V 1.5
t
fall
Output Fall CLK4 2.6V to 0.8V (Note 1, 7)
CLK2 V
CLK1 V
b
1.0V to 1.0V 2.0 ns
CC
b
1.0V to 1.0V
CC
All 0.8V to 2.0V 1.5
t
SKEW
t
LOCK
t
CYCLE
Maximum Edge-toEdge Output Skew
Time to Lock the Output to the Synch Input 20 100 ms
Output Duty Cycle CLK1 Outputs 49 51 (Note 3, 7)
atoa
Edges CLK1ÐCLK1 400 (Note 2, 7)
atoa
Edges CLK1ÐCLK4 1000 ps
atoa
Edges CLK2ÐCLK4 1000
CLK2 Output 49 51 %
CLK4 Output 35 65
J
LT
t
PD
F
MIN
F
MAX
Note 1: t
Note 2: Skew is measured at 50% of V
Note 3: Output duty cycle is measured at V
Note 4: Jitter parameter is characterized and is guaranteed by design only. It measures the uncertainty of either the positive or the negative edge over 1000 cycles.
It is also measured at output levels of V
Note 5: Measured from the ref. input to any output pin. The length of the feedback and XTALIN traces will impact this delay time.
Note 6: This parameter includes pin-to-pin skew, longterm jitter over 1000 cycles, part-to-part variation as well as propagation delay thru the device.
Note 7: The GNDA pins of the 701 must be as free of noise as possible for minimum jitter. Separate analog ground plane is recommended for the PCB.
Also the V
Output Jitter (Long Term) 0.3 ns (Note 4, 7)
Propogation Delay from XTALIN to FBKOUT
Minimum XTALIN Frequency 15 MHz
Maximum XTALIN Frequency 43 MHz
and t
parameters are measured at the pin of the device.
rise
fall
pin requires extra filtering to further reduce noise. Ferrite beads for filtering and bypass capacitors are suggested for the V
CCA
for CLK1 and CLK2 while it is being measured at 1.4V for CLK4. Limits are guaranteed by design.
CC
/2 for CLK1 and CLK2 while it is being measured at 1.4V for CLK4. Limits are guaranteed by design.
DD
/2. Refer to
Figure 3
CC
for further explanation.
0§Ctoa70§C
e
C
Circuit 1
L
e
R
Circuit 1
L
Min Typ Max
b
0.3
CC
e
5V, T
e
25§C.
A
Units Notes
a
0.3 ns (Notes 2, 4, 5, 6, 7)
pin.
CCA
Circuit 1. Test Circuit
TL/F/11920– 4
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AC Electrical Characteristics
CGS701A
(Continued)
FIGURE 2. Waveforms
TL/F/11920– 5
e
Jitter
Period(n)bPeriod(na1)
l
e
300 ps for either the rising or falling edge, where n is 1 to 1000 cycles.
l
FIGURE 3. Jitter
TL/F/11920– 6
APPLICATION REFERENCES AND BIBLIOGRAPHY:
Information relating to EMI, external feedback and general application issues are in the following application notes:
AN-968
AN-988 (EMI Application Note)
AN-640
AN-991
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Application Example: Cascading CGS701A
TL/F/11920– 7
Application Example: External Feedback Option for the CGS701A
Any one of the 1X output clocks, (CLK1–0–CLK1–5), on the CGS701A can be used instead of the FBK OUT pin. When used in
this configuration, pin 7 is a no connect and the 1X outputs can no longer be used in the 2X mode.
TL/F/11920– 15
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Page 8
Ordering Information (Contact NSC Marketing for Specific Date of Availability)
TL/F/11920– 16
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Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Molded Plastic Leaded Chip Carrier
Order Number CGS701AV or CGS701ATV
NS Package Number V28A
CGS701ATV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701AV Commercial Low Skew PLL 1 to 8 CMOS Clock Driver
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax:
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Tel: 1(800) 272-9959 Deutsch Tel:
Fax: 1(800) 737-7018 English Tel:
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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