Datasheet CD4069UBCW, CD4069UBCSJX, CD4069UBCSJ, CD4069UBCN, CD4069UBSJX Datasheet (Fairchild Semiconductor)

October 1987
Revised January 1999

CD4069UBC Inverter Circuits

© 1999 Fairchild Semiconductor Corporation DS005975.prf www.fairchildsemi.com

CD4069UBC
Inverter Circuits

General Description

The CD4069UB consists of six inverter circuits and is man­ufactured using complementa ry MOS (CMOS) to achieve
wide power supply operating range, low power con sump­tion, high noise immunity, and symmetric controlled rise
and fall times.

This device is intended for all general purpose inverter
applications where the special characteristics of the
MM74C901, MM74C907 , and CD4049A Hex Inverter/Buff­ers are not required. In tho se applications requiring larg er
noise immunity the MM74C14 or MM74C914 Hex Schmitt
Trigger is suggested.

All inputs are protected from damage due to static dis­charge by diode clamps to V

DD

and VSS.

Features

■ Wide supply voltage range: 3.0V to 15V

■ High noise immunity: 0.45 V

DD

typ.

■ Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS

■ Equivalent to MM74C04

Ordering Code:

Device also available in Tape and Reel. Specify by appendin g s uf f ix “X” to the ordering code.

Connection Diagram

Pin Assignments for SOIC and DIP

Schematic Diagram

Order Number Package Number Package Description

CD4069UBCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
CD4069UBCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4069UBCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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CD4069UBC

Absolute Maximum Ratings(Note 1)

(Note 2)

Recommended Operating
Conditions

(Note 2)

Note 1: “Absolute Maxi mum Ratings” are those valu es beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be ope rated at these limi ts. The table of “Recom­mended Operating Condi tions” an d Elect rical Characte ristic s table provi de
conditions for actual device op eration.

Note 2: V

SS

= 0V unless otherw is e s pecified.

DC Electrical Characteristics (Note 3)

Note 3: VSS = 0V unless otherwise s pec if ied.
Note 4: I

OH

and IOL are tested one output at a time.

DC Supply Voltage (VDD) −0.5V to +18 V

DC

Input Voltage (VIN) −0.5V to VDD +0.5 V

DC

Storage Temperature Range (TS) −65°C to +150°C
Power Dissipation (P

D

)
Dual-In-Line 700 mW
Small Outline 500 mW

Lead Temperature (T

L

)
(Soldering, 10 seconds) 260°C

DC Supply Voltage (V

DD

) 3V to 15V

DC

Input Voltag e (VIN)0V to V

DD VDC

Operating Temperature Range (TA) −40°C to +85°C

Symbol Parameter Conditions

−40°C +25°C +85°C

Units

Min Max Min Typ Max Min Max

I

DD

Quiescent Device Current VDD = 5V, 1.0 1.0 7.5 µA

VIN = VDD or V

SS

VDD = 10V, 2.0 2.0 15 µA
VIN = VDD or V

SS

VDD = 15V, 4.0 4.0 30 µA
VIN = VDD or V

SS

V

OL

LOW Level Output Voltage |IO| < 1 µA

VDD = 5V 0.05 0 0.05 0.05 V
VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V

V

OH

HIGH Level Output Voltage |IO| < 1 µA

VDD = 5V 4.95 4.95 4.95 V
VDD = 10V 9.95 9.95 9.95 V
VDD = 15V 14.95 14.95 14.95 V

V

IL

LOW Level Input Voltage |IO| < 1 µA

VDD = 5V, VO = 4.5V 1.0 1.0 1.0 V
VDD = 10V, VO = 9V 2.0 2. 0 2.0 V
VDD = 15V, VO = 13.5V 3.0 3.0 3.0 V

V

IH

HIGH Level Input Voltage |IO| < 1 µA

VDD = 5V, VO = 0.5V 4.0 4.0 4.0 V
VDD = 10V, VO = 1V 8.0 8.0 8.0 V
VDD = 15V, VO = 1.5V 12.0 12.0 12.0 V

I

OL

LOW Level Output Current VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
(Note 4) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA

VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA

I

OH

HIGH Level Output Current VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
(Note 4) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA

VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA

I

IN

Input Current VDD = 15V, VIN = 0V −0.30 −10−5−0.30 −1.0 µA

VDD = 15V, VIN = 15V 0.30 10−50.30 1.0 µA

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CD4069UBC

AC Electrical Characteristics (Note 5)

T

A

= 25°C, CL = 50 pF, RL = 200 kΩ, tr and tf ≤ 20 ns, unle ss otherwise specified

Note 5: AC Parameters are guaranteed by DC correlated testing.
Note 6: C

PD

determines t he no lo ad AC power cons um ptio n of any CM OS d evice. For com plet e expla nati on, se e Family C harac ter istic s ap plica tion no te—

AN-90.

AC Test Circuits and Switching Time Waveforms

Symbol Parameter Conditions Min Typ Max Units

t

PHL

or t

PLH

Propagation Delay Time from VDD = 5V 50 90 ns
Input to Output VDD = 10V 30 60 ns

VDD = 15V 25 50 ns

t

THL

or t

TLH

Transition Time VDD = 5V 80 150 ns

VDD = 10V 50 100 ns
VDD = 15V 40 80 ns

C

IN

Average Input Capacitance Any Gate 6 15 pF

C

PD

Power Dissipation Capacitance Any Gate (Note 6) 12 pF

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CD4069UBC

Typical Performance Characteristics

Gate Transfer Characteristics

Power Dissipation vs

Frequency

Propagation Delay vs

Ambient Temperature

Propagation Delay vs
Ambient Temperature

Propagation Delay Time

vs Load Capacitance

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CD4069UBC

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

Package Number M14A

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm wide

Package Number M14D

Fairchild does not assume any responsi bility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

CD4069UBC Inverter Circuits

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant injury to the
user.

2. A critical component in any c omponent of a life suppor t
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N14A