Datasheet CD40163BMS, CD40162BMS, CD40161BMS Datasheet (Intersil Corporation)

CD40160BMS, CD40161BMS, CD40162BMS,

CD40163BMS

December 1992 File Number 3358

CMOS Synchronous Programmable 4-Bit
Counters

CD40160BMS, CD40161BMS, CD40162BMS and
CD40163BMS are 4-bit synchronous programmable
counters. The CLEAR function of the CD40162BMS and
CD40163BMS is synchronous and a low level at the
input sets all four outputs low on the next positive CLOCK
edge. The CLEAR function of the CD40160BMS and
CD40161BMS is asychronous and a low level at the
input sets all four outputs low regardless of the state of the
CLOCK,

LOAD, or ENABLE inputs. A low level at the LOAD
input disables the counter and causes the output to agree
with the setup data after the next CLOCK pulse regardless of
the conditions of the ENABLE inputs.

The carry look-ahead circuitry provides for cascading counters
for n-bit synchronous applications without additional gating.
Instrumental in accomplishing this function are two count-enable
inputs and a carry output (COUT). Counting is enabled when
both PE and TE inputs are high. The TE input is fed forward to
enable COUT. This enabled output produces a positive output
pulses with a duration approximately equal to the positive portion
of the Q1 output. This positive overflow carry pulse can be used
to enable successive cascaded stages. Logic transitions at the
PE or TE inputs may occur when the clock is either high or low.

The CD40160BMS through CD40163BMS types are functionally
equivalent to and pin-compatible with the TTL counter series
74LS160 through 74LS163 respectively.

The CD40160BMS, CD40161BMS , CD40162BMS and
CD40163BMS are supplied in these 16 lead outline packages:

CD40160 CD40161 CD40162 CD40163
Braze Seal DIP H4W H4X H4X H4W
Frit Seal DIP H1F H1F H1L H1F
Ceramic Flatpack H6P H6W H6P H6W

CLEAR

CLEAR

Features

• High-Voltage Types (20V Rating)

• CD40160BMS Decade with Asynchronous Clear

• CD40161BMS Binary with Asynchronous Clear

• CD40162BMS Decade with Synchronous Clear

• CD40163BMS Binary with Synchronous Clear

• Internal Look-Ahead for Fast Counting

• Carry Output for Cascading

• Synchronously Programmable

• Clear Asynchronous Input (CD40160BMS, CD40161BMS)

• Clear Synchronous Input (CD40162BMS, CD40163BMS)

• Synchronous Load Control Input

• Low Power TTL Compatibility

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package

Temperature Range; 100nA at 18V and +25oC

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

• MeetsAllRequirements of JEDEC T entativeStandard No. 13B,
“Standard Specifications for Description of ‘B’ Series CMOS
Devices”

Applications

• Programmable Binary and Decade Counting

• Counter Control/Timers

• Frequency Dividing

Pinout

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

TOP VIEW

16

CLEAR

CLOCK

P1
P2
P3
P4

PE

VSS

1
2
3
4
5
6
7
8

4-1

VDD
CARRY OUT

15
14

Q1

13

Q2

12

Q3
Q4

11
10

TE

9

LOAD

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Functional Diagram

7

PE Q1

10

TE

LOAD

P1
P2
P3
P4

1
9
2
3
4
5

6

CLEAR

CLOCK

VDD = 16
VSS = 8

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

14

13

12

11

15

Q2

Q3

Q4

CARRY

OUT

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . .-0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA

VDD = 18V, VIN = VDD or GND 3 -55oC-10µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low
(Note 2)

Input Voltage High
(Note 2)

Input Voltage Low
(Note 2)

Input Voltage High
(Note 2)

NOTES: 1. All voltages referenced to device GND, 100% testing being im-

plemented.

2. Go/No Go test with limits applied to inputs.

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

Thermal Resistance. . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W

Flatpack Package. . . . . . . . . . . . . . . . 70oC/W 20oC/W

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55oC to +100oC (Package Type D, F, K). . . . . . .500mW

For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate

Linearity at 12mW/oC to 200mW

Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC

GROUP A

SUBGROUPS TEMPERATURE

2 +125oC - 1000 µA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. For accuracy,voltage ismeasureddifferentially toVDD.Limit is

0.050V max.

ja

LIMITS

VDD/2

VOL <
VDD/2

θ

jc

UNITSMIN MAX

V

4-2

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1, 2)

Propagation Delay
Clock to Q

Propagation Delay
Clock to COut

Propagation Delay
TE to COut

Propagation Delay
CD40160BMS,
CD40161BMS Clear to Q

Transition Time TTHL

Maximum Clock Input Fre­quency

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TPHL1
TPLH1

TPHL2
TPLH2

TPHL3
TPLH3

TPHL4 VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns

TTLH

FCL VDD = 5V, VIN = VDD or GND 9 +25oC 2 - MHz

VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 450 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 250 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

GROUP A

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 540 ns

10, 11 +125oC, -55oC - 608 ns

10, 11 +125oC, -55oC - 338 ns

10, 11 +125oC, -55oC - 675 ns

10, 11 +125oC, -55oC - 270 ns

10, 11 +125oC, -55oC 1.48 - MHz

LIMITS

UNITSMIN MAX

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

+125oC - 150 µA

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

+125oC - 300 µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

+125oC - 600 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -

55oC

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -

55oC

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -

55oC

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -

55oC

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

-55oC 0.64 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

-55oC 1.6 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

-55oC 4.2 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

-55oC - -0.64 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

-55oC - -2.0 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

-55oC - -1.6 mA

-50mV

-50mV

4.95 - V

9.95 - V

UNITSMIN MAX

4-3

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

-55oC - -4.2 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -

55oC

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -

55oC

Propagation Delay
Clock to Q

Propagation Delay
Clock to C Out

Propagation Delay
TE to C Out

Propagation Delay
CD40160BMS,
CD40161BMS Clear to Q

Transition Time TTHL

Maximum Clock Input Fre­quency

Maximum Clock Rise or
Fall Time

Minimum Data Hold Time
Clock Operation

Minimum Clock Pulse
Width
Clock Operation

Minimum Setup Time
Data to Clock

Minimum Setup Time
Load to Clock

Minimum Setup Time PE
to TE to Clock

Minimum Clear Pulse
Width (CD40160BMS,
CD40161BMS)

Minimum Setup Time
Clear to Clock
(CD40162BMS,
CD40163BMS)

Minimum Hold Time
Clear to Clock
(CD40162BMS,
CD40163BMS)

TPHL1
TPLH1

TPHL2
TPLH2

TPHL3
TPLH3

TPHL4 VDD = 10V 1, 2, 3 +25oC - 220 ns

TTLH

FCL VDD = 10V 1, 2, 3 +25oC 5.5 - MHz

TRCL
TFCL

TH VDD = 5V 1, 2, 3 +25oC-0ns

TW VDD = 5V 1, 2, 3 +25oC - 170 ns

TS VDD = 5V 1, 2, 3 +25oC - 240 ns

TS VDD = 5V 1, 2, 3 +25oC - 240 ns

TS VDD = 5V 1, 2, 3 +25oC - 340 ns

TW VDD = 5V 1, 2, 3 +25oC - 170 ns

TS VDD = 5V 1, 2, 3 +25oC - 340 ns

TH VDD = 5V 1, 2, 3 +25oC-0ns

VDD = 10V 1, 2, 3 +25oC - 160 ns
VDD = 15V 1, 2, 3 +25oC - 120 ns
VDD = 10V 1, 2, 3 +25oC - 190 ns
VDD = 15V 1, 2, 3 +25oC - 140 ns
VDD = 10V 1, 2, 3 +25oC - 110 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns

VDD = 15V 1, 2, 3 +25oC - 160 ns

VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns

VDD = 15V 1, 2, 3 +25oC 8 - MHz
VDD = 5V 1, 2, 3, 4 +25oC - 200 µs
VDD = 10V 1, 2, 3, 4 +25oC-70µs
VDD = 15V 1, 2, 3, 4 +25oC-15µs

VDD = 10V 1, 2, 3 +25oC-0ns
VDD = 15V 1, 2, 3 +25oC-0ns

VDD = 10V 1, 2, 3 +25oC - 70 ns
VDD = 15V 1, 2, 3 +25oC - 50 ns

VDD = 10V 1, 2, 3 +25oC - 90 ns
VDD = 15V 1, 2, 3 +25oC - 60 ns

VDD = 10V 1, 2, 3 +25oC - 90 ns
VDD = 15V 1, 2, 3 +25oC - 60 ns

VDD = 10V 1, 2, 3 +25oC - 140 ns
VDD = 15V 1, 2, 3 +25oC - 100 ns

VDD = 10V 1, 2, 3 +25oC - 70 ns
VDD = 15V 1, 2, 3 +25oC - 50 ns

VDD = 10V 1, 2, 3 +25oC - 140 ns
VDD = 15V 1, 2, 3 +25oC - 100 ns

VDD = 10V 1, 2, 3 +25oC-0ns
VDD = 15V 1, 2, 3 +25oC-0ns

-3V

7-V

UNITSMIN MAX

4-4

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Minimum Clear Removal
Time
(CD40160BMS,
CD40161BMS)

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of
the output of the driving stage for the estimated capacitive load.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

Propagation Delay Time TPHL

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TREM VDD = 5V 1, 2, 3 +25oC - 200 ns

VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 70 ns

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

VOL <

TPLH

VDD = 3V, VIN = VDD or GND
VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

3. See Table 2 for +25oC limit.

4. Read and Record

VDD/2

VDD/2

+25oC

Limit

UNITSMIN MAX

UNITSMIN MAX

V

ns

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

METHOD GROUP A SUBGROUPS READ AND RECORD

4-5

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

CONFORMANCE GROUPS

MIL-STD-883

METHOD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION OPEN GROUND VDD 9V ± -0.5V

50kHz 25kHz

Static Burn-In 1 Note 1 11 - 15 1 - 10 16
Static Burn-In 2 Note 1 11 - 15 8 1 - 7, 9, 10, 16
Dynamic Burn-In Note 1 - 8 1, 7, 9, 10, 16 11 - 15 2 - 6 ­Irradiation Note 2 11 - 15 8 1 - 7, 9, 10, 16

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

Logic Diagrams

LOAD*

9

CLOCK*

2

CLEAR*

1

LOAD*

9

CLOCK

2

CLEAR*

1

CD40160BMS

ASYNCHRONOUS

CLEAR

CD40162BMS

SYNCHRONOUS

CLEAR

*

CD40160BMS AND CD40162BMS BCD DECADE COUNTERS

*** * * **

Q1

LD PI

T

CL

CLR

616543107

PE TE P1 P2 P3 VDD P4

LD PI

T

CL

CLR

Q1

Q4

LD PI

Q1 Q2 Q3 Q4

T

Q1 Q2

CL

CLR

Q4

Q1

LD PI

T

CL

CLR

Q3 Q4

Q1

*INPUTS PROTECTED BY

CMOS PROTECTION NETWORK

FIGURE 1. LOGIC DIAGRAM FOR CD40160BMS AND CD40162BMS BCD DECADE COUNTERS

4-6

VDD

14 13 12 11 15

Q1 Q2 Q3 Q4 COUT

VSS

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

Logic Diagrams (Continued)

CD40161BMS AND CD40163BMS BINARY COUNTERS

LOAD*

9

CLOCK*

2

CLEAR*

1

LOAD*

9

CLOCK

2

CLEAR*

1

CD40161BMS

ASYNCHRONOUS

CLEAR

CD40163BMS

SYNCHRONOUS

CLEAR

*

*** * * *

16

PE TE P1 P2 P3 P4

LD PI

T

CL

CLR

VDD

Q1 Q1

Q1

LD PI

Q1 Q2 Q3 Q4

T
CL

CLR

Q1 Q2 Q3 Q4

Q2

LD PI

T

CL

CLR

Q2

Q2

LD PI

T

CL

CLR

6543107

Q2

Q4

Q3

Q1

*INPUTS PROTECTED BY

CMOS PROTECTION NETWORK

VDD

14 13 12 11 15

Q1 Q2 Q3 Q4 COUT

VSS

FIGURE 2. LOGIC DIAGRAM FOR CD40161BMS AND CD40163BMS BINARY COUNTERS

TRUTH TABLE

CLOCK CLR LOAD PE TE OPERATION

1 0 X X Preset
110XNC
11X0NC
1111Count

X 0 X X X Reset (CD40160BMS, CD40161BMS)

0 X X X Reset (CD40162BMS, CD40163BMS)
1 X X X NC (CD40162BMS, CD40163BMS)

1 = High Level
0 = Low Level

X = Don’t Care
NC = No Change

4-7

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC

30

25

20

15

10

5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

AMBIENT TEMPERATURE (TA) = +25oC

15.0

12.5

10.0

7.5

5.0

2.5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

FIGURE 4. MIMIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

0-5-10-15

0

-5

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

0-5-10-15

0

-5

-10V

-15V

-10

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

300

SUPPL Y VOLT AGE (VDD) = 5V

200

100

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

0

20 40 60 80 100

LOAD CAPACITANCE (CL) (pF)

10V

15V

FIGURE7. TYPICAL PROPAGATIONDELAY TIME ASAFUNC-

TION OF LOAD CAPACITANCE (CLOCK TO Q)

-10V

-15V

-10

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

200

150

100

50

TRANSITION TIME (tTHL, tTLH) (ns)

0

0 40 60 80 10020

SUPPL Y VOLT AGE (VDD) = 5V

10V
15V

LOAD CAPACITANCE (CL) (pF)

FIGURE 8. TYPICAL TRANSISTION TIME AS A FUNCTION OF

LOAD CAPACITANCE

4-8

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

Typical Performance Characteristics (Continued)

5

10

8

AMBIENT TEMPERATURE (TA)

6

o

C

= +25

4
2

4

10

SUPPLY VOLTAGE (VDD)
= 15V

8
6

4
2

3

10

8
6

4
2

2

10

8
6

POWER DISSIPATION (PD) (µW)

4
2

10

11010

FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY

8642

8642864286428642

2

CLOCK FREQUENCY (fCL) (kHz)

5V

10

10V

CL = 50pF
CL = 15pF

3

10V

4

10

CLEAR (CD40160BMS)
CLEAR (CD40162BMS)

LOAD

P1

P2

DATA INPUTS

P3

P4

CLOCK (CD40160BMS)

CLOCK (CD40162BMS)

PE

ENABLES

TE

Q1

ASYNCHRONOUS

SYNCHRONOUS

OUTPUTS

CARRY OUT

Q2

Q3

Q4

0 7890123

CLEAR PRESET

COUNT INHIBIT

FIGURE 10. TIMING DIAGRAM FOR CD40160BMS, CD40162BMS

4-9

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

CLEAR (CD40161BMS)
CLEAR (CD40163BMS)

LOAD

P1

P2

DATA INPUTS

P3

P4

CLOCK (CD40161BMS)

CLOCK (CD40163BMS)

PE

ENABLES

TE

Q1

ASYNCHRONOUS

SYNCHRONOUS

OUTPUTS

CARRY OUT

Q2

Q3

Q4

0 121314150 1 2

CLEAR PRESET

COUNT INHIBIT

FIGURE 11. TIMING DIAGRAM FOR CD40161BMS AND CD40163BMS

4-10

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

CL

CLRLDPNTN

p
n

p
n

p
n

CL

CL

CL

p
n

CL CL

p
n

CL

CL

CL

p
n

p
n

QN

QN

FIGURE 12. DETAIL OF FLIP-FLOPS OF CD40160BMS AND CD40161BMS (ASYNCHRONOUS CLEAR)

LDPNTN CLR

CL

p
n

p
n

p
n

CL

CL

CL

CL

CL

CL

p
n

p
n

CL

CL

p
n

p
n

QN

QN

FIGURE 13. DETAIL OF FLIP-FLOPS OF CD40162BMS AND CD40163BMS (SYNCHRONOUS CLEAR)

4-11

LOAD

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

VDD

CLOCK

CLEAR

LOAD

CLOCK

VDD

PE
TE
CLK

P1 P2 P3 P4

LD

CLR

Q1 Q2 Q3 Q4

CD

VDD

PE
TE
CLK

P1 P2 P3 P4

LD

CLR

Q1 Q2 Q3 Q4

CD

PE
TE
CLK

FIGURE 14. CASCADED COUNTER PACKAGES IN THE PARALLEL-CLOCKED MODE

VDD VDD

P1 P2 P3 P4

LD

CLR

Q1 Q2 Q3 Q4

CD

PE
TE
CLK

PE
TE
CLK

P1 P2 P3 P4

LD

CLR

Q1 Q2 Q3 Q4

CD

PE
TE
CLK

P1 P2 P3 P4

LD

CD

CLR

Q1 Q2 Q3 Q4

P1 P2 P3 P4

LD

CD

CLR

Q1 Q2 Q3 Q4

CLEAR

FIGURE 15. CASCADED COUNTER PACKAGES IN THE RIPPLE-CLOCKED MODE

Chip Dimensions and Pad Layout

Dimensions and pad layout for CD40160BMSH.
Dimensions and pad layout for CD40161BMS,
CD40162BMSH, and CD40163BMSH are identical.

Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10

-3

inch)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

4-12

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. Howev er, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

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NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

4-13

EUROPE

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Mercure Center
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1130 Brussels, Belgium
TEL: [phone]
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