Datasheet CD4021BMS, CD4014BMS Datasheet (Intersil Corporation)

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Page 1

CD4014BMS,

CD4021BMS

December 1992

Features

• High Voltage Types (20V Rating)

• Medium Speed Operation 12MHz (Typ.) Clock Rate at VDD-VSS = 10V

• Fully Static Operation

• 8 Master-Slave Flip-Flops Plus Output Buffering and Control Gating

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25

• Noise Margin (Full Package Temperature Range)

• 1V at VDD = 5V

• 2V at VDD = 10V

• 2.5V at VDD = 15V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Speciﬁcations for Description of `B' Series CMOS Devices

Applications:

CMOS 8-Stage Static Shift Registers

Description

CD4014BMS -Synchronous Parallel or Serial Input/Serial Output CD4021BMS -Asynchronous Parallel Input or Synchronous

Serial Input/Serial Output

CD4014BMS and CD4021BMS series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel “JAM” inputs to each register stage. Each register stage is a D-type, master-slave ﬂip-ﬂop. In addition to an output from stage 8, “Q” outputs are also available

from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014BMS. In the CD4021BMS serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the P ARALLEL/ SERIAL CONTROL input is high, data is jammed into the 8stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021BMS, the CLOCK input of the internal stage is “forced” when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.

The CD4014BMS and CD4021BMS are supplied in these 16 lead outline packages:

• Parallel Input/Serial Output Data Queueing

• Parallel to Serial Data Conversion

• General Purpose Register

Pinout

PI-8

Q8 PI-4 PI-3 PI-2 PI-1

VSS

1 2 3 4 5 6 7 8

VDD

PI-7

PI-6

PI-5

SERIAL IN

CLOCK

PARALLEL/SERIAL CONTROL

Braze Seal DIP H4T Frit Seal DIP H1F Ceramic Flatpack H6W

Functional Diagram

12345678

PARALLEL/SERIAL

CONTROL

SERIAL IN

CLOCK

PAR. IN

VDD

14 1513 1456716

BUFFERED

VSS

OUT

7-80

File Number

3294

Page 2

Speciﬁcations CD4014BMS, CD4021BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65

C to +125oC

C to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25

VDD = 18V, VIN = VDD or GND 3 -55oC-10µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

(Note 2) Input Voltage High

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

(Note 2) Input Voltage Low

(Note 2) Input Voltage High

(Note 2)

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs.

Thermal Resistance . . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55 For TA = +100

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

C to +100oC (Package Type D, F, K). . . . . . 500mW

C to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

C/W 20oC/W

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

GROUP A

LIMITS

SUBGROUPS TEMPERATURE

C-10µA

2 +125oC - 1000 µA

C -100 - nA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

VOL <

VDD/2

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.

UNITSMIN MAX

7-81

Page 3

Speciﬁcations CD4014BMS, CD4021BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL CONDITIONS (NOTE 1, 2)

Propagation Delay TPHL

TPLH

Transition Time TTHL

TTLH

Maximum Clock Input Frequency

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

FCL VDD = 5V, VIN = VDD or GND 9 +25oC 3 - MHz

VDD = 5V, VIN = VDD or GND 9 +25oC - 320 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 432 ns

10, 11 +125oC, -55oC - 270 ns

10, 11 +125oC, -55oC 2.22 - MHz

+125oC - 150 µA

+125oC - 300 µA

+125oC - 600 µA

-55oC

-55oC 0.64 - mA

-55oC 1.6 - mA

-55oC 4.2 - mA

-55oC - -0.64 mA

-55oC - -2.0 mA

-55oC - -1.6 mA

-55oC - -4.2 mA

-55oC

LIMITS

UNITSMIN MAX

LIMITS

UNITSMIN MAX

-50mV

4.95 - V

9.95 - V

-3V

7-V

7-82

Page 4

Speciﬁcations CD4014BMS, CD4021BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Propagation Delay TPHL

TPLH

Transition Time TTHL

TTLH

Maximum Clock Input

FCL VDD = 10V 1, 2, 3 +25

Frequency Clock Rise and Fall Time

(Note 4)

TRCL TFCL

VDD = 10V 1, 2, 3 +25oC - 160 ns VDD = 15V 1, 2, 3 +25oC - 120 ns VDD = 10V 1, 2, 3 +25oC - 100 ns

VDD = 15V 1, 2, 3 +25

C - 80 ns

C 6 - MHz

VDD = 15V 1, 2, 3 +25oC 8.5 - MHz

VDD = 5V 3, 5 +25 VDD = 10V 3, 5 +25

C-15µs

VDD = 15V 3, 5 +25oC-15µs

Minimum Hold Time Serial In, Parallel In Parallel/Serial Control

TH VDD = 5V 1, 2, 3 +25oC-0ns

VDD = 10V 1, 2, 3 +25oC-0ns VDD = 15V 1, 2, 3 +25oC-0ns

Minimum Clock Pulse Width

TW VDD = 5V 1, 2, 3 +25oC - 180 ns

VDD = 10V 1, 2, 3 +25oC - 80 ns VDD = 15V 1, 2, 3 +25oC - 50 ns

Minimum Setup Time Serial Input (Ref. to CL)

TS VDD = 5V 2, 3 +25oC - 120 ns

VDD = 10V 2, 3 +25oC - 80 ns VDD = 15V 2, 3 +25oC - 60 ns

Minimum Setup Time Parallel Inputs CD4014BMS (Ref. to CL)

Minimum Setup Time Parallel Inputs CD4021BMS (Ref. to P/S)

Minimum Setup Time Parallel/Serial Control CD4014BMS (Ref. to CL)

TS VDD = 5V 2, 3 +25oC - 80 ns

VDD = 10V 2, 3 +25oC - 50 ns VDD = 15V 2, 3 +25oC - 40 ns

TS VDD = 5V 2, 3 +25oC - 50 ns

VDD = 10V 2, 3 +25oC - 30 ns VDD = 15V 2, 3 +25oC - 20 ns

TS VDD = 5V 2, 3 +25oC - 180 ns

VDD = 10V 2, 3 +25oC - 80 ns VDD = 15V 2, 3 +25oC - 60 ns

Minimum P/S Pulse Width (CD4021BMS)

TWH VDD = 5V 2, 3 +25oC - 160 ns

VDD = 10V 2, 3 +25oC - 80 ns VDD = 15V 2, 3 +25oC - 50 ns

Minimum P/S Removal Time CD4021BMS (Ref. to CL)

TREM VDD = 5V 2, 3 +25oC - 280 ns

VDD = 10V 2, 3 +25oC - 140 ns VDD = 15V 2, 3 +25oC - 100 ns

Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. If more than one unit is cascaded, TRCL should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.

UNITSMIN MAX

7-83

Page 5

Speciﬁcations CD4014BMS, CD4021BMS

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V N Threshold Voltage

Delta P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage

Delta Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

Propagation Delay Time TPHL

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

∆VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

∆VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

VOL < VDD = 3V, VIN = VDD or GND VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

TPLH

3. See Table 2 for +25oC limit.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading Output Current (Source) IOH5A ± 20% x Pre-Test Reading

VDD/2

+25oC

Limit

UNITSMIN MAX

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

CONFORMANCE GROUPS

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

METHOD GROUP A SUBGROUPS READ AND RECORD

TABLE 7. TOTAL DOSE IRRADIATION

MIL-STD-883

METHOD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

TEST READ AND RECORD

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION OPEN GROUND VDD 9V ± -0.5V

Static Burn-In 1 (Note 1) 2, 3, 12 1,4-11, 13-15 16

7-84

OSCILLATOR

50kHz 25kHz

Page 6

Speciﬁcations CD4014BMS, CD4021BMS

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued)

OSCILLATOR

FUNCTION OPEN GROUND VDD 9V ± -0.5V

50kHz 25kHz

Static Burn-In 2 (Note 1) 2, 3, 12 8 1, 4-7, 9-11, 13-6 Dynamic Burn-In (Note 1) - 1, 4-9, 13 -15 16 2, 3, 12 10 11 Irradiation (Note 2) 2, 3, 12 8 1, 4-7, 9-11, 13-16

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V

Logic Diagram

P7 P8P6P5P4P3P2P1

7 6 5 4 13 14 15 1

********

SERIAL INPUT

CLOCK

D Q

PARALLEL/SERIAL CONTROL

D Q

*ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION NETWORK

≡

VDD

VSS

p n

FIGURE 1. CD4014BM LOGIC DIAGRAM

TRUTH TABLE - CD4014BMS

CL SERIAL INPUT PARALLEL/SERIAL CONTROL PI-1 PI-n Q1 (INTERNAL) Qn

X 1 0000 X 1 1010 X 1 0101 X 1 1111 0 0 X X 0 Qn-1 1 0 X X 1 Qn-1 X X X X Q1 Qn NC

X = Don’t Care Case NC = No Change

322

p n

Q8Q7Q6

7-85

Page 7

SERIAL INPUT

CLOCK

PARALLEL/ SERIAL CONTROL

D Q

CD4014BMS, CD4021BMS

P7 P8P6P5P4P3P2P1

7 6 5 4 13 14 15 1

********

D Q

322

Q8Q7Q6

D Q

p n

D Q

p n

D Q

p n

≡

p n

D Q

p n

D Q

p n

VDD

VSS

*ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION NETWORK

FIGURE 2. CD4021BMS LOGIC DIAGRAM

TRUTH TABLE - CD4021BMS

SERIAL

INPUT

PARALLEL/SERIAL

CONTROL PI-1 PI-nQ1(INTERNAL) Qn

XX 1 0000 XX 1 0101 XX 1 1010 XX 1 1111

0 0 X X 0 Qn-1 1 0 X X 1 Qn-1

X 0 X X Q1 Qn NC

X = Don’t Care Case

7-86

Page 8

CD4014BMS, CD4021BMA

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

AMBIENT TEMPERATURE (TA) = +25oC

15.0

12.5

10.0

7.5

5.0

2.5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

0-5-10-15

-5

-10

-15

-20

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

0-5-10-15

-5

-10

-25

-15V

-30

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

200

150

100

TRANSITION TIME (tTHL, tTLH) (ns)

0 40 60 80 10020

SUPPLY VOLTAGE (VDD) = 5V

10V 15V

LOAD CAPACITANCE (CL) (pF)

FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE

-15V

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

300

200

100

PROPAGATION DELAY TIME (tTHL, tTLH) (ns)

0 40 60 80 10020

SUPPLY VOLTAGE (VDD) = 5V

CAPACITANCE (CL) (pF)

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

10V

15V

7-87

Page 9

CD4014BMS, CD4021BMS

Typical Performance Characteristics (Continued)

6 4

POWER DISSIPATION (PD) (µW)

8 6 4

SUPPLY VOLTAGE (VDD) = 15V

2468102468

AMBIENT TEMPERATURE (TA) = +25oC

2468

CLOCK INPUT FREQUENCY (fCL) (kHz)

FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY

Chip Dimensions and Pad Layouts

10V

CL = 50pF CL = 15pF

2468

Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10

-3

inch)

METALLIZATION: Thickness: 11kÅ− 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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