Datasheet CD4015BMSFN3295 Datasheet (Intersil Corporation)

7-89

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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CD4015BMS

CMOS Dual 4-Stage Static Shift Register

With Serial Input/Parallel Output

Pinout

CD4015BMS

TOP VIEW

Functional Diagram

14

15

16

9

13
12
11
10

1
2
3
4
5

7

6

8

CLOCK B

Q4B
Q3A
Q2A
Q1A

RESET A

VSS

DATA A

VDD

RESET B
Q1B
Q2B
Q3B
Q4A
CLOCK A

DATA B

DATA A

CLOCK A

RESET A

DATA B

CLOCK B

RESET B

Q1A
Q2A
Q3A
Q4A

Q1B

Q2B

Q3B

Q4B

VSS

VDD

7
9
6

15

1

14

5
4
3
10
13
12
11
2

16

8

4

STAGE

4

STAGE

Features

• High-Voltage Type (20V Rating)

• Medium Speed Operation 12MHz (typ.) Clock Rate at
VDD - VSS = 10V

• Fully Static Operation

• 8 Master-Slave Flip-Flops Plus Input and Output Buffering

• 100% Tested For Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

• Maximum Input Current of 1µA at 18V Over Full Pack­age-Temperature Range; 100nA at 18V and 25

o

C

• Noise Margin (Full Package-Temperature Range) =

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”

Applications

• Serial-Input/Parallel-Output Data Queueing

• Serial to Parallel Data Conversion

• General-Purpose Register

Description

CD4015BMS consists of two identical, independent, 4-stage
serial-input/parallel output registers. Each register has inde­pendent CLOCK and RESET inputs as well as a single serial
DATA input. “Q” outputs are available from each of the four
stages on both registers. All register stages are D type, mas­ter-slave flip-flops. The logic level present at the DATA input
is transferred into the first register stage and shifted over one
stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line.
Register expansion to 8 stages using one CD4015BMS
package, or to more than 8 stages using additional
CD4015BMS’s is possible.

The CD4015BMS is supplied in these 16 lead outline pack­ages:

Braze Seal DIP H4X
Frit Seal DIP H1F
Ceramic Flatpack H6W

December 1992

File Number

3295

7-90

Specifications CD4015BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55

o

C to +125oC

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65

o

C to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265

o

C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum

Thermal Resistance . . . . . . . . . . . . . . . . θ

ja

θ

jc

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70

o

C/W 20oC/W

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55

o

C to +100oC (Package Type D, F, K). . . . . . 500mW

For TA = +100

o

C to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25

o

C-10µA

2 +125oC - 1000 µA

VDD = 18V, VIN = VDD or GND 3 -55oC-10µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25

o

C -100 - nA

2 +125oC -1000 - nA

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

2 +125oC - 1000 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD/2

VOL <
VDD/2

V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low
(Note 2)

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

Input Voltage High
(Note 2)

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

Input Voltage Low
(Note 2)

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

1, 2, 3 +25oC, +125oC, -55oC- 4 V

Input Voltage High
(Note 2)

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

1, 2, 3 +25oC, +125oC, -55oC11 - V

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs

3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.

7-91

Specifications CD4015BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1, 2)

GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Propagation Delay
Clock To Q

TPHL1
TPLH1

VDD = 5V, VIN = VDD or GND 9 +25oC - 320 ns

10, 11 +125oC, -55oC - 432 ns

Propagation Delay
Reset To Q

TPHL2 VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns

10, 11 +125oC, -55oC - 540 ns

Transition Time TTHL

TTLH

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

10, 11 +125oC, -55oC - 270 ns

Maximum Clock Input
Frequency

FCL VDD = 5V, VIN = VDD or GND 9 +25oC 3 - MHz

10, 11 +125oC, -55oC 3/1.35 - MHz

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

+125oC - 150 µA

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

+125oC - 300 µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

+125oC - 600 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC

-50mV

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC

-50mV

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC

4.95 - V

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC

9.95 - V

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

-55oC 0.64 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

-55oC 1.6 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

-55oC 4.2 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

-55oC - -0.64 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

-55oC - -2.0 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

-55oC - -1.6 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

-55oC - -4.2 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,

-55oC

-3V

7-92

Specifications CD4015BMS

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

-55oC

+7 - V

Propagation Delay
Clock To Q

TPHL1
TPLH1

VDD = 10V 1, 2, 3 +25

o

C - 160 ns

VDD = 15V 1, 2, 3 +25

o

C - 120 ns

Propagation Delay
Reset To Q

TPHL2 VDD = 10V 1, 2, 3 +25oC - 200 ns

VDD = 15V 1, 2, 3 +25oC - 160 ns

Transition Time TTHL

TTLH

VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns

Maximum Clock Input
Frequency

FCL VDD = 10V 1, 2, 3 +25oC 6 - MHz

VDD = 15V 1, 2, 3 +25oC 8.5 - MHz

Minimum Data Setup
Time

TS VDD = 5V 1, 2, 3 +25oC - 70 ns

VDD = 10V 1, 2, 3 +25oC - 40 ns
VDD = 15V 1, 2, 3 +25oC - 30 ns

Clock Rise and Fall Time TRCL

TFCL

VDD = 5V 1, 2, 3 +25oC-15µs
VDD = 10V 1, 2, 3 +25oC-15µs
VDD = 15V 1, 2, 3 +25oC-15µs

Minimum Clock Pulse
Width

TWCL VDD = 5V 1, 2, 3 +25oC - 180 ns

VDD = 10V 1, 2, 3 +25oC - 80 ns
VDD = 15V 1, 2, 3 +25oC - 50 ns

Minimum Reset Pulse
Width

TWR VDD = 5V 2, 3 +25oC - 200 ns

VDD = 10V 2, 3 +25oC - 80 ns
VDD = 15V 2, 3 +25oC - 60 ns

Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage

Delta

∆VNTH VDD = 10V, ISS= -10µA 1, 4 +25oC-±1V

P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage

Delta

∆VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

VDD/2

VOL <
VDD/2

V

VDD = 3V, VIN = VDD or GND

Propagation Delay Time TPHL

TPLH

VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

+25oC

Limit

ns

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

3. See Table 2 for +25oC limit.

4. Read and Record

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

7-93

Specifications CD4015BMS

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

CONFORMANCE GROUP

MIL-STD-883

METHOD GROUP A SUBGROUPS READ AND RECORD

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

CONFORMANCE GROUPS

MIL-STD-883

METHOD

TEST READ AND RECORD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION OPEN GROUND VDD 9V ± -0.5V

OSCILLATOR

50kHz 25kHz

Static Burn-In 1
Note 1

2 - 5, 10 - 13 1, 6 - 9, 14, 15 16

Static Burn-In 2
Note 1

2 - 5, 10 - 13 8 1, 6, 7, 9, 14 - 16

Dynamic Burn­In Note 1

- 6, 8, 14 16 2 - 5, 10 - 13 1, 9 7, 15

Irradiation
Note 2

2 - 5, 10 - 13 8 1, 6, 7, 9, 14 - 16

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

94

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
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Specifications CD4015BMS

Logic Diagram

FIGURE 1. CD4015BMS LOGIC DIAGRAM

TRUTH TABLE

CL D R Q1 Qn

0 0 0 Qn-1
1 0 1 Qn-1
X 0 Q1 Qn (No Change)

XX100

X = Don’t care Case

DQ

QCL

R

p
n

CL

CL

D

DQ
CL

Q

R

CL

CL

Q

DQ

QCL

R

DQ

QCL

R

DQ

QCL

R

p
n

CL

CL

p
n

CL

CL

p
n

CL

CL

VDD

VSS

CL

R

Q

13Q1 (5) 12Q2 (4) 11Q3 (3) 2Q4 (10)

15

DATA

(7)

*

1

CLOCK

(9)

*

14

RESET

(6)

*

*ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION
NETWORK

≡

7-95

CD4015BMS

Typical Performance Characteristics

FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE

FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

10V

5V

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

0 5 10 15

15

10

5

20

25

30

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

10V

5V

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

15

12.5

10

7.5

5

2.5

0 5 10 15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-10V

-15V

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

0

-5

-10

-15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-20

-25

-30

0-5-10-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

-10V

-15V

AMBIENT TEMPERATURE (TA) = +25oC

0

-5

-10

-15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

0-5-10-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

AMBIENT TEMPERATURE (TA) = +25oC

LOAD CAPACITANCE (CL) (pF)

0 40 60 80 10020

0

50

100

150

200

SUPPLY VOLTAGE (VDD) = 5V

10V
15V

TRANSITION TIME (tTHL, tTLH) (ns)

AMBIENT TEMPERATURE (TA) = +25oC

LOAD CAPACITANCE (CL) (pF)

0 40 60 80 10020

50

100

150

200

SUPPLY VOLTAGE (VDD) = 5V

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

15V

10V

250

7-96

CD4015BMS

Chip Dimensions and Pad Layout

FIGURE 8. TYPICAL POWER DISSIPATION AS

A FUNCTION OF FREQUENCY

Typical Performance Characteristics (Continued)

CL = 50pF
CL = 15pF

AMBIENT TEMPERATURE (TA) = +25oC

SUPPLY VOLTAGE (VDD) = 15V

10V

5V

10V

tr, tf = 20ns
RL = 200kΩ

1

2468102468

10

2

2468

10

3

2468

10

4

2468

CLOCK INPUT FREQUENCY (fCL) (kHz)

10

5

10

10

2

2

8
6
4

10

3

2

8
6
4

10

4

2

8
6
4

10

5

2

8
6
4

POWER DISSIPATION (PD) (µW)

Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10

-3

inch)

METALLIZATION: Thickness: 1 1kÅ− 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
DIE SIZE: X = 80 (77 - 85) = (1.956 - 2.159)

Y = 98 (95 - 103) = (2.413 - 2.616)

13

3

14

15

12

1110

2

1

16

4

5

6

7

8 9

98

80