Datasheet CA3524F, CA1524F, CA1524E Datasheet (Intersil Corporation)

CA1524, CA2524

CA2524 IS AN OBSOLETE

ODUCT

PR

October 2000

Features

• Complete PWM Power Control Circuitry

• Separate Outputs for Single-Ended or Push-Pull
Operation

• Line and Load Regulation. . . . . . . . . . . . . . . 0.2%(Typ)

• Internal Reference Supply with 1% (Max) Oscillator
and Reference Voltage Variation Over Full
Temperature Range

• Standby Current of Less Than 10mA

• Frequency of Operation Beyond 100kHz

• Variable-Output Dead Time of 0.5µs to 5µs

•Low V

Over the Temperature Range

CE(sat)

Applications

• Positive and Negative Regulated Supplies

• Dual-Output Regulators

• Flyback Converters

• DC-DC Transformer-Coupled Regulating Converters

• Single-Ended DC-DC Converters

• Variable Power Supplies

CA3524

Regulating Pulse Width Modulator

Description

The CA1524 and CA3524 are silicon monolithic integrated
circuits designed to provide all the control circuitry for use in
a broad range of switching regulator circuits.

The CA1524 and CA3524 have all the features of the indus­try types SG1524, SG2524, and SG3524, respectively. A
block diagram of the CA1524 series is shown in Figure 1.
The circuit includes a zener voltage reference, transconduc­tance error amplifier, precision R-C oscillator, pulse-width
modulator, pulse-steering flip-flop, dual alternating output
switches, and current-limiting and shutdown circuitry. This
device can be used for switching regulators of either polarity,
transformer-coupled dc-dc converter, transformerless volt­age doublers, dc-ac power inverters, highly efficient variable
power supplies, and polarity converter, as well as other
power-control applications.

Ordering Information

PART

NUMBER

CA1524E -55oC to +125oC 16 Lead Plastic DIP
CA1524F -55oC to +125oC 16 Lead CerDIP
CA2524E 0oC to +70oC 16 Lead Plastic DIP
CA2524F 0oC to +70oC 16 Lead CerDIP
CA3524E 0oC to +70oC 16 Lead Plastic DIP
CA3524F 0oC to +70oC 16 Lead CerDIP

TEMPERATURE

RANGE PACKAGE

Pinout

CA1524, CA3524

(PDIP, CERDIP)

TOP VIEW

V

16

REF

15

V+

14

EMITTER B
COLLECTOR B

13

12

COLLECTOR A
EMITTER A

11

10

SHUTDOWN
COMPENSATION

9

AND COMPARATOR

NON-

R

C

GND

1

2

3

4

5

6

T

7

T

8

1

INV. INPUT

INV. INPUT

OSC OUT

(+) C.L.
SENSE

(-) C.L.

SENSE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143

| Copyright © Intersil Corporation 2000

File Number

1239.4

Functional Block Diagram

CA1524, CA2524, CA3524

15

16

3

6

7

1

2

10

V+

V

OSC OUT

R

C

INV. INPUT

NON-INV.
INPUT

REF

T

T

SHUTDOWN

REFERENCE
REGULATOR

5V

+5V

OSCILLATOR

-

ERROR

AMP

+

1kΩ

10kΩ

COMPARATOR

+5V

+5V TO ALL
INTERNAL CIRCUITS

+5V

FLIP

FLOP

+5V

+5V

C.L.

+

-

COMPENSATION AND COMPARATOR

+ SENSE

- SENSE

C

A

12

S

A

11

E

A

C

B

13

S

B

14

E

B

4

5

9

Test Circuit

8 - 40V

ls

8

0.1µF

V+
15

16

3

GND

2kΩ

1W

2kΩ
1W

OUT A

12

OUT B

13

CA1524

11

14

5410912768

2kΩ

2kΩ

R

C

T

T

10kΩ

2kΩ

10

kΩ

1kΩ

2

Specifications CA1524, CA2524, CA3524

Absolute Maximum Ratings Thermal Information

Input Voltage (Between VIN and GND Terminals). . . . . . . . . . . . 40V

Operating Voltage Range (VIN to GND) . . . . . . . . . . . . . . . .8 to 40V

Output Current Each Output:

(Terminal 11, 12 or 13, 14) . . . . . . . . . . . . . . . . . . . . . . . . .100mA

Output Current (Reference Regulator). . . . . . . . . . . . . . . . . . .50mA

Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance θ

JA

Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . 100oC/W

Device Dissipation

Up to TA = +25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W

Above TA = +25oC . . . . . . . . . . . . . . .Derate Linearly at 10mW/oC

Operating Temperature Range . . . . . . . . . . . . . . . .-55

Storage Temperature Range. . . . . . . . . . . . . . . . . . -65

o

C to +125oC

o

C to +150oC

Lead Temperature (During Soldering)

At distance 1/16 ± in. (1.59mm ±0.79mm)

from case for 10s Max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC

Electrical Specifications T

= -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and

A

f = 20kHz, Unless Otherwise Stated.

CA1524, CA2524 CA3524

PARAMETER TEST CONDITIONS

UNITSMIN TYP MAX MIN TYP MAX

REFERENCE SECTION
Output Voltage 4.8 5 5.2 4.6 5 5.4 V
Line Regulation V+ = 8 to 40V - 10 20 - 10 30 mV
Load Regulation IL = 0 to 20mA - 20 50 - 20 50 mV
Ripple Rejection f = 120Hz, TA = 25oC - 66 - - 66 - db
Short Circuit Current Limit V
Temperature Stability Over Operating Temperature

= 0, TA = 25oC - 100 - - 100 - mA

REF

- 0.3 1 - 0.3 1 %

Range
Long Term Stability TA = 25oC - 20 - - 20 - mV/khr
OSCILLATOR SECTION
Maximum Frequency CT = 0.001µF, RT = 2KΩ - 300 - - 300 - kHz
Initial Accuracy RT and CT Constant - 5 - - 5 - %
Voltage Stability V+ = 8 to 40V, TA = 25oC--1--1%
Temperature Stability Over Operating Temperature

--2--2 %

Range
Output Amplitude Terminal 3, TA = 25oC - 3.5 - - 3.5 - V
Output Pulse Width (Pin 3) CT = 0.01µF, TA = 25oC - 0.5 - - 0.5 - µs
Ramp Voltage Low (Note 1) Pin 7 - 0.6 - - 0.6 - V
Ramp Voltage High (Note 1) Pin 7 - 3.5 - - 3.5 - V
Capacitor Charging Current Range Pin 7 (5-2 VBE)/R

T

0.03 - 2 0.03 - 2 mA
Timing Resistance Range Pin 6 1.8 - 120 1.8 - 120 kΩ
Charging Capacitor Range Pin 7 0.001 - 0.1 0.001 - 0.1 µF
Dead Time Expansion Capacitor on

Pin 3 100 - 1000 100 - 1000 pF

Pin 3 (when a small osc. cap is used)
ERROR AMPLIFIER SECTION
Input Offset Voltage VCM = 2.5V - 0.5 5 - 2 10 mV
Input Bias Current VCM = 2.5V - 1 10 - 1 10 µA
Open Loop Voltage Gain 72 80 - 60 80 - dB
Common Mode Voltage TA = 25oC 1.8 - 3.4 1.8 - 3.4 V
Common Mode Rejection Ratio TA = 25oC - 70 - - 70 - dB
Small Signal Bandwidth AV = 0dB, TA = 25oC - 3 - - 3 - MHz

3

Specifications CA1524, CA2524, CA3524

Electrical Specifications T

PARAMETER TEST CONDITIONS

Output Voltage TA = 25oC 0.5 - 3.8 0.5 - 3.8 V
Amplifier Pole - 250 - - 250 - Hz
Pin 9 Shutdown Current External Sink - 200 - - 200 - µA
COMPARATOR SECTION
Duty Cycle % Each Output On 0 - 45 0 - 45 %
Input Threshold Zero Duty Cycle - 1 - - 1 - V
Input Threshold Max. Duty Cycle - 3.5 - - 3.5 - V
Input Bias Current - 1 - - 1 - µA
CURRENT LIMITING SECTION
Sense Voltage for 25% Output Duty

Cycle

Sense Voltage T.C. - 0.2 - - 0.2 - mV/oC
Common Mode Voltage -1 - +1 -1 - +1 V
Rolloff Pole of R51 C3 + Q64 - 300 - - 300 - Hz
OUTPUT SECTION (EACH OUTUT)
Collector-Emitter Voltage 40 - - 40 - - V
Collector Leakage Current VCE = 40V - 0.1 50 - 0.1 50 µA
Saturation Voltage V+ = 40V, IC = 50mA - 0.8 2 - 0.8 2 V
Emitter Output Voltage V+ = 20V 17 18 - 17 18 - V
Rise Time RC = 2KΩ, TA = 25oC - 0.2 - - 0.2 - µs
Fall Time RC = 2KΩ, TA = 25oC - 0.1 - - 0.1 - µs
Total Standby Current: (Note 2) I

NOTES:

1. Ramp voltage at Pin 7 where t = OSC period in microseconds

Output frequency at each output transistor is half OSC frequency when each output is used separately and is equal to the OSC frequency
when each output is connected in parallel.

2. Excluding oscillator charging current, error and current limit dividers, and with outputs open.

High
Low

= -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and

A

f = 20kHz, Unless Otherwise Stated. (Continued)

CA1524, CA2524 CA3524

Terminal 9 = 2V with Error
Amplifier Set for Max Out,
TA = 25oC

V+ = 40V - 4 10 - 4 10 mA

S

t

t ≅ RTCT with CT in microfarads and RT in ohms.

190 200 210 180 200 220 mV

UNITSMIN TYP MAX MIN TYP MAX

4

Schematic Diagram

R1

500

Q1

Q2

Q3 Q4

R2

2.7K

R3

D1

8

GND

Q42 Q43

6.3K

RA

5.3K

RB

4.8K

R4

500

CA1524, CA2524, CA3524

R5
1K

Q7

Q6

Q9

D2

R6

500

Q10

OSC SECTION

RC

10K

QA

Q5 Q12

Q47 Q48

Q13

Q11

R7
1K

20pF

C1

RD

10K 1.9K

R9
500

R43

7.4K

Q16

Q19

Q14 Q15

R14
450

R8

8.4K

R10
1K

R11
500

Q17

R12
10K

STEERING

FLIP-FLOP

N

R13

6Ω

C4

PULSE

C2

20pF

+

P

Q18

R15
25K

Q20

15

V

IN

R16

16.2K

R17

R18

18.7

18.7

K

K

Q21 Q23

R19

R18

18.7

18.7

K

K

Q22

ERROR

Q59 Q60

Q24

AMP

V

+5V

A

B

16

REF

C

D
E

F
G
H

I

6

R

T

7

C

T

Q45

Q44

Q49 Q50

Q46

R39
1K

R41
24K

R40

560

Q51

R42

19.8K

Q52

R44

1.8K

R45
25K

Q53

Q54

Q55

INV.

IN

OSC.

OUT

3

R46

3.3K

Q56 Q57

Q58 Q62

R471KR48

21

2K

Q61

NON-INV.
INPUT

J

K
L

5

CA1524, CA2524, CA3524

Schematic Diagram

A

OUTPUT A

B

COLL. A

EMIT A

C

D
E

F

G
H

I

12

11

(Continued)

Q34

R31

4.7Ω

R21

43.3K

R23

8.7K
Q26

Q27

R24

5K

R32
1K

R33
200

R34
500

Q35

CA

1pF

R25

5K

R52

1.96K

Q36

D3 D4

RE

500

Q37 Q38

R26

5K

Q33

Q29

R27

5K

R54

1.96K

Q39

RF
500

NORNOR

Q30

COMPARATOR

CB

1pF

Q40

Q31

OUTPUT B

R36

200

R37

1K

R35

500

R30

43.3K

R28

8.7K

R38

4.7Ω

Q41

13

14

COLL. B

EMIT B

COMP

10 9

J

R49
1K

Q63

R50
10K

K

L

C3

45pF

Q64

CURRENT

LIMIT

SECTION

5 4

(-) C.L.

SENSE

Q65 Q67

R53

1.8K

R51
10K

Q66

(+) C.L.
SENSE

Q70Q68

Q68 Q71

Q73Q72

6

CA1524, CA2524, CA3524

Circuit Description

Voltage Reference Section

The CAl524 series contains an internal series voltage regu­lator employing a zener reference to provide a nominal 5-volt
output, which is used to bias all internal timing and control
circuitry. The output of this regulator is available at terminal
l6 and is capable of supplying up to 50mA output current.

Figure 1 shows the temperature variation of the reference
voltage with supply voltages of 8V to 40V and load currents
up to 20mA. Load regulation and line regulation curves are
shown in Figures 2 and 3, respectively.

5.02

5.00

4.98

4.96

REFERENCE VOLTAGE (V)

-60 -40 -20 0 20 40 60 80 100 120 140
AMBIENT TEMPERATURE (

o

FIGURE 1. TYPICAL REFERENCE VOLTAGE AS A FUNCTION

OF AMBIENT TEMPERATURE

V+ = 40V, IL = 0mA
V+ = 20V, IL = 0mA
V+ = 40V, IL = 20mA
V+ = 8V, IL = 0mA

V+ = 20V, IL = 20mA
V+ = 8V, IL = 20mA

C)

Osclllator Section

Transistors Q42, Q43 and Q44, in conjunction with an
external resistor R
into an external capacitor C

, establishes a constant charging current

T

to provide a linear rampvoltage

T

at terminal 7. The ramp voltage has a value that ranges from

0.6V to 3.5V and is used as the reference for the comparator
in the device. The charging current is equal to (5-2V
approximately 3.6/R
30pA to 2mA by varying R

and should be kept within the range of

T

. The discharge time of CTdeter-

T

)/RTor

BE

mines the pulse width of the oscillator output pulse at termi­nal 3. This pulse has a practical range of 0.5µsto5µs for a
capacitor range of 0.001 to 0.1µF. The pulse has two internal
uses: as a dead-time control of blanking pulse to the output
stages to assure that both outputs cannot be on simulta­neously and as a trigger pulse to the internal flip-flop which
controls the switching of the output between the two output
channels. The output dead-time relationship is shown in Fig­ure 4. Pulse widths less than 0.5µs may allow false trigger­ing of one output by removing the blanking pulse prior to a
stable state in the flip-flop.

100

TA = +25oC
V+ = 8V - 40V

10

5.1

4.9

4.7

4.5

4.3
TA = +25oC

4.1
V+ = 20V

3.9

REFERENCE VOLTAGE (V)

3.7

3.5

0 8 16 24 32 40 48 56 64 72 80

REFERENCE OUTPUT CURRENT (mA)

V+ = 20V

V+ = 40V

V+ = 8V

FIGURE 2. TYPICAL REFERENCE VOLTAGE AS A FUNCTION

OF REFERENCE OUTPUT CURRENT

8

TA = +25oC

7
6

5
4

3
2

REFERENCE VOLTAGE (V)

1
0

0

10 20 30 40

SUPPLY VOLTAGE, V+ (V)

FIGURE 3. TYPICAL REFERENCE VOLTAGE AS A FUNCTION

OF SUPPLY VOLTAGE

1.0

OUTPUT DEAD TIME (µs)

0.1

0.0001 0.001 0.01 0.1 1.0
TIMING CAPACITOR, C

(µF)

T

FIGURE 4. TYPICAL OUTPUT STAGE DEAD TIME AS A

FUNCTION OF TIMING CAPACITOR VALUE

If a small value of CTmust be used, the pulse width can be
further expanded by the addition of a shunt capacitor in the
order of 100pF but no greater than 1000pF, from terminal 3
to ground. When the oscillator output pulse is used asa sync
input to an oscilloscope, the cable and input capacitances
may increase the pulse width slightly. A 2-KΩ resistor at
terminal 3 will usually provide sufficient decoupling of the
cable. The upper limit of the pulsewidth is determined by the
maximum duty cycle acceptable.

The oscillator period is determined by R
approximate value of t = R

, where RTis in ohms, CTis in

TCT

and CT, with an

T

µF, and t is in µs. Excess lead lengths, which produce stray
capacitances, should be avoided in connecting R

and CTto

T

their respective terminals. Figure 5 provides curves for
selecting these values for a wide range of oscillator periods.
For series regulator applications, the two outputs can be
connected in parallel for an effective 0-90% duty cycle with
the output stage frequency the same as the oscillator
frequency. Since the outputs are separate, push-pull and
flyback applications are possible. The flip-flop divides the
frequency such that the duty cycle of each output is 0-45%
and the overall frequency is half that of the oscillator. Curves

7

CA1524, CA2524, CA3524

of the output duty cycle as a function of the voltage at
terminal 9 are shown in Figure 7. To synchronize two or
more CAl524’s, one must be designated as master, with R
CTset for the correct period. Each of the remaining units
(slaves) must have a C
and approximately a 1010 longer R

of 1/2 the value used in the master

T

period than the mas-

TCT

ter. Connecting terminal 3 together on all units assures that
the master output pulse, which occurs first and has a wider
pulse width, will reset the slave units.

TA = +25oC

5

10

V+ = 8V - 40V

(Ω)

T

10

TIMING RESISTANCE, R

10

C
CT = 0.002µF

= 0.005µF

C

T

4

3

1

= 0.001µF

T

CT = 0.01µF

10

OSCILLATOR PERIOD, t (µs)

2

10

CT = 0.02µF

C

= 0.05µF

T

C

= 0.1µF

T

3

10

4

10

FIGURE 5. TYPICAL OSCILLATOR PERIOD AS A FUNCTION

OF RT AND C

T

Error AmplIfIer Section

The error amplifier consists of a differential pair (Q56,Q57)
with an active load (Q61 and Q62) forming a differential
transconductance amplifier. Since Q61 is driven by a
constant current source, Q62, the output impedance R

OUT

terminal 9, is very high (≅ 5MΩ).
The gain is:

= gmR = 8 lC R/2KT = 104,

A

V

R

OUT RL

where R =

Since R

R

OUT

R

is extremely high, the gain can be easily

OUT

, RL = ∞, AV∝ 10

+

L

reduced from a nominal 10

4

(80dB) by the addition of an

4

external shunt resistor from terminal 9 to ground as shown in
Figure 6.

80

RL = ∞

70

60

50

R

= 3MΩ

L

RL = 1MΩ

RL = 300kΩ

OPEN LOOP GAIN

PHASE ANGLE (DEGREES)

The output amplifier terminal is also used to compensate the
system for ac stability. The frequency response and phase
shift curves are shown in Figure 7. The uncompensated

T

amplifier has a single pole at approximately 250Hz and a
unity gain cross-over at 3MHz.

Since most output filter designs introduce one or more
additional poles at a lower frequency, the best network to
stabilize the system is a series RC combination at terminal9
to ground. This network should be designed to introduce a
zero to cancel out one of the output filter poles. A good start­ing point to determine the external poles is a 1000-pF
capacitor and a variable series 50-KΩ potentiometer from
terminal 9 to ground. The compensation point is also a
convenient place to insert any programming signal to
override the error amplifier. internal shutdown and current
limiting are also connected at terminal 9. Any external circuit
that can sink 200µA can pull this point to ground and shut off
both output drivers.

While feedback is normally applied around the entire regula­tor, the error amplifier can be used with conventional
operational amplifier feedback and will be stable in either the
inverting or non-inverting mode. Input common-mode limits
must be observed; if not, output signal inversion may result.
The internal 5V reference can be used for conventional regu­lator applications if divided as shown in Figure 8. If the error
amplifier is connected as a unity gain amplifier, a fixed duty
cycle application results.

TA = +25oC

,

FIGURE 7. TYPICAL DUTY CYCLE AS A FUNCTION OF

V+ = 20V

48
40
32
24
16

8

OUTPUT DUTY CYCLE (%)

0

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4

CT = 2700pF
R

= 6.19k

T

f

= 60kHz

OSC

CT =1000pF
R

= 5k

T

f

= 20kHz

OSC

COMPARATOR VOLTAGE (V)

COMPARATOR VOLTAGE (AT TERMINAL 9).

1.1

1.0

RL =100kΩ

40

o

0

VOLTAGE GAIN (dB)

90
50

5

10

10 10

OPEN LOOP PHASE

2

3

10

FREQUENCY (Hz)

4

10

FIGURE 6. OPEN-LOOP ERROR AMPLIFIER RESPONSE

CHARACTERISTICS.

0.9

0.8

o

OUTPUT SATURATION VOLTAGE (V)

0.7

-75 -50 -25 0 25 50 75 100 125 150 175
AMBIENT TEMPERATURE (oC)

FIGURE 8. TYPICAL OUTPUT SATURATION VOLTAGE AS A

FUNCTION OF AMBIENT TEMPERATURE.

8

CA1524, CA2524, CA3524

Output Section

The CA1524 series outputs are two identical n-p-n
transistors with both collectors and emitters uncommitted.
Each output transistor has antisaturation circuitry that
enables a fast transient response for the wide range of
oscillator frequencies. Current limiting of the output section
is set at 100mA for each output and 100mA total if both
outputs are paralleled. Having both emitters and collectors
availableprovides the versatility to drive either n-p-n or p-n-p
external transistors. Curves of the output saturation voltage
as a function of temperature and output current are shown in
Figures 8 and 9, respectively. There are a number of output
configurations possible in the application of the CA1524 to
voltage regulator circuits which fall into three basic
classifications:

1. Capacitor-diode coupled voltage multipliers

2. Inductor-capacitor single-ended circuits

3. Transformer-coupled circuits

2.0
TA = +25oC
V+ = 8V to 40V

1.5

1.0

The internal 5V reference can be used for conventional regu­lator applications if divided as shownin Figure 11. Ifthe error
amplifier is connected as a unity gain amplifier, a fixed duty
cycle application results.

V

REF

5K

5K

R1

GND

V

REF

5K

5K

GND

FIGURE 11. ERROR AMPLIFIER BIASING CIRCUITS

R1

R2

2

1

2

+

-

2.5V (R1 + R2)

V

O

R1R2

R1 + R2

+

-

1

R2

POSITIVE
OUTPUT
VOLTAGES

R1
= 2.5KW

NEGATIVE
OUTPUT
VOLTAGES

0.5

OUTPUT SATURATION VOLTAGE (V)

0

0 20 40 60 80 100

OUTPUT CURRENT, I

(mA)

L

FIGURE 9. TYPICAL OUTPUT SATURATION VOLTAGE AS A

FUNCTION OF OUTPUT CURRENT

Device Application Suggestions

For higher currents,the circuit of Figure 10 may be used with
an external p-n-p transistor and bias resistor. The internal
regulator may be bypassed for operation from a fixed 5V
supply by connecting both terminals 15 and 16 to the input
voltage, which must not exceed 6V.

Q1

IL TO I

A

DEPENDING
ON CHOICE

+

-

FOR Q1

V

REF

V+

GND

100Ω

15

CA1524

REFERENCE

SECTION

8

16

10µF

FIGURE 10. CIRCUIT FOR EXPANDING THE REFERENCE

CURRENT CAPABILITY

16

V

REF

V+ CANNOT
EXCEED 6V

V

T

15

CA1524

REFERENCE

SECTION

8

NOTE: V+ Should Be in the 5V Range

And Must Not Exceed 6V

FIGURE 12. CIRCUIT TO ALLOW EXTERNAL BYPASS OF THE

REFERENCE REGULATION

To provide anexpansion of the dead time without loading the
oscillator, the circuit of Figure 13 may be used.

16

5KΩ

8

FIGURE 13. CIRCUIT FOR EXPANSION OF DEAD TIME, WITH-

OUT USING A CAPACITOR ON PIN 3 OR WHEN A
LOW VALUE OSCILLATOR CAPACITOR IS USED

9

9

CA1524, CA2524, CA3524

V

= 5V

I

MAX

ISC=

V

TH

O

VTH +

WHERE

V

OR2

R1 + R2

I

=

()

R

S

V

TH

R

S

= 200mV

//S

S

A

B

-

+

SENSE

R1

R2

RS

5

4

FIGURE 14. FOLDBACK CURRENT-LIMITING CIRCUIT USED

TO REDUCE POWER DISSIPATION UNDER
SHORTED OUTPUT CONDITIONS

D1

V+

V+

V+

S

A

S

B

D1

S

A

S

B

D1

S

A

S

B

+V

O

V+ > V

O

+V

O

V+ < V

O

-V

O

| V+ | > | VO |

TABLE 1. INPUT vs. OUTPUT VOLTAGE, AND FEEDBACK

RESISTOR VALUES FOR I

= 40mA (FOR CAPACI-

L

TOR-DIODE OUTPUT CIRCUIT IN FIGURE 18)

VO (V) R2 (KΩ) V+ (Min.) (V)

-0.5 6 8

-2.5 10 9

-3 11 10

-4 13 11

-5 15 12

-6 17 13

-7 19 14

-8 21 15

-9 23 16

-10 25 17

-11 27 18

-12 29 19

-13 31 20

-14 33 21

-15 35 22

-16 37 23

-17 39 24

-18 41 25

-19 43 26

-20 45 27

V+

V

O

NOTE: Diode D1 Is Necessary To Prevent Reverse

Emitter-Base Breakdown of Transistor Switch SA.

FIGURE 15. CAPACITOR-DIODE COUPLED VOLTAGE

MULTIPLIER OUTPUT STAGES

S

A/SB

V+

V+

V+

SA/S

SA/S

B

B

V+ > V

V+ < V

+V

+V

-V

O

O

O

O

O

| V+ | < | VO |

FIGURE16. SINGLE-ENDEDINDUCTOR CIRCUITSWHERE THE

TWO OUTPUTS OF THE 1524 ARE CONNECTED IN
PARALLEL

S

A-B

FLYBACK

S

A

V+

S

B

PUSH-PULL

+

V

O

S

A

V+

S

B

CAN BE S

CAN DRIVEQ1

S

A

Q1

CAN BE S

CAN DRIVEQ2

S

B

Q2

­V+

+

V

O

-

FULL BRIDGE

FIGURE 17. TRANSFORMER-COUPLED OUTPUTS

V

O

OR

A

OR

B

10

CA1524, CA2524, CA3524

Applications (Note 1)

A capacitor-diode output filter is used in Figure 19 to convert
+15V
output transistors have built-in current limiting, no additional
current limiting is needed. Table 1 gives the required
minimum input voltage and feedback resistor values, R2, for
an output voltage.

Capacitor-Diode Output Circuit

A capacitor-diode output filter is used in Figure18 to convert
+15V
output transistors have built-in current limiting, no additional
current limiting is needed. Table 1 gives the required
minimum input voltage and feedback resistor values, R2, for
an output voltage range of -0.5V to -20V with an output
current of 40mA.

to -5VDCat output currents up to 50mA. Since the

DC

to -5VDCat output currents up to 50mA. Since the

DC

V+

+15V

5KΩ

5KΩ

0.1µF

2KΩ

0.01µF

R2
15KΩ

R1
5KΩ

6

1

1

1
2

1

16

1
6

1
7

1

3

1

10

1

CA3524

8

1

0.01µF

Single-Ended Switching Regulator

The CA1524 in the circuit of Figure 19 has both output
stages connected in parallel to produce an effective 0% ­90% duty cycle. Transistor Q1 is pulsed on and off by these
output stages. Regulation is achieved from the feedback
provided by R1 and R2 to the error amplifier which adjusts
the on-time of the output transistors according to the load
current being drawn. Various output voltages can be
obtained by adjusting R1 and R2. The use of an output
inductor requires an R-C phase compensation network to
stabilize the system. Current limitingis set at 1.9 amperesby
the sense resistor R3.

NOTE:

1. Foradditional information on the application of this device and a
further explanation of the circuits below, see Intersil Application
Note AN6915 “Application of the CA1524 series PWM lC”.

12

1

IN4001

11

1

13

1

14

1
4

1
5

1
9

1

20µF

IN4001

IN4001

50µF

-5V
20mA

R1 = 5KΩ

R1 ( | V

R2 =

| + 2.5)

O

(V

- 2.5)

REF

+28V

FIGURE 18. CAPACITOR-DIODE OUTPUT CIRCUIT

V+

0.9mH

RURD410

0.1Ω

3KΩ

5KΩ

R1
5KΩ

15

1

1

1
2

1

16

1
6

1
7

1

3

1

10

1

CA3524

8

1

12

11
13

14

1

1

1

1
4

1
5

1
9

1

2N6388

Q1

2KΩ

0.001µF

50KΩ

R2

5KΩ

5KΩ

0.1µF

0.02µF

V-

+5V IA

500µF

FIGURE 19. SINGLE-ENDED LC SWITCHING REGULATOR CIRCUIT

11

CA1524, CA2524, CA3524

Flyback Converter

Figure 20 shows a flyback converter circuit for generating a
dual 15V output at 20mA from a 5V regulated line.
Reference voltage is provided by the input and the internal
reference generator is unused. Current limiting in this circuit
is accomplished by sensing current in the primary line and
resetting the soft-start circuit.

Push-Pull Converter

The output stages of the CA1524 provide the drive for
transistors Q1 and Q2 in the push-pull application of Figure

21. Since the internal flip-flop divides the oscillator frequency
by two, the oscillator must be set at twice the output
frequency. Current limiting for this circuit is done in the
primary of transformer T1 so that the pulse width will be
reduced if transformer saturation should occur.

V+

+5V

100µF

+

25K

5K

Ω

Ω

1

5KΩ
5KΩ

2KΩ

0.02µF

1
2

1

16

1
6

1
7

1

3

1

10

1

15

1

CA3524

8

1

Low-Frequency Pulse Generator

Figure 22 showsthe CA1524 being used as a low-frequency
pulse generator. Since all components (error amplifier,
oscillator, oscillator reference regulator, output transistor
drivers) are on the lC, a regulated 5-V (or 2.5-V) pulse of 0%

- 45% (or 0% - 90%) on time is possible over a frequency
range of 150 to 500Hz. Switch S1 is used to go from a 5-V
output pulse (S1 closed) to a 2.5-V output pulse (S1 open)
with a duty cycle range of 0% to 45%. The output frequency
will be roughly half of the oscillator frequency when the
output transistors are not connected in parallel (75Hz to
250Hz, respectively). Switch S2 will allow both output stages
to be paralleled for an effective duty cycle of 0%-90% with
the output frequency range from 150 to 500Hz. The
frequency is adjusted by R1; R2 controls duty cycle.

RURD620

4.7µF

200Ω

0.1µF

620Ω

510Ω

2N2102

50T

20T

50T

RURD620

2N6290

CORE: FEROX CUBE
2213P - A250 - 387
OR EQUIVALENT

1Ω

50µF

50µF

300Ω

12

1

11

1

13

1

14

1

4

1
5

1
9

1

1MΩ

IN914

+

0.001µF

+15V

-15V

+28V

V+

5KΩ
5KΩ

0.1µF

0.01µF

5K

FIGURE 20. FLYBACK CONVERTER CIRCUIT

15

Ω

1

1
2

5KΩ

2KΩ

1

16

1
6

1
7

1

3

1

10

1

1

8

1

1KΩ

1W

12

1

11

1

13

1

14

1

4

1
5

1
9

1

0.001µF
20KΩ

1KΩ
1W

1KΩ

1KΩ

2N6292

2N6292

0.1µF

20T

20T

+
100µF

RURD620

5T

5T

RURD620

1mH

1500µF

+

5V
5A

FIGURE 21. PUSH-PULL TRANSFORMER-COUPLED CONVERTER

12

CA1524, CA2524, CA3524

FREQUENCY

ADJUSTMENT

R2

10K

2K

DUTY CYCLE
ADJUSTMENT

2K

20K

R1
50K

0.1µF

TO PIN 9

SILVER

MICA

1
2
3
4
5
6
7
8

+5

CA3524

V

REFERENCE

16
15
14
13
12
11
10

9

TO PIN 1

FIGURE 22. LOW-FREQUENCY PULSE GENERATOR

The Variable Switcher

The circuit diagram of theCA1524, used as a variableoutput
voltage power supply is shown in Figure 23. By connecting
the two output transistors in parallel, the duty cycle is
doubled, i.e., 0% - 90%. As the reference voltage level is

1.1K 1.1K

1

1

/2S1

1

/2S2

/2S1

TO PIN 13
OUTPUT 2

1

/2S2

SWITCH

OUTPUT 1A

OUTPUT 2A

OUTPUT

PULSES

DUTY

CYCLE

V+ = 9V

1.5K

1.5K

TO PIN 12
OUTPUT 1

S1 0V - 5V 0% - 45%
S2 - 0% - 90%

varied, the feedback voltage will track that level and cause
the output voltage to change according to the change in
reference voltage.

R3

10K

R4
5K

R5
2K

D1

D2 D4

D1-D4 - A15A

C7

0.1µF

R6
2K

R7

10K

VOLTAGE
CONTROL f

AC

IN

R8
2K

D3

V

36

DC

5100µF

100V

16 15 14 13 12 11 10 9

2N6385

(PNP DARLINGTON)

R1
1K

1W

CA1524

1234567 8

C8

0.1µF

Q1

R2

1.5
10W

0.01µF

R9

15K

1%

OSC

L1

20mH

D5
RURD410

10000µF

= 20KHz

C3

100V

C9
3300
pF
1%

L2

50mH

BIFILAR

WINDING

R10
16K

SILVER
MICA

C11

0.01µF

C10
1100pF

C4

0.1µF

7V - 30V
0A - 3A

V

OUT

C5
25µF

NON-POLAR

RETURN

C6
25µF

NON-POLAR

FIGURE 23. THE CA1524 USED AS A 0-5A, 7-30 V LABORATORY SUPPLY

13

Digital Readout Scale

CA1524, CA2524, CA3524

The CA1524 can be used as the driving source for an
electronic scale application. The circuit shown in Figures 24
and 25 uses half (Q2) of the CA1524 output in a low-voltage
switching regulator (2.2V) application to drive the LED’s
displaying the weight. The remaining output stage (Q1) is
used as a driver for the sampling plates PL1 and PL2. Since
the CA1524 contains a 5V internal regulator and a wide
operating range of 8V to 40V, a single 9V battery can power
the total system. The two plates, PL1 and PL2, are driven
with opposite phase signals (frequency held constant but
duty cycle may change) from the pulse-width modulator lC
(CA1524). The sensor, S, is located between the two plates.
Plates PL1, S and PL2 form an effective capacitance bridge­type divider network. As plate S is moved according to the

PL1

OSCILLATOR ≈ 20KHz

(PART OF CA1524)

FULL SCALE
NO WEIGHT

S

PL2

COUPLED TO
MECHANICAL

SCALE MECHANISM

AC
AMP

object’s weight, a change in capacitance is noted between
PL1, S and PL2. This change is reflected as a voltage to the
ac amplifier (CA3160). At the null position the signals from
PL1 and PL2 as detected by S are equal in amplitude, but
opposite in phase. As S is driven by the scale mechanism
down toward PL2, the signal at S becomes greater. The
CA3160 ac amplifier provides a buffer for the small signal
change noted at S. The output of the CA3160 isconverted to
a dc voltage by a peak-to-peak detector. A peak-to-peak
detector is needed, since the duty cycle of the sampled
waveform is subject to change.The detector outputis filtered
further and displayed via the CA3161E and CA3162E digital
readout system, indicating the weight on the scale.

CA3130

PEAK TO PEAK

DETECTOR

DISPLAY DRIVE

(PART OF CA1524)

LOW PASS

FILTER

DIGITAL METER

AND DISPLAY

DC

VOLTAGE

A
B
C

2.5V

ZERO

ADJUSTMENT

HIGH

INPUTS:

LOW

ADJUSTMENT

GAIN

11

10

50K

0.27

µF

8 12 149

13 7

10KΩ

FIGURE 24. BASIC DIGITAL READOUT SCALE

+5V

0.1
µF

5
3
4

DIGIT

DRIVERS
16

6

15 2

1

1

72

BCD

OUTPUTS

16

CA3161ECA3162E

8 3

MSD NSD LSD

13
12
11
10

9
15
14

POWER 2N2907
OR EQUIVALENT

COMMON­ANODE LED
DISPLAYS
(NOTE 1)

NOTE:

1. FAIRCHILD FND507 OR EQUIVALENT

FIGURE 25. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE (CONT’D)

14

CA1524, CA2524, CA3524

TO SCALE

MECHANISM

9V

5V

4.7K

39K

430K

4.7K

141516 13 12 11 10 9

CA1524

30K

200Ω

PL1

S

PL2

2N4037

100
MΩ

22MΩ

125µH

9V

470µF

3

22MΩ

2

200pF

1

8

+

CA3160

-

9V

7

4

10K

100µF

0.1µF

6
68K 6.2K

10K

10µF

910K 910K

2.5V

0.47
µF

2µF

2µF

300K

A
B
C

4.7K

4.7K

87654321

6.2K
4700pF

0.01µF

24K

FIGURE 26. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE

DIMENSIONS AND PAD LAYOUT FOR CA3524RH CHIP

NOTE: Dimensions in parentheses are in millimeters and are de­rived from the basic inch dimensions as indicated. Grid graduations
are in mils (10-3inch). The layout represents a chip when it is part of

the wafer. When the wafer is cut into chips, the cleavage angles are
57oinstead of 90owith respect to the face of the chip.Therefore, the
isolated chip is actually 7 mils (0.17mm) larger in both dimensions.

15

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly ,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli­able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

File Number

16