Datasheet CA3338, CA3338A Datasheet (Intersil Corporation)

August 1997

CA3338, CA3338A

CMOS Video Speed, 8-Bit,

50 MSPS, R2R D/A Converters

Features

• CMOS/SOS Low Power

• R2R Output, Segmented for Low “Glitch”

• CMOS/TTL Compatible Inputs

1

• Fast Settling: (Typ) to

/2 LSB . . . . . . . . . . . . . . . .20ns

• Feedthrough Latch for Clocked or Unclocked Use

• Accuracy (Typ). . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB

• Data Complement Control

• High Update Rate (Typ). . . . . . . . . . . . . . . . . . . . 50MHz

• Unipolar or Bipolar Operation

Applications

• TV/Video Display

• High Speed Oscilloscope Display

• Digital Waveform Generator

• Direct Digital Synthesis

Pinout

CA3338, CA3338A

(PDIP, SBDIP, SOIC)

TOP VIEW

Description

The CA3338 family are CMOS/SOS high speed R2R voltage
output digital-to-analog converters. They can operate from a
single +5V supply, at video speeds, and can produce
“rail-to-rail” output swings. Internal level shifters and a pin for
an optional second supply provide for an output range below
digital ground. The data complement control allows the inver­sion of input data while the latch enable control provides
either feedthrough or latched operation. Both ends of the
R2R ladder network are available externally and may be
modulated for gain or offset adjustments. In addition, “glitch”
energy has been kept very low by segmenting and thermom­eter encoding of the upper 3 bits.

The CA3338 is manufactured on a sapphire substrate to give
low dynamic power dissipation, low output capacitance, and
inherent latch-up resistance.

Ordering Information

PART

NUMBER

LINEARITY

(INL, DNL)

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

V

1

D7

2

D6

3

D5

4

D4

5

D3

6

D2

7

D1

8

V

SS

16
15
14
13
12
11
10

9

DD

LE
COMP
V

REF

V

OUT

V

REF

V

EE

D0

+

-

CA3338E ±1.0 LSB -40 to 85 16 Ld PDIP E16.3

CA3338AE ±0.75 LSB -40 to 85 16 Ld PDIP E16.3

CA3338D ±1.0 LSB -55 to 125 16 Ld SBDIP D16.3

CA3338AD ±0.75 LSB -55 to 125 16 Ld SBDIP D16.3

CA3338M ±1.0 LSB -40 to 85 16 Ld SOIC M16.3

CA3338AM ±0.75 LSB -40 to 85 16 Ld SOIC M16.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

10-11

File Number 1850.2

Functional Diagram

CA3338, CA3338A

V

DD

LE

COMP

D7

D6

D5

D4

D3

D2

D1

D0

V

SS

16

8R

15

3-BIT

14

1

2

3

4

5

6

7

9

8

LEVEL

SHIFTERS

TO 7-LINE

THERMOMETER

ENCODER

FEEDTHROUGH

LATCHES

8R

8R

8R

4R

4R

2R

2R

2R

2R

2R

2R

R ≅160Ω

R

R

R

R

R

R

R

2R

13

V

+

REF

12

V

OUT

11

V

-

REF

10

V

EE

10-12

CA3338, CA3338A

Absolute Maximum Ratings Thermal Information

DC Supply-Voltage Range . . . . . . . . . . . . . . . . . . . . . . -0.5V to +8V

(VDD - VSS or VDD - VEE, Whichever is Greater)

Input Voltage Range

Digital Inputs (LE, COMP D0 - D7). . . . VSS - 0.5V to VDD + 0.5V

Analog Pins (V

REF

+, V

REF

-, V

). . . . VDD - 8V to VDD + 0.5V

OUT

DC Input Current

Digital Inputs (LE, COMP, D0 - D7). . . . . . . . . . . . . . . . . . ±20mA

Recommended Supply Voltage Range. . . . . . . . . . . . . .4.5V to 7.5V

Operating Conditions

Temperature Range (TA)

Ceramic Package, D suffix . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Plastic Package, E suffix, M suffix . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

SBDIP Package. . . . . . . . . . . . . . . . . . 75 24

PDIP Package. . . . . . . . . . . . . . . . . . . 100 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . 100 N/A

Maximum Junction Temperature

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC

Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range, T

. . . . .-65oC to 150oC

STG

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Electrical Specifications T

= 25oC, VDD = 5V, V

A

+ = 4.608V, VSS = VEE = V

REF

- = GND, LE Clocked at 20MHz, RL≥ 1 MΩ,

REF

Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ACCURACY

Resolution 8 - - Bits
Integral Linearity Error See Figure 4

CA3338 - - ±1 LSB
CA3338A - - ±0.75 LSB

Differential Linearity Error See Figure 4

CA3338 - - ±0.75 LSB
CA3338A - - ±0.5 LSB

Gain Error Input Code = FF

, See Figure 3

HEX

CA3338 - - ±0.75 LSB
CA3338A - - ±0.5 LSB

Offset Error Input Code = 00

; See Figure 3 - - ±0.25 LSB

HEX

DIGITAL INPUT TIMING

Update Rate To Maintain1/2 LSB Settling DC 50 - MHz
Update Rate V
Set Up Time t
Set Up Time t
Hold Time t
Latch Pulse Width t
Latch Pulse Width t

SU1
SU2

H

W
W

OUTPUT PARAMETERS RL Adjusted for 1V
Output Delay t
Output Delay t
Rise Time t
Settling Time t

D1
D2

r

S

Output Impedance V

- = VEE = -2.5V, V

REF

+ = +2.5V DC 20 - MHz

REF

For Low Glitch - -2 - ns
For Data Store - 8 - ns
For Data Store - 5 - ns
For Data Store - 5 - ns
V

- = VEE = -2.5V, V

REF

P-P

+ = +2.5V - 25 - ns

REF

Output
From LE Edge - 25 - ns
From Data Changing - 22 - ns
10% to 90% of Output - 4 - ns
10% to Settling to1/2 LSB - 20 - ns

+ = 6V, VDD = 6V 120 160 200 Ω

REF

Glitch Area - 150 - pV/s
Glitch Area V

- = VEE = -2.5V,V

REF

+ = +2.5V - 250 - pV/s

REF

10-13

CA3338, CA3338A

Electrical Specifications T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

REFERENCE VOLTAGE

V

+ Range (+) Full Scale, Note 1 V

REF

V

- Range (-) Full Scale, Note 1 V

REF

V

+ Input Current V

REF

SUPPLY VOLTAGE

Static IDD or I

Dynamic IDD or I
Dynamic IDD or I
VDD Rejection 50kHz Sine Wave Applied - 3 - mV/V
VEE Rejection 50kHz Sine Wave Applied - 1 - mV/V
DIGITAL INPUTS D0 - D7, LE, COMP
High Level Input Voltage Note 1 2 - - V
Low Level Input Voltage Note 1 - - 0.8 V
Leakage Current - ±1 ±5 µA
Capacitance - 5 - pF

TEMPERATURE COEFFICIENTS

Output Impedance -

NOTE:

1. Parameter not tested. but guaranteed by design or characterization.

EE

EE
EE

= 25oC, VDD = 5V, V

A

Unless Otherwise Specified (Continued)

+ = 6V, VDD = 6V - 40 50 mA

REF

LE = Low, D0 - D7 = High - 100 220 µA
LE = Low, D0 - D7 = Low - - 100 µA
V

= 10MHz, 0V to 5V Square Wave - 20 - mA

OUT

V

= 10MHz, ±2.5V Square Wave - 25 - mA

OUT

+ = 4.608V, VSS = VEE = V

REF

REF

- = GND, LE Clocked at 20MHz, RL≥ 1 MΩ,

REF

- + 3 - V

EE

-V

200

DD

+ - 3 V

REF

- ppm/oC

V

Pin Descriptions

PIN NAME DESCRIPTION

1 D7 Most Significant Bit
2 D6 Input
3 D5 Data
4 D4 Bits
5 D3 (High = True)
6D2
7D1
8VSSDigital Ground
9D0Least Significant Bit. Input Data Bit

10 V
11 V
12 V
13 V
14 COMP Data Complement Control input. Active High
15 LE Latch Enable Input. Active Low
16 V

Analog Ground

EE

- Reference Voltage Negative Input

REF

Analog Output

OUT

+ Reference Voltage Positive Input

REF

Digital Power Supply, +5V

DD

Digital Signal Path

The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically

1.5V.
The 8 data bits, D0 (weighted 2

are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.

The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of V

and VSS, are shifted to operate between V

DD

and VEE. VEE optionally at ground or at a negative voltage,
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the V
and VEE supplies.

The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).

0

) through D7 (weighted 27),

DD

DD

10-14

CA3338, CA3338A

INPUT DATA

t

SU1

LATCHED LATCHED

LATCH

ENABLE

FIGURE 1. DATA TO LATCH ENABLE TIMING

INPUT

DAT A

LATCH

ENABLE

OUTPUT

VOLTAGE

FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING

t

W

DAT A

FEEDTHROUGH

t

D1

t

D2

90%

t

r

10%

t

t

S

t

H

SU2

1

/2 LSB

1

/2 LSB

Latch Operation

Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.

Non-clocked operation or changing data while LE is low is
not recommended for applications requiring low output
“glitch” energy: there is no guarantee of the simultaneous
changing of input data or the equal propagation delay of all
bits through the converter. Several parameters are given if
the converter is to be used in either of these modes: t
gives the delay from the input changing to the output chang­ing (10%), while t

and tH give the set up and hold times

SU2

(referred to LE rising edge) needed to latch data. See
Figures 1 and 2.

Clocked operation is needed for low “glitch” energy use.
Data must meet the given t
edge, and the t

hold time from the LE rising edge. The

H

delay to the output changing, t

set up time to the LE falling

SU1

, is now referred to the LE

D1

falling edge.

D2

In unipolar operation, V

- would typically be returned to

REF

analog ground, but may be raised abo v e g round (see specifi­cations). There is substantial code dependent current that
flows from V
specifications), so V

REF

+ to V

REF

REF

- (see V

+ input current in

REF

- should have a low impedance path

to ground.
In bipolar operation, V

voltage (the maximum voltage rating to V
observed). V

, which supplies the gate potential for the

EE

- would be returned to a negative

REF

must be

DD

output drivers, must be returned to a point at least as nega­tive as V

-. Note that the maximum clocking speed

REF

decreases when the bipolar mode is used.

Static Characteristics

The ideal 8-bit D/A would have an output equal to V
an input code of 00
equal to 255/256 of V
code of FF

(full scale output). The difference between the

HEX

(zero scale output), and an output

HEX

+ (referred to V

REF

-) with an input

REF

ideal and actual values of these two parameters are the OFF­SET and GAIN errors, respectively; see Figure 3.

If the code into an 8-bit D/A is changed by 1 count, the output
should change by 1/255 (full scale output - zero scale output). A
deviation from this step size is a differential linearity error, see
Figure 4. Note that the error is expressed in fractions of the
ideal step size (usually called an LSB). Also note that if the (-)
differential linearity error is less (in absolute numbers) than 1
LSB, the device is monotonic. (The output will always increase
for increasing code or decrease for decreasing code).

If the code into an 8-bit D/A is at any value, say “N”, the output
voltage should be N/255 of the full scale output (referred to the
zero scale output). Any deviation from that output is an integral
linearity error, usually expressed in LSBs . See Figure 4.

Note that OFFSET and GAIN errors do not affect integral
linearity, as the linearity is referenced to actual zero and full
scale outputs, not ideal. Absolute accuracy would have to
also take these errors into account.

­255/256

REF

+ - V

254/256

REF

253/256

= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE

GAIN ERROR

(SHOWN -)

REF

- with

There is no need for a square wave LE clock; LE must only
meet the minimum t

pulse width for successful latch opera-

W

tion. Generally, output timing (desired accuracy of settling)
sets the upper limit of usable clock frequency.

Output Structure

The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.

The “N” channel (pull down) transistor of each driver plus the
bottom “2R” resistor are returned to V
scale reference. The “P” channel (pull up) transistor of each
driver is returned to V

+, the (+) full-scale reference.

REF

- this is the (-) full-

REF

10-15

3/256

2/256

1/256

OUTPUT VOLTAGE AS A FRACTION OF V

OFFSET

ERROR

(SHOWN +)

0

00 01 02 03 FD FE FF

INPUT CODE IN HEXADECIMAL (COMP = LOW)

FIGURE 3. D/A OFFSET AND GAIN ERROR

CA3338, CA3338A

STRAIGHT LINE
FROM “0” SCALE
TO FULL SCALE

= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE

OUTPUT VOLTAGE

0

00

A

C

VOLTAGE

INTEGRAL LINEARITY

ERROR (SHOWN -)

B

A = IDEAL STEP SIZE (1/255 OF FULL

SCALE -“0” SCALE VOLTAGE)
B - A = +DIFFERENTIAL LINEARITY ERROR
C - A = -DIFFERENTIAL LINEARITY ERROR

INPUT CODE

FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY

ERROR

Dynamic Characteristics

Keeping the full-scale range (V
possible gives the best linearity and lowest “glitch” energy
(referred to 1V). This provides the best “P” and “N” channel
gate drives (hence saturation resistance) and propagation

REF

+ - V

-) as high as

REF

delays. The V

REF

+ (and V

- if bipolar) terminal should be

REF

well bypassed as near the chip as possible.
“Glitch” energy is defined as a spurious voltage that occurs as

the output is changed from one voltage to another. In a binary
input converter, it is usually highest at the most significant bit
transition (7F

HEX

to 80

for an 8 bit device), and can be

HEX

measured by displaying the output as the input code alter­nates around that point. The “glitch” energy is the area
between the actual output display and an ideal one LSB step
voltage (subtracting negative area from positive), at either the
positive or negative-going step . It is usually e xpressed in pV/s .

The CA3338 uses a modified R2R ladder, where the 3 most
significant bits drive a bar graph decoder and 7 equally
weighted resistors. This makes the “glitch” energy at each
scale transition (1F

HEX

to 20

HEX

, 3F

HEX

to 40

HEX

1

, etc.)
essentially equal, and far less than the MSB transition would
otherwise display.

For the purpose of comparison to other converters, the output
should be resistively divided to 1V full scale. Figure 5 shows a
typical hook-up for checking “glitch” energy or settling time.

The settling time of the A/D is mainly a function of the output
resistance (approximately 160Ω in parallel with the load resis­tance) and the load plus internal chip capacitance. Both
“glitch” energy and settling time measurements require very
good circuit and probe grounding: a probe tip connector such
as Tektronix part number 131-0258-00 is recommended.

/

8

CA3338

CLOCK

8 DATA BITS

+5V

DIGITAL

GROUND

1-7, 9

15

LE

D0 - D7

16

V

DD

+

14

COMP

8

V

SS

12

V

OUT

13

V

+

REF

11

-

V

REF

10

V

EE

+

+

+5V
+2.5V

-2.5V

R1

PROBE TIP
OR BNC
CONNECTOR

R2

FUNCTION CONNECTOR R1 R2 R3 V

Oscilloscope Display Probe Tip 82Ω 62Ω N/C 1V
Match 93Ω Cable BNC 75 160 93 1V
Match 75Ω Cable BNC 18 130 75 1V
Match 50Ω Cable BNC Short 75 50 0 79V

NOTES:

2. V

OUT(P-P)

is approximate, and will vary as R

of D/A varies.

OUT

3. All drawn capacitors are 0.1µF multilayer ceramic/4.7µF tantalum.

4. Dashed connections are for unipolar operation. Solid connection are for bipolar operation.

FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT

ANALOG
GROUND

OUT (P-P)

R3

REMOTE
V

OUT

10-16

CA3338

15

16

14

8

LE

D0 - D7

V

DD

COMP
V

SS

V

V

V

REF

REF

OUT

V

EE

+

-

CLOCK

8 DATA

BITS

+5V

1-7, 9

4.7µF

+

TAN

0.1µF
CER.

NOTES:

1. Both V

+pin and 392Ω resistor should be

REF

bypassed within1/4 inch.

2. Keep nodal capacitance at CA3450 pin 3 as
low as possible.

3. V

Range = ±3V at CA3450.

OUT

FIGURE 6. CA3338 AND CA3450 FOR DRIVING MULTIPLE COAXIAL LINES

CA3338, CA3338A

+6V

4.7µF TAN

+

0.1µF
CER.

12

+3.00V AT 25mA

392Ω

13

11
10

+

4.7µF TAN

1%

1kΩ

10kΩ

ADJUST
OFFSET

0.1µF CER.

7, 8

14

3

392Ω

1%

9

+
CA3450

-

4, 5, 12, 13

-6V

5pF

11

6

0.1µF CER.

+

4.7µF
TAN

UP TO 5 OUTPUT LINES
FOR R = 75Ω, 3 LINES
FOR R = 50Ω

R

V

= ±1.5V

OUT

R

PEAK

V

1

OUT

R

V

N

OUT

R

TABLE 1. OUTPUT VOLTAGE vs INPUT CODE AND V

V

+

REF

V

-

REF

STEP SIZE

5.12V
0

0.0200V

5.00V
0

0.0195V

4.608V
0

0.0180V

2.56V

-2.56V

0.0200V

REF

2.50V

-2.50V

0.0195V

Input Code
111111112 = FF
111111102 = FE-

HEX

HEX

5.1000V

5.0800

4.9805V

4.9610

4.5900V

4.5720

2.5400V

2.5200

2.4805V

2.4610

•

•

•

100000012 = 81
100000002 = 80
011111112 = 7F

HEX
HEX
HEX

2.5800

2.5600

2.5400

2.5195

2.5000

2.4805

2.3220

2.3040

2.2860

0.0200

0.0000

- 0.0200

0.0195

0.0000

-0.0195

•

•

•

000000012= 01
000000002= 00

HEX
HEX

0.0200

0.0000

0.0195

0.0000

0.0180

0.0000

-2.5400

-2.5600

-2.4805

-2.5000

Applications

The output of the CA3338 can be resistively divided to match a
doubly terminated 50Ω or 75Ω line, although peak-to-peak
swings of less than 1V may result. The output magnitude will
also vary with the converter’s output impedance. Figure 5
shows such an application. Note that because of the HCT input
structure, the CA3338 could be operated up to +7.5V V
V

+ supplies and still accept 0V to 5V CMOS input voltages.

REF

If larger voltage swings or better accuracy is desired, a high
speed output buffer, such as the HA-5033, HA-2542, or
CA3450, can be employed. Figure 6 shows a typical applica­tion, with the output capable of driving ±2V into multiple 50Ω
terminated lines.

DD

and

Operating and Handling Considerations

HANDLING

All inputs and outputs of CMOS devices have a network
for electrostatic protection during handling. Recom­mended handling practices for CMOS devices are
described in AN6525. “Guide to Better Handling and
Operation of CMOS Integrated Circuits.”

OPERATING

Operating Voltage

During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and turn-off transients, power supply ripple, or
ground noise; any of these conditions must not cause the
absolute maximum ratings to be exceeded.

Input Signals

To prevent damage to the input protection circuit, input
signals should never be greater than V
V

. Input currents must not exceed 20mA even when

SS

the power supply is off.

Unused Inputs

A connection must be provided at ev ery input terminal. All
unused input terminals must be connected to either V
or GND, whichever is appropriate.

nor less than

DD

CC

10-17