1
Standard ICs
8-bit compatible shift / store register
BU4094BC / BU4094BCF / BU4094BCFV
The BU4094BC, BU4094BCF, and BU4094BCFV are shift / store registers, each consisting of an 8-bit register and
an 8-bit latch.
As the data in the shift register can be latched by an asynchronous strobe input, it is possible to hold the output in
the data transfer mode.
The tri-state parallel output can be connected directly with an 8-bit bus line.
These registers are suitable for in-line / parallel data conversion, data receivers and other similar applications.
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Logic circuit diagram
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Truth table
8-STAGE
SHIFT REGISTER
IN
CLOCK
SERIAL
Q
S
Q'S
SERIAL
OUTPUT
PARALLEL OUTPUTS
8-BIT
LATCHES
STROBE
3-STATE
OUTPUTS
OUTPUT
ENABLE
Q1 Q8
CLOCK
OUTPUT
ENABLE
STROBE
Parallel output Serial output
Q
1 Qn QS
HH L L Q7 NC
HH H H Q
7 NC
HL XNCNCQ
7 NC
LX X ZZQ
7 NC
HX XNCNCNCQ
S
LX X ZZNCQS
Qn-1
Qn-1
SERIAL IN
Q'
S
NC: No Change Z: High Impedance X: Irrelevant
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Block diagram
2
SERIAL
IN
STROBE
Q
1
Q2
Q3
Q4
CLOCK
3
4
5
6
7
8
15
14
13
12
11
10
9
V
SS
1
OUTPUT
ENABLE
V
DD
Q6
Q7
Q8
Q'S
Q5
QS
16
2
Standard ICs BU4094BC / BU4094BCF / BU4094BCFV
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Absolute maximum ratings (Ta = 25°C)
Parameter Symbol Limits Unit
Power supply voltage V
DD V
Power dissipation mW
Operating temperature Topr °C
Storage temperature Tstg °C
Input voltage V
IN V – 0.5 ~ VDD + 0.5
Pd
– 0.5 ~ + 20
– 55 ~ + 150
– 40 ~ + 85
1000 (DIP), 500 (SOP)
400 (SSOP)
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Electrical characteristics
DC characteristics (unless otherwise noted, V
SS = 0V, Ta = 25°C)
Parameter Symbol Min. Typ. Max. Unit Conditions
V
DD (V)
Input high level voltage
Input low level voltage
Input high level current
Input low level current
Output high level voltage
Output low level voltage
Output high level current
Output low level current
Static current dissipation
Output high level
disable current
Output low level
disable current
V
IH
3.5 — —
V
5
—7.0 — — 10
11.0 — — 15
V
IL
— — 1.5
V
5
—— — 3.0 10
— — 4.0 15
I
IH — — 0.3 µA15VIH = 15V
I
IL — — – 0.3 µA15VIL = 0V
V
OH
4.95 — —
V
5
I
O = 0mA9.95 — — 10
14.95 — — 15
V
OL
— — 0.05
V
5
I
O = 0mA— — 0.05 10
— — 0.05 15
I
OH
– 0.44 — —
mA
5VOH = 4.6V
– 1.1 — — 10 V
OH = 9.5V
– 3.0 — — 15 V
OH = 13.5V
I
OL
0.44 — —
mA
5VOL = 0.4V
1.1 — — 10 V
OL = 0.5V
3.0 — — 15 V
OL = 1.5V
I
DD
IDH
——20
µA
µA
5
V
I = VDD, or GND
V
OUT = 15V
— — 40 10
——80
— — 1.0
15
15
I
DL µAVOUT = 0V— — – 1.0 15
3
Standard ICs BU4094BC / BU4094BCF / BU4094BCFV
Switching characteristics (unless otherwise noted, VSS = 0V, Ta = 25°C, CL = 50pF)
Parameter Symbol Min. Typ. Max. Unit Conditions
Measurement
circuit
t
TLH
— 100 — ns 5
— Fig.1— 50 — ns 10
— 40 — ns 15
t
THL
— 100 — ns 5
— Fig.1— 50 — ns 10
— 40 — ns 15
t
PLH
tPHL
— 350 600 ns 5
— Fig.1— 125 250 ns 10
— 95 190 ns 15
t
PLH
tPHL
— 230 460 ns 5
— Fig.1— 110 220 ns 10
— 75 150 ns 15
t
PLH
tPHL
— 420 840 ns 5
— Fig.1— 195 390 ns 10
— 135 270 ns 15
t
PLH
tPHL
— 290 580 ns 5
— Fig.1— 145 290 ns 10
— 100 200 ns 15
t
PHZ
tPZH
— 140 280 ns 5
R
L = 1kΩ Fig.2— 75 150 ns 10
— 55 110 ns 15
t
PLZ
tPZL
— 140 280 ns 5
R
L = 1kΩ Fig.2— 75 150 ns 10
— 55 110 ns 15
t
SU
— 20 125 ns 5
— Fig.1— 8 55 ns 10
— 6 35 ns 15
t
H
—1040ns 5
— Fig.1—1020ns 10
— 5 15 ns 15
t
W
— 100 200 ns 5
— Fig.1— 50 100 ns 10
—4080ns 15
t
r (CL)
tf (CL)
NO Limit
µs5
— Fig.1µs10
µs15
f
CL
1.25 5 — MHz 5
— Fig.12.5 10 — MHz 10
3.0 12.5 — MHz 15
t
WH
— 100 200 ns 5
— Fig.1—4080ns 10
—3570ns 15
C
IN —5—pF — — —
V
DD
(V)
Output rise time
Output fall time
Propagation delay
time, CLOCK to Qs
Propagation delay
time, CLOCK to Qs
Propagation delay
time, CLOCK to Qn
Propagation delay
time, STROBE to Qn
3-state propagation
delay time,
Output Enable to Qn
3-state propagation
delay time, Output
Enable to Qn
Minimum setup time,
DATA to CLOCK
Minimum hold time,
CLOCK to DATA
Minimum clock
pulse width
Maximum clock rise
time and fall time
Maximum clock
frequency
Minimum strobe
pulse width
Input capacitance
4
Standard ICs BU4094BC / BU4094BCF / BU4094BCFV
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Measurement circuits
50pF
OUTPUT
GND
P.G.
CLOCK
DATA
STROBE
OUTPUT
ENABLE
Fig. 1 Switching waveform
OUTPUT
GND
P.G.
CLOCK
DATA
STROBE
OUTPUT
ENABLE
1kΩ
50pF
SW
V
DD
A
B
A: tPLZ, tPZL
B: tPHZ, tPZH
Fig. 2 3-state delay time
90%90%
50%50%50%50%50%
10%
tr tf
50% 50%
tW
tHtSU
50%
50%50% 50%50%
t
WH
90%
50%
10% 10%
90%
90%
10%
50%
90%
10%
50%50%
50% 50%
t
PLH tPHL
tPLH
tPLH tPHL
50%
tPLH tPHZ tPLZ tPZLtPZH
tTLH tTHL
tPHL
CLOCK
DATA
STROBE
OUTPUT
ENABLE
Q
1 ~ Q8
Qs
Q's
Fig. 3 Switching time test waveform
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Electrical characteristic curve
POWER DISSIPATION: Pd (mW)
1200
1000
800
600
400
200
0
0 25 50 75 100 125 150
AMBIENT TEMPERATURE: Ta (°C)
SOP16
SSOP - B16
DIP16
Fig. 4 Power dissipation vs.
ambient temperature
5
Standard ICs BU4094BC / BU4094BCF / BU4094BCFV
BU4094BC BU4094BCF
BU4094BCFV
DIP16 SOP16
SSOP-B16
0.4 ± 0.11.27
0.15
0.15 ± 0.1
0.3Min.
4.4 ± 0.2
6.2 ± 0.3
0.11
1.5 ± 0.1
1
16
10.0 ± 0.2
8
9
9
8
16
1
0.1
6.4 ± 0.3
4.4 ± 0.2
5.0 ± 0.2
0.1
0.15 ± 0.1
0.22 ± 0.1
0.65
1.15 ± 0.1
0.3Min.
0.51Min.
0.3
± 0.1
916
81
6.5 ± 0.3
3.2
±
0.2
4.25
±
0.3
0.5 ± 0.1
19.4 ± 0.3
2.54
0° ~ 15°
7.62
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External dimensions (Units: mm)
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