Audio ICs
PLL frequency synthesizer for tuners
BU2616F
BU2616F PLL frequency synthesizers work up through the FM band.
Featuring low power dissipation and highly sensitive built-in RF amps, they detect intermediate frequencies.
Applications
Tuners (Mini components, radio cassette players, radio
equipment, etc.)
Features
1) Built-in high-speed prescaler can divide 130MHzVCO.
2) Low current dissipation (during operation: 6mA PLL
OFF: 1mA)
3) In addition to the standard FM and AM, also offers the
following 7 frequencies: 25kHz, 12.5kHz, 6.25kHz,
10kHz, 9kHz, 5kHz, and 1kHz.
4) SD (station detector) input circuit.
5) Intermediate frequency detection circuit
6) Charge pump output control circuit
7) Four output ports (Nch open drain).
8) Serial data input (CE, CK, DA)
Absolute maximum ratings (Ta = 25C)
Recommended operating conditions (Ta = 25C)
119
Audio ICs BU2616F
Block diagram
Pin descriptions
120
Audio ICs BU2616F
Electrical characteristics (unless otherwise noted, Ta = 25C, VDD1 = VDD2 = 5V)
Input data format
121
Audio ICs BU2616F
Input data format
Explanation of the data
(1) Division data: For D
0 through D15 (When S = 0, use D4 through D15.)
Example: S = 0, SW = 0
When divide ratio = 1000, the actual set value is 500 since it passes through 1/2 the circuit. This translates to 1F4 (H)
in HEX notation, and to (MSB) 0000 0001 1111 0100 (LSB) in binary notation. This data is used from LSB to D0 through
D15.
Example: S = 1, SW = 1
When divide ratio = 1000, the actual set value is 1000 since it does not pass through 1/2 the circuit. This translates to
3E8 (H) in HEX notation, and to (MSB) 0000 0011 1110 1000 (LSB) in binary notation. This data is used from LSB to
D0 through D15.
Example: S = 1, SW = 0
When divide ratio = 1000, D0 through D3 can be anything since it does not pass through the prescalar. This translates
to 3E8 (H) in HEX notation, and to (MSB) 0001 1111 0100 (LSB) in binary notation. This data is used from LSB to D0
through D15.
(2) Output port control data: P
0, P1, P2, P3
1: Nch open drain output ON
0: Nch open drain output OFF
0, R1, R2, standard frequency data
(3) R
(4) S: switch between FMIN and AMIN
0: FMIN
1: AMIN
122
(5) CT: Intermediate frequency measurement opera-
tion
1: Begins measurement.
0: Resets internal counter, IFIN goes to pulldown.
(6) L0, L1: Setting of IF frequency detection amplitude
Audio ICs BU2616F
(7) GT: Control of frequency measurement time
0: 32ms
1: 64ms
(8) SW: If this bit is set to ON while AMIN is
selected, swallow counter division is possible.
Intermediate frequency detection circuit and the
DO output.
(1) Structure (2) How the IF frequency detection circuit operates
External dimensions (Units: mm)
(9) PL PH: Control of charge pump output
PL = 0, PH = 0 PD1, PD2 go to PLL operation.
PL = 1, PH = 0 PD1, PD2 go to LO level.
PL = 0, PH = 1 PD1, PD2 go to HI level.
PL = 1, PH = 1 PD1, PD2 go to LO level.
(10) TS: Test data (0) is input
When control data CT is set to ON, the counter and the
amp go into operation. When CT equals 0, the amp input
pulldown counter is reset.
(3) Explanation of the DO
∗1 When the IF counter is OFF (CT = 0), SD input ap-
pears at the DO.
∗2 When the IF counter is set to ON (CT = 1), the con-
trol system keeps it at LO level until the measurement is finished.
∗3 After the measurement is finished, it goes to HI level
if it is within the range of input frequency settings,
and is kept at LO level if it is beyond the range of input frequency settings. When CT = 0, it returns to
the conditions described under paragraph ∗1.
123
Loading...